From patchwork Fri Apr 22 16:08:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Hoyes X-Patchwork-Id: 7042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 740D4C63697 for ; Fri, 22 Apr 2022 16:52:02 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10433.1650643760795888791 for ; Fri, 22 Apr 2022 09:09:21 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: peter.hoyes@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 47CF21FB; Fri, 22 Apr 2022 09:09:19 -0700 (PDT) Received: from e125920.arm.com (unknown [10.57.95.219]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 567B73F5A1; Fri, 22 Apr 2022 09:09:18 -0700 (PDT) From: Peter Hoyes To: meta-arm@lists.yoctoproject.org Cc: diego.sueiro@arm.com, Peter Hoyes Subject: [PATCH 1/6] arm/fvp-base-r-aem: Automatically download FVP tarball Date: Fri, 22 Apr 2022 17:08:55 +0100 Message-Id: <20220422160900.1861031-1-peter.hoyes@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 22 Apr 2022 16:52:02 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/3286 From: Peter Hoyes The FVP_Base_AEMv8R tarball is now available to download directly from developer.arm.com without logging in. Therefore, remove the FVP_BASE_R_AEM_TARBALL_URI env var (and references in the documentation) and update the SRC_URI in the recipe. Move fvpboot and userNetPorts to the machine conf, now that the FVP configuration is no longer dependent on an external tarball. Clarify the currently supported FVP version in the documentation. Put the current PV in the recipe filename. Issue-Id: SCM-4304 Signed-off-by: Peter Hoyes Change-Id: I776277c690bf4466445ca2df17eedb202f172f58 --- kas/fvp-baser-aemv8r64-bsp.yml | 3 --- .../conf/machine/fvp-baser-aemv8r64.conf | 2 ++ .../documentation/fvp-baser-aemv8r64.md | 20 +++++-------------- .../recipes-devtools/fvp/fvp-base-r-aem.bb | 17 ---------------- .../fvp/fvp-base-r-aem_11.17.21.bb | 10 ++++++++++ 5 files changed, 17 insertions(+), 35 deletions(-) delete mode 100644 meta-arm/recipes-devtools/fvp/fvp-base-r-aem.bb create mode 100644 meta-arm/recipes-devtools/fvp/fvp-base-r-aem_11.17.21.bb diff --git a/kas/fvp-baser-aemv8r64-bsp.yml b/kas/fvp-baser-aemv8r64-bsp.yml index 6871201..43ca36a 100644 --- a/kas/fvp-baser-aemv8r64-bsp.yml +++ b/kas/fvp-baser-aemv8r64-bsp.yml @@ -25,7 +25,6 @@ repos: meta-poky: env: - FVP_BASE_R_AEM_TARBALL_URI: "" FVP_BASE_R_ARM_EULA_ACCEPT: "False" local_conf_header: @@ -34,8 +33,6 @@ local_conf_header: PACKAGE_CLASSES = "package_ipk" PACKAGECONFIG:remove:pn-qemu-system-native = "gtk+ sdl" EXTRA_IMAGE_FEATURES:append = " debug-tweaks ssh-server-openssh" - FVP_CONFIG[bp.virtio_net.hostbridge.userNetPorts] ?= "8022=22" - IMAGE_CLASSES:append = " ${@oe.utils.ifelse(d.getVar('FVP_BASE_R_AEM_TARBALL_URI'), 'fvpboot', '')}" LICENSE_FLAGS_ACCEPTED:append = " ${@oe.utils.vartrue('FVP_BASE_R_ARM_EULA_ACCEPT', 'Arm-FVP-EULA', '', d)}" target: diff --git a/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf b/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf index db8c4fe..8646bdf 100644 --- a/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf +++ b/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf @@ -19,6 +19,7 @@ UBOOT_MACHINE ?= "vexpress_aemv8r_defconfig" SERIAL_CONSOLES = "115200;ttyAMA0" +IMAGE_CLASSES:append = " fvpboot" IMAGE_FSTYPES += "wic" WKS_FILE ?= "efi-disk.wks.in" EFI_PROVIDER ?= "grub-efi" @@ -61,6 +62,7 @@ FVP_CONFIG[gic_distributor.has-two-security-states] ?= "0" FVP_CONFIG[pctl.startup] ?= "0.0.0.*" FVP_CONFIG[bp.virtio_net.enabled] ?= "1" FVP_CONFIG[bp.virtio_net.hostbridge.userNetworking] ?= "1" +FVP_CONFIG[bp.virtio_net.hostbridge.userNetPorts] ?= "8022=22" FVP_CONFIG[bp.virtio_rng.enabled] ?= "1" FVP_CONFIG[bp.vis.rate_limit-enable] ?= "0" FVP_CONFIG[bp.refcounter.use_real_time] ?= "1" diff --git a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md index eeeb4fa..0b34d7f 100644 --- a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md +++ b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md @@ -27,6 +27,7 @@ The fvp-baser-aemv8r64 Yocto MACHINE supports the following BSP components, where either a standard or Real-Time Linux kernel (PREEMPT\_RT) can be built and run: + - FVP_Base_AEMv8R: v11.17.21 - boot-wrapper-aarch64: provides PSCI support - U-Boot: v2022.01 - provides UEFI services - Linux kernel: linux-yocto-5.15 @@ -104,20 +105,11 @@ is 3.0, install it like so: For more details on kas, see https://kas.readthedocs.io/. -To build the images for fvp-base machine, you also need to: +To build the images for the fvp-baser-aemv8r64 machine, you also need to accept +the EULA at +https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/end-user-license-agreement-for-fixed-virtual-platforms +by setting the following environment variable: - - download the ``FVP_Base_AEMv8R_11.17_21.tgz`` image AEM V8-R FVP Installer - (Linux) package from Arm's website: - https://silver.arm.com/download/download.tm?pv=4865959&p=4029857. You need - to have an account and be logged in to be able to download it - - set absolute path to the ``FVP_Base_AEMv8R_11.17_21.tgz`` downloaded - package in ``FVP_BASE_R_AEM_TARBALL_URI`` - - accept EULA in ``FVP_BASE_R_ARM_EULA_ACCEPT`` - - -The variables should be set like so: - - FVP_BASE_R_AEM_TARBALL_URI="file:///absolute/path/to/FVP_Base_AEMv8R_11.17_21.tgz" FVP_BASE_R_ARM_EULA_ACCEPT="True" **Note:** The host machine should have at least 50 GBytes of free disk space @@ -142,14 +134,12 @@ Fetch the meta-arm repository into a build directory: Building with the standard Linux kernel: cd ~/fvp-baser-aemv8r64-build - export FVP_BASE_R_AEM_TARBALL_URI="file:///absolute/path/to/FVP_Base_AEMv8R_11.17_21.tgz" export FVP_BASE_R_ARM_EULA_ACCEPT="True" kas build meta-arm/kas/fvp-baser-aemv8r64-bsp.yml Building with the Real-Time Linux kernel (PREEMPT\_RT): cd ~/fvp-baser-aemv8r64-build - export FVP_BASE_R_AEM_TARBALL_URI="file:///absolute/path/to/FVP_Base_AEMv8R_11.17_21.tgz" export FVP_BASE_R_ARM_EULA_ACCEPT="True" kas build meta-arm/kas/fvp-baser-aemv8r64-rt-bsp.yml diff --git a/meta-arm/recipes-devtools/fvp/fvp-base-r-aem.bb b/meta-arm/recipes-devtools/fvp/fvp-base-r-aem.bb deleted file mode 100644 index f21ccae..0000000 --- a/meta-arm/recipes-devtools/fvp/fvp-base-r-aem.bb +++ /dev/null @@ -1,17 +0,0 @@ -require fvp-envelope.inc - -SUMMARY = "Arm Fixed Virtual Platform - Armv8-R Base Architecture Envelope Model FVP" -LIC_FILES_CHKSUM = "file://license_terms/license_agreement.txt;md5=1a33828e132ba71861c11688dbb0bd16 \ - file://license_terms/third_party_licenses.txt;md5=41029e71051b1c786bae3112a29905a7" - -# This FVP cannot be downloaded directly, so download the Armv8-R Base AEM FVP -# yourself from the homepage and set FVP_BASE_R_AEM_TARBALL_URI appropriately -# (for example, file:///home/user/FVP_Base_AEMv8R_11.17_21.tgz). -FVP_BASE_R_AEM_TARBALL_URI ?= "" -PV = "11.17.21" - -SRC_URI = "${FVP_BASE_R_AEM_TARBALL_URI};subdir=${BP}" -python() { - if not d.getVar("FVP_BASE_R_AEM_TARBALL_URI"): - raise bb.parse.SkipRecipe("FVP_BASE_R_AEM_TARBALL_URI not set") -} diff --git a/meta-arm/recipes-devtools/fvp/fvp-base-r-aem_11.17.21.bb b/meta-arm/recipes-devtools/fvp/fvp-base-r-aem_11.17.21.bb new file mode 100644 index 0000000..06bc370 --- /dev/null +++ b/meta-arm/recipes-devtools/fvp/fvp-base-r-aem_11.17.21.bb @@ -0,0 +1,10 @@ +require fvp-envelope.inc + +SUMMARY = "Arm Fixed Virtual Platform - Armv8-R Base Architecture Envelope Model FVP" +LIC_FILES_CHKSUM = "file://license_terms/license_agreement.txt;md5=1a33828e132ba71861c11688dbb0bd16 \ + file://license_terms/third_party_licenses.txt;md5=41029e71051b1c786bae3112a29905a7" + +SRC_URI = "https://developer.arm.com/-/media/Files/downloads/ecosystem-models/${MODEL_CODE}_${PV_URL}.tgz;subdir=${BP}" +SRC_URI[sha256sum] = "483ec3c2c6569e3e7e0c4c46329662c0d19475dee8e8947c24fa3de4b00da488" + +MODEL_CODE = "FVP_Base_AEMv8R" From patchwork Fri Apr 22 16:08:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Hoyes X-Patchwork-Id: 7044 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7916AC63686 for ; Fri, 22 Apr 2022 16:52:02 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.10532.1650643778517566901 for ; Fri, 22 Apr 2022 09:09:39 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: peter.hoyes@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 133561FB; Fri, 22 Apr 2022 09:09:38 -0700 (PDT) Received: from e125920.arm.com (unknown [10.57.95.219]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2FC443F5A1; Fri, 22 Apr 2022 09:09:37 -0700 (PDT) From: Peter Hoyes To: meta-arm@lists.yoctoproject.org Cc: diego.sueiro@arm.com, Peter Hoyes Subject: [PATCH 2/6] ci,arm-bsp/conf: Add testimage for fvp-baser-aemv8r64 Date: Fri, 22 Apr 2022 17:08:56 +0100 Message-Id: <20220422160900.1861031-2-peter.hoyes@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220422160900.1861031-1-peter.hoyes@arm.com> References: <20220422160900.1861031-1-peter.hoyes@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 22 Apr 2022 16:52:02 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/3287 From: Peter Hoyes Add test configuration to machine config. Add testimage to Kas file, so that testimage works out of the box. Issue-Id: SCM-4304 Signed-off-by: Peter Hoyes Change-Id: I27dc9760a2c58f43ea557efdc97d363b0d3c1447 --- .gitlab-ci.yml | 5 +++++ kas/fvp-baser-aemv8r64-bsp.yml | 1 + meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf | 6 ++++++ meta-arm-bsp/documentation/fvp-baser-aemv8r64.md | 1 + 4 files changed, 13 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index bd1ae59..04d8754 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -108,6 +108,11 @@ fvp-base-arm32: fvp-baser-aemv8r64: extends: .build + parallel: + matrix: + - TESTING: testimage + tags: + - x86_64 fvps: extends: .build diff --git a/kas/fvp-baser-aemv8r64-bsp.yml b/kas/fvp-baser-aemv8r64-bsp.yml index 43ca36a..0958c9b 100644 --- a/kas/fvp-baser-aemv8r64-bsp.yml +++ b/kas/fvp-baser-aemv8r64-bsp.yml @@ -34,6 +34,7 @@ local_conf_header: PACKAGECONFIG:remove:pn-qemu-system-native = "gtk+ sdl" EXTRA_IMAGE_FEATURES:append = " debug-tweaks ssh-server-openssh" LICENSE_FLAGS_ACCEPTED:append = " ${@oe.utils.vartrue('FVP_BASE_R_ARM_EULA_ACCEPT', 'Arm-FVP-EULA', '', d)}" + IMAGE_CLASSES:append = " testimage" target: - core-image-minimal diff --git a/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf b/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf index 8646bdf..7e45ff8 100644 --- a/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf +++ b/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf @@ -31,6 +31,12 @@ MACHINE_FEATURES:append = " efi" PACKAGECONFIG:remove:pn-openssh = "rng-tools" MACHINE_EXTRA_RRECOMMENDS += "ssh-pregen-hostkeys" +# testimage configuration +TEST_TARGET = "OEFVPTarget" +TEST_SUITES = "ping ssh" +TEST_TARGET_IP ?= "127.0.0.1:8022" +TEST_SERVER_IP ?= "127.0.1.1" + FVP_EXTRA_ARGS = "-a cluster0*=${DEPLOY_DIR_IMAGE}/linux-system.axf" FVP_PROVIDER ?= "fvp-base-r-aem-native" FVP_EXE ?= "FVP_BaseR_AEMv8R" diff --git a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md index 0b34d7f..9880896 100644 --- a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md +++ b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md @@ -234,6 +234,7 @@ Known Issues and Limitations Change Log ---------- +- Enabled testimage support by default. - Added virtio\_rng to improve random number generation. - Added U-Boot v2022.01 for UEFI support. - Updated Linux kernel version from 5.14 to 5.15 for both standard and From patchwork Fri Apr 22 16:08:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Hoyes X-Patchwork-Id: 7046 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A16CC6369B for ; Fri, 22 Apr 2022 16:52:02 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.10720.1650643780278850910 for ; Fri, 22 Apr 2022 09:09:40 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: peter.hoyes@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5CB21FB; Fri, 22 Apr 2022 09:09:39 -0700 (PDT) Received: from e125920.arm.com (unknown [10.57.95.219]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 097FF3F5A1; Fri, 22 Apr 2022 09:09:38 -0700 (PDT) From: Peter Hoyes To: meta-arm@lists.yoctoproject.org Cc: diego.sueiro@arm.com, Peter Hoyes Subject: [PATCH 3/6] arm-bsp/boot-wrapper-aarch64,u-boot: Clarify fvp-baser Upstream-Status Date: Fri, 22 Apr 2022 17:08:57 +0100 Message-Id: <20220422160900.1861031-3-peter.hoyes@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220422160900.1861031-1-peter.hoyes@arm.com> References: <20220422160900.1861031-1-peter.hoyes@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 22 Apr 2022 16:52:02 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/3288 From: Peter Hoyes The final firmware design for the fvp-baser-aemv8r64 is pending further discussion, so the current implementation contains several "temporary" patches which are likely to be removed or replaced in the future. These are already marked as "Inappropriate" to upstream, but amend the reason to "Implementation pending further discussion" to avoid confusion. Issue-Id: SCM-4304 Signed-off-by: Peter Hoyes Change-Id: I7dc6eae73fbb18f4b7b63540fb45b6a62d455093 --- .../0008-aarch64-Disable-CNTPCT_EL0-trap-for-v8-R64.patch | 2 +- .../files/fvp-baser-aemv8r64/0009-lds-Mark-the-mem-range.patch | 2 +- .../fvp-baser-aemv8r64/0010-common-Introduce-the-libfdt.patch | 2 +- .../0011-common-Add-essential-libc-functions.patch | 2 +- .../0012-Makefile-Add-the-libfdt-to-the-Makefile-system.patch | 2 +- .../fvp-baser-aemv8r64/0013-platform-Add-print_hex-func.patch | 2 +- .../0014-common-Add-mem-usage-to-memreserve.patch | 2 +- .../0015-boot-Add-the-enable-keep-el-compile-option.patch | 2 +- .../0006-armv8-Add-ARMv8-MPU-configuration-logic.patch | 2 +- ...7-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch | 2 +- .../0008-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch | 2 +- ...9-armv8-Make-disabling-HVC-configurable-when-switching.patch | 2 +- .../0010-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch | 2 +- .../0011-vexpress64-Add-BASER_FVP-vexpress-board-variant.patch | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0008-aarch64-Disable-CNTPCT_EL0-trap-for-v8-R64.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0008-aarch64-Disable-CNTPCT_EL0-trap-for-v8-R64.patch index a14e54a..2ce28b7 100644 --- a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0008-aarch64-Disable-CNTPCT_EL0-trap-for-v8-R64.patch +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0008-aarch64-Disable-CNTPCT_EL0-trap-for-v8-R64.patch @@ -16,7 +16,7 @@ FEAT_VHE. We can simply set CNTHCTL_EL2.EL1PCTEN to 1. Issue-ID: SCM-3508 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Jaxson Han Change-Id: I4147e66341c8153312021e6f2ab67d0037246da1 --- diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0009-lds-Mark-the-mem-range.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0009-lds-Mark-the-mem-range.patch index 3d4fec8..0c310eb 100644 --- a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0009-lds-Mark-the-mem-range.patch +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0009-lds-Mark-the-mem-range.patch @@ -9,7 +9,7 @@ calculate the mem range of boot-wrapper and then set the range to Issue-ID: SCM-3815 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Jaxson Han Change-Id: Idc5a2894e193c75381049a0f359b4b2a51c567ee --- diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0010-common-Introduce-the-libfdt.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0010-common-Introduce-the-libfdt.patch index e0496dc..0305f8b 100644 --- a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0010-common-Introduce-the-libfdt.patch +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0010-common-Introduce-the-libfdt.patch @@ -15,7 +15,7 @@ We choose BSD because the boot-wrapper is under BSD. Issue-Id: SCM-3814 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Jaxson Han Change-Id: Iec2f469053c8ac0ed38838c597b21a42bdf67b38 --- diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0011-common-Add-essential-libc-functions.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0011-common-Add-essential-libc-functions.patch index aa05a72..871a178 100644 --- a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0011-common-Add-essential-libc-functions.patch +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0011-common-Add-essential-libc-functions.patch @@ -13,7 +13,7 @@ terms of BSD license. It is the same with boot-wrapper. Issue-Id: SCM-3814 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Jaxson Han Change-Id: If3b55b00afa8694c7522df989a41e0b38eda1d38 --- diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0012-Makefile-Add-the-libfdt-to-the-Makefile-system.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0012-Makefile-Add-the-libfdt-to-the-Makefile-system.patch index eeddaac..5917ef2 100644 --- a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0012-Makefile-Add-the-libfdt-to-the-Makefile-system.patch +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0012-Makefile-Add-the-libfdt-to-the-Makefile-system.patch @@ -9,7 +9,7 @@ compile. Add -fno-stack-protector to fix it. Issue-Id: SCM-3814 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Jaxson Han Change-Id: I472bc28cdc5cde3b22461a4b7d7a3752ae382b4b --- diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0013-platform-Add-print_hex-func.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0013-platform-Add-print_hex-func.patch index 7d643ff..136e18e 100644 --- a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0013-platform-Add-print_hex-func.patch +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0013-platform-Add-print_hex-func.patch @@ -8,7 +8,7 @@ numbers. Issue-Id: SCM-3814 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Jaxson Han Change-Id: Ic960345d9ef0b41d81d30c4a4dbd9c31139907c4 --- diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0014-common-Add-mem-usage-to-memreserve.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0014-common-Add-mem-usage-to-memreserve.patch index f5263d2..ea51816 100644 --- a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0014-common-Add-mem-usage-to-memreserve.patch +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0014-common-Add-mem-usage-to-memreserve.patch @@ -8,7 +8,7 @@ services with libfdt. Issue-Id: SCM-3815 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Jaxson Han Change-Id: I2ea80cdf736a910fa2c3deb622e21d50f04be960 --- diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0015-boot-Add-the-enable-keep-el-compile-option.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0015-boot-Add-the-enable-keep-el-compile-option.patch index 6c708e9..0411ef0 100644 --- a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0015-boot-Add-the-enable-keep-el-compile-option.patch +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0015-boot-Add-the-enable-keep-el-compile-option.patch @@ -12,7 +12,7 @@ Linux PSCI, this option will cause secondary cores booting at EL1. Issue-Id: SCM-3813 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Jaxson Han Change-Id: I3ba9c87cf0b59d163ca433f74c9e3a46e5ca2c63 --- diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-armv8-Add-ARMv8-MPU-configuration-logic.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-armv8-Add-ARMv8-MPU-configuration-logic.patch index 6e708e1..08cfa26 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-armv8-Add-ARMv8-MPU-configuration-logic.patch +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-armv8-Add-ARMv8-MPU-configuration-logic.patch @@ -16,7 +16,7 @@ board configurations. Issue-Id: SCM-2443 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: I0ee3879f9d7f03fe940664b3551c68eeaa458d17 --- diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch index 1000123..4c567dc 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch @@ -16,7 +16,7 @@ that both config flags be be targeted using CONFIG_IS_ENABLED. Issue-Id: SCM-3728 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: I0cf0fc6d7ef4d45791411cf1f67c65e198cc8b2b --- diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch index 046636b..8cbd1f8 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch @@ -13,7 +13,7 @@ option. Issue-Id: SCM-3728 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: If98478148d6d8d1f732acac5439276700614815f --- diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Make-disabling-HVC-configurable-when-switching.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Make-disabling-HVC-configurable-when-switching.patch index b12e018..f1d35d5 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Make-disabling-HVC-configurable-when-switching.patch +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Make-disabling-HVC-configurable-when-switching.patch @@ -12,7 +12,7 @@ control whether to disable HVC exceptions in HCR_EL2->HCD Issue-Id: SCM-3728 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: I463d82f1db8a3cafcab40a9c0c208753569cc300 --- diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0010-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0010-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch index 2912070..e63b28d 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0010-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0010-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch @@ -11,7 +11,7 @@ providing PSCI services). Issue-Id: SCM-3728 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: I137473d721e58e4c348b9641f5b9778178d3bb65 --- diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0011-vexpress64-Add-BASER_FVP-vexpress-board-variant.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0011-vexpress64-Add-BASER_FVP-vexpress-board-variant.patch index 36e820c..8a99063 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0011-vexpress64-Add-BASER_FVP-vexpress-board-variant.patch +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0011-vexpress64-Add-BASER_FVP-vexpress-board-variant.patch @@ -19,7 +19,7 @@ inverted from the BASE_FVP Issue-Id: SCM-3728 Upstream-Status: Inappropriate [other] - Temporary patch + Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: Id173e52afad473abcf3f61c6bf374fc31f17edd3 --- From patchwork Fri Apr 22 16:08:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Hoyes X-Patchwork-Id: 7047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89F49C636C8 for ; Fri, 22 Apr 2022 16:52:02 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.10743.1650643782310551838 for ; Fri, 22 Apr 2022 09:09:42 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: peter.hoyes@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E120F1FB; Fri, 22 Apr 2022 09:09:41 -0700 (PDT) Received: from e125920.arm.com (unknown [10.57.95.219]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A54EC3F5A1; Fri, 22 Apr 2022 09:09:40 -0700 (PDT) From: Peter Hoyes To: meta-arm@lists.yoctoproject.org Cc: diego.sueiro@arm.com, Peter Hoyes Subject: [PATCH 4/6] arm-bsp/boot-wrapper-aarch64: Add fvp-baser support for EL2 SMP payloads Date: Fri, 22 Apr 2022 17:08:58 +0100 Message-Id: <20220422160900.1861031-4-peter.hoyes@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220422160900.1861031-1-peter.hoyes@arm.com> References: <20220422160900.1861031-1-peter.hoyes@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 22 Apr 2022 16:52:02 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/3289 From: Peter Hoyes Add additional fvp-baser-aemv8r64-specific patches for boot-wrapper-aarch64. These patches add a "function call" entry point for the PSCI services, so that payloads starting at S-EL2 (e.g. Xen) can boot the secondary cores. Issue-ID: SCM-4386 Signed-off-by: Peter Hoyes Change-Id: I961c78352987f711664e06ab39b00f6eb97a81de --- .../documentation/fvp-baser-aemv8r64.md | 1 + ...oot-wrapper-aarch64-fvp-baser-aemv8r64.inc | 5 + ...lush-cache-after-setting-branch_data.patch | 52 +++ ...8-PSCI-Add-function-call-entry-point.patch | 74 ++++ ...-lds-Rearrange-and-mark-the-sections.patch | 61 ++++ ...n-Provide-firmware-info-using-libfdt.patch | 345 ++++++++++++++++++ ...-Enable-firmware-node-initialization.patch | 98 +++++ 7 files changed, 636 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0017-PSCI-Apply-flush-cache-after-setting-branch_data.patch create mode 100644 meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0018-PSCI-Add-function-call-entry-point.patch create mode 100644 meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0019-lds-Rearrange-and-mark-the-sections.patch create mode 100644 meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0020-common-Provide-firmware-info-using-libfdt.patch create mode 100644 meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0021-boot-Enable-firmware-node-initialization.patch diff --git a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md index 9880896..4cd18f0 100644 --- a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md +++ b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md @@ -234,6 +234,7 @@ Known Issues and Limitations Change Log ---------- +- Added boot-wrapper-aarch64 support for booting SMP payloads at S-EL2. - Enabled testimage support by default. - Added virtio\_rng to improve random number generation. - Added U-Boot v2022.01 for UEFI support. diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/boot-wrapper-aarch64-fvp-baser-aemv8r64.inc b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/boot-wrapper-aarch64-fvp-baser-aemv8r64.inc index 6bc7385..8ffa0aa 100644 --- a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/boot-wrapper-aarch64-fvp-baser-aemv8r64.inc +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/boot-wrapper-aarch64-fvp-baser-aemv8r64.inc @@ -18,6 +18,11 @@ SRC_URI:append = " \ file://0014-common-Add-mem-usage-to-memreserve.patch \ file://0015-boot-Add-the-enable-keep-el-compile-option.patch \ file://0016-Makefile-Change-COUNTER_FREQ-to-100-MHz.patch \ + file://0017-PSCI-Apply-flush-cache-after-setting-branch_data.patch \ + file://0018-PSCI-Add-function-call-entry-point.patch \ + file://0019-lds-Rearrange-and-mark-the-sections.patch \ + file://0020-common-Provide-firmware-info-using-libfdt.patch \ + file://0021-boot-Enable-firmware-node-initialization.patch \ " BOOT_WRAPPER_AARCH64_CMDLINE = "\ diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0017-PSCI-Apply-flush-cache-after-setting-branch_data.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0017-PSCI-Apply-flush-cache-after-setting-branch_data.patch new file mode 100644 index 0000000..8d981f5 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0017-PSCI-Apply-flush-cache-after-setting-branch_data.patch @@ -0,0 +1,52 @@ +From 6923f2a0c59cf92ba5ad50ec1d658a357b4ba5d7 Mon Sep 17 00:00:00 2001 +From: Jaxson Han +Date: Tue, 2 Nov 2021 10:48:39 +0800 +Subject: [PATCH] PSCI: Apply flush cache after setting branch_data + +For v8-R64, Hypervisor calls boot-wrapper's PSCI service using simple +function call (instead of hvc). + +In this case, hypervisor's main core has enabled MPU and cache, but +the secondary cores which are spinning have not enabled cache. +That means if the main core set the branch_data to 1 to boot other +cores, the secondary cores cannot see the change of branch_data and +also cannot break the spin. + +Thus, the PSCI service in boot-wrapper needs a cache flush after +setting branch_data in order to let other cores see the change. + +Issue-ID: SCM-3816 +Upstream-Status: Inappropriate [other] + Implementation pending further discussion +Signed-off-by: Jaxson Han +Change-Id: Ifc282091c54d8fb2ffdb8cfa7fd3ffc1f4be717e +--- + common/psci.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/common/psci.c b/common/psci.c +index 945780b..6efc695 100644 +--- a/common/psci.c ++++ b/common/psci.c +@@ -24,12 +24,18 @@ static unsigned long branch_table[NR_CPUS]; + + bakery_ticket_t branch_table_lock[NR_CPUS]; + ++static inline void flush_per_cpu_data(void *data) ++{ ++ asm volatile ("dc cvac, %0" : : "r" (data)); ++} ++ + static int psci_store_address(unsigned int cpu, unsigned long address) + { + if (branch_table[cpu] != PSCI_ADDR_INVALID) + return PSCI_RET_ALREADY_ON; + + branch_table[cpu] = address; ++ flush_per_cpu_data((void*)&(branch_table[cpu])); + return PSCI_RET_SUCCESS; + } + +-- +2.25.1 + diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0018-PSCI-Add-function-call-entry-point.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0018-PSCI-Add-function-call-entry-point.patch new file mode 100644 index 0000000..97cd3cb --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0018-PSCI-Add-function-call-entry-point.patch @@ -0,0 +1,74 @@ +From ed46e83df2400b1b3f3364169aacf787bd91bd45 Mon Sep 17 00:00:00 2001 +From: Jaxson Han +Date: Tue, 25 Jan 2022 14:56:36 +0800 +Subject: [PATCH] PSCI: Add function call entry point + +The max exception level of Armv8R AArch64 is EL2, which means it has no +exclusive EL for firmware. That is, firmware and hypervisors have to share +the EL2. Also, hypervisors cannot call firmware services via a 'smc' +instruction. Thus, boot-wrapper has to provide a function entry point +for Armv8R AArch64. + +Issue-Id: SCM-3816 +Upstream-Status: Inappropriate [other] + Implementation pending further discussion +Signed-off-by: Jaxson Han +Change-Id: I06ec8e50298603155c6d8ae2330e71db2f111182 +--- + common/psci.c | 24 ++++++++++++++++++++---- + 1 file changed, 20 insertions(+), 4 deletions(-) + +diff --git a/common/psci.c b/common/psci.c +index 6efc695..8fdefb5 100644 +--- a/common/psci.c ++++ b/common/psci.c +@@ -20,6 +20,8 @@ + + extern unsigned int spsr_to_elx; + ++unsigned long flag_from_smc_fn[NR_CPUS]; ++ + static unsigned long branch_table[NR_CPUS]; + + bakery_ticket_t branch_table_lock[NR_CPUS]; +@@ -49,12 +51,14 @@ static int psci_cpu_on(unsigned long target_mpidr, unsigned long address) + return PSCI_RET_INVALID_PARAMETERS; + + bakery_lock(branch_table_lock, this_cpu); +- ret = psci_store_address(cpu, address); +- bakery_unlock(branch_table_lock, this_cpu); +- + #ifdef KEEP_EL +- spsr_to_elx = SPSR_KERNEL_EL1; ++ if (!flag_from_smc_fn[this_cpu]) { ++ spsr_to_elx = SPSR_KERNEL_EL1; ++ flush_per_cpu_data((void*)&(spsr_to_elx)); ++ } + #endif ++ ret = psci_store_address(cpu, address); ++ bakery_unlock(branch_table_lock, this_cpu); + + return ret; + } +@@ -90,6 +94,18 @@ long psci_call(unsigned long fid, unsigned long arg1, unsigned long arg2) + } + } + ++long smc_fn_entry(unsigned long fid, unsigned long arg1, unsigned long arg2) ++{ ++ long ret; ++ unsigned int this_cpu = this_cpu_logical_id(); ++ ++ flag_from_smc_fn[this_cpu] = 1; ++ ret = psci_call(fid, arg1, arg2); ++ flag_from_smc_fn[this_cpu] = 0; ++ ++ return ret; ++} ++ + void __noreturn psci_first_spin(unsigned int cpu) + { + if (cpu == MPIDR_INVALID) +-- +2.25.1 + diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0019-lds-Rearrange-and-mark-the-sections.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0019-lds-Rearrange-and-mark-the-sections.patch new file mode 100644 index 0000000..1f10209 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0019-lds-Rearrange-and-mark-the-sections.patch @@ -0,0 +1,61 @@ +From 36b5fa3f4db49ac7aef42ff1d58a895226c7e96c Mon Sep 17 00:00:00 2001 +From: Jaxson Han +Date: Tue, 2 Nov 2021 15:10:28 +0800 +Subject: [PATCH] lds: Rearrange and mark the sections + +To make it possible for the next stage to protect sections with MPU, +boot-wrapper needs to provide the text and data section information. +By rearranging the .data .rodata and .vector sections, all sections +can be split into 2 big sections: + - RO and Executable + - RW and Non-Executable +Add firmware_data to mark the boundry, thus: +firmware_start to firmware_data - 1 indicates RO and Executable section, +firmware_data to firmware_end - 1 indicates RW and Non-Executable +section. + +Also, the firmware_data and firmware_end should align with 64 bytes, +since Armv8R AArch64 MPU requires it. + +Issue-ID: SCM-3816 +Upstream-Status: Inappropriate [other] + Implementation pending further discussion +Signed-off-by: Jaxson Han +Change-Id: I55342aa7492f2c7b5c16ab9a6472c8cb45cff8fd +--- + model.lds.S | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/model.lds.S b/model.lds.S +index ab98ddf..85451f9 100644 +--- a/model.lds.S ++++ b/model.lds.S +@@ -63,12 +63,16 @@ SECTIONS + } + #endif + ++#define FIRMWARE_ALIGN . = ALIGN(1 << 6) + .boot PHYS_OFFSET: { + PROVIDE(firmware_start = .); + *(.init) + *(.text*) +- *(.data* .rodata* .bss* COMMON) + *(.vectors) ++ *(.rodata*) ++ FIRMWARE_ALIGN; ++ PROVIDE(firmware_data = .); ++ *(.data* .bss* COMMON) + *(.stack) + PROVIDE(etext = .); + } +@@ -77,6 +81,7 @@ SECTIONS + mbox = .; + QUAD(0x0) + } ++ FIRMWARE_ALIGN; + PROVIDE(firmware_end = .); + + ASSERT(etext <= (PHYS_OFFSET + TEXT_LIMIT), ".text overflow!") +-- +2.25.1 + diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0020-common-Provide-firmware-info-using-libfdt.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0020-common-Provide-firmware-info-using-libfdt.patch new file mode 100644 index 0000000..cafcc09 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0020-common-Provide-firmware-info-using-libfdt.patch @@ -0,0 +1,345 @@ +From 8bdbb64d13f14d40546b71dbcfee2b2a8ea002a5 Mon Sep 17 00:00:00 2001 +From: Jaxson Han +Date: Wed, 29 Dec 2021 15:17:38 +0800 +Subject: [PATCH] common: Provide firmware info using libfdt + +Boot-wrapper uses libfdt to provide more info in device tree. +We add a new node to include those new firmware relevant infomation. +The new node defined as follows: + fw-shared-info { + compatible = "firmware,shared_info"; + + #address-cells = <0x02>; + #size-cells = <0x02>; + + version = "1.0"; + regions = ; + regions-permission = "RX", "R", "RWX", "RW"; + regions-cache = "Cache", "NCache", "Cache", "Device" + + function_entry = ; + }; +The node path is /fw-shared-info. +For boot-wrapper, in real case, it will be: + fw-shared-info { + compatible = "firmware,shared_info"; + + #address-cells = <0x02>; + #size-cells = <0x02>; + + version = "1.0"; + regions = <0x0 firmware_start 0x0 firmware_code_size + 0x0 firmware_data 0x0 firmware_data_size>; + regions-permission = "RX", "RW"; + regions-cache = "Cache", "Cache"; + + function_entry = <0x0 smc_fn_entry>; + }; + +Issue-Id: SCM-3816 +Upstream-Status: Inappropriate [other] + Implementation pending further discussion +Signed-off-by: Jaxson Han +Change-Id: I6ebc59ce2bd3939b0fe066720d57821eaa1bed27 +--- + common/device_tree.c | 271 ++++++++++++++++++++++++++++++++++++++++++- + 1 file changed, 270 insertions(+), 1 deletion(-) + +diff --git a/common/device_tree.c b/common/device_tree.c +index 4d0876c..7f7befc 100644 +--- a/common/device_tree.c ++++ b/common/device_tree.c +@@ -8,13 +8,225 @@ + */ + #include + ++#define DEVICE_TREE_DEBUG 1 ++ ++#define FW_NODE_NAME "/fw-shared-info" ++#define FW_COMPAT "firmware,shared_info" ++#define FW_INFO_VER "1.0" ++ ++#ifdef BOOTWRAPPER_32 ++#define CELL_NUM 1 ++#define VAL_TYPE uint32_t ++#else ++#define CELL_NUM 2 ++#define VAL_TYPE uint64_t ++#endif ++ ++#define ALIGN(x) (((x) + (FDT_TAGSIZE) - 1) & ~((FDT_TAGSIZE) - 1)) ++ + extern unsigned long dtb; +-extern char firmware_start[], firmware_end[]; ++extern char firmware_start[], firmware_data[], firmware_end[]; ++ ++extern long smc_fn_entry(unsigned long, unsigned long, unsigned long); + + extern void print_string(const char *str); ++extern void print_hex(unsigned int val); + + static void *blob; + ++static char *realloc_node(char *fdt, const char *name) ++{ ++ int delta; ++ int new_sz; ++ /* FDT_BEGIN_NODE, node name in off_struct and FDT_END_NODE */ ++ delta = sizeof(struct fdt_node_header) + ALIGN(strlen(name) + 1) ++ + FDT_TAGSIZE; ++ new_sz = fdt_totalsize(fdt) + delta; ++ fdt_open_into(fdt, fdt, new_sz); ++ return fdt; ++} ++ ++static int create_node(const char *node_name) ++{ ++ int node = 0; ++ char *p; ++ ++ p = strrchr(node_name, '/'); ++ if (!p) { ++ print_string("node name without '/'\r\n"); ++ return -1; ++ } ++ *p = '\0'; ++ ++ blob = realloc_node(blob, p + 1); ++ ++ if (p > node_name) { ++ node = fdt_path_offset(blob, node_name); ++ if (node < 0) { ++ print_string("no node name\r\n"); ++ return -1; ++ } ++ } ++ ++ node = fdt_add_subnode(blob, node, p + 1); ++ if (node < 0) { ++ print_string("add subnode err\r\n"); ++ return -1; ++ } ++ ++ return node; ++} ++ ++static int dt_create_fw_node(void) { ++ int fw_node; ++ ++ fw_node = fdt_path_offset(blob, FW_NODE_NAME); ++ ++ if(fw_node < 0) { ++ fw_node = create_node(FW_NODE_NAME); ++ } ++ ++ return fw_node; ++} ++ ++static char *realloc_property(char *fdt, int nodeoffset, const char *name, ++ int newlen) ++{ ++ int delta = 0; ++ int oldlen = 0; ++ int new_sz; ++ ++ if (!fdt_get_property(fdt, nodeoffset, name, &oldlen)) ++ delta = sizeof(struct fdt_property) + strlen(name) + 1; ++ ++ if (newlen > oldlen) ++ delta += ALIGN(newlen) - ALIGN(oldlen); ++ ++ new_sz = fdt_totalsize(fdt) + delta; ++ fdt_open_into(fdt, fdt, new_sz); ++ return fdt; ++} ++ ++static void dt_set_prop(int node, char *property, void *buf, int len) ++{ ++ int err; ++ ++ err = fdt_setprop(blob, node, property, buf, len); ++ if (err == -FDT_ERR_NOSPACE) { ++ blob = realloc_property(blob, node, property, len); ++ err = fdt_setprop(blob, node, property, buf, len); ++ } ++ if (err) { ++ print_string("fdt error\n\r"); ++ } ++} ++ ++static void dt_set_prop_u32(int node, char *property, uint32_t val) ++{ ++ fdt32_t fdt_val = cpu_to_fdt32(val); ++ int len = sizeof(fdt32_t); ++ ++ dt_set_prop(node, property, (void*)&fdt_val, len); ++} ++ ++static void dt_set_prop_u64(int node, char *property, uint64_t val) ++{ ++ fdt64_t fdt_val = cpu_to_fdt64(val); ++ int len = sizeof(fdt64_t); ++ ++ dt_set_prop(node, property, (void*)&fdt_val, len); ++} ++ ++/* This dt_set_prop_u32_array maybe unused according to the BOOTWRAPPER_32 */ ++__attribute__((unused)) ++static void dt_set_prop_u32_array(int node, char *property, uint32_t *vals, ++ int size) ++{ ++ fdt32_t *fdt_vals = (fdt32_t*)vals; ++ int len = sizeof(fdt32_t) * size; ++ ++ for (int i = 0; i < size; i++) { ++ fdt_vals[i] = cpu_to_fdt32(vals[i]); ++ } ++ ++ dt_set_prop(node, property, (void*)fdt_vals, len); ++} ++ ++static void dt_set_prop_u64_array(int node, char *property, uint64_t *vals, ++ int size) ++{ ++ fdt64_t *fdt_vals = (fdt64_t*)vals; ++ int len = sizeof(fdt64_t) * size; ++ ++ for (int i = 0; i < size; i++) { ++ fdt_vals[i] = cpu_to_fdt64(vals[i]); ++ } ++ ++ dt_set_prop(node, property, (void*)fdt_vals, len); ++} ++ ++#if DEVICE_TREE_DEBUG ++static void dt_dump_string(const void *s, int len) ++{ ++ char *sub = (char*)s; ++ int sublen; ++ while(*sub && ((uint64_t)sub - (uint64_t)s) < len) { ++ sublen = strlen(sub) + 1; ++ print_string(sub); ++ print_string(" "); ++ sub += sublen; ++ } ++ print_string("\n\r"); ++} ++ ++static void dt_dump_fdt32_array(const void *vals, int len) ++{ ++ fdt32_t *fdt_vals = (fdt32_t*)vals; ++ len = len / sizeof(fdt32_t); ++ for (int i = 0; i < len; i++) { ++ print_hex(fdt32_to_cpu(fdt_vals[i])); ++ print_string(" "); ++ } ++ print_string("\n\r"); ++} ++ ++static void dt_dump(int node, char *property, char type) ++{ ++ const void *val; ++ int len; ++ ++ val = fdt_getprop(blob, node, property, &len); ++ print_string(property); ++ print_string(": "); ++ ++ if (type == 's') { ++ /* string type */ ++ dt_dump_string(val, len); ++ return; ++ } ++ ++ /* uint type */ ++ dt_dump_fdt32_array(val, len); ++} ++ ++void dt_dump_all(int node) ++{ ++ if (node >= 0) { ++ print_string(FW_NODE_NAME" info:\r\n"); ++ dt_dump(node, "compatible", 's'); ++ dt_dump(node, "version", 's'); ++ dt_dump(node, "function_entry", 'i'); ++ dt_dump(node, "address-cells", 'i'); ++ dt_dump(node, "size-cells", 'i'); ++ dt_dump(node, "regions", 'i'); ++ dt_dump(node, "regions-permission", 's'); ++ dt_dump(node, "regions-cache", 's'); ++ print_string("\r\n"); ++ } ++} ++#else ++void dt_dump_all(int node) { (void*)node; return; } ++#endif + + void dt_add_memreserve(void) + { +@@ -32,3 +244,60 @@ void dt_add_memreserve(void) + print_string("reserve mem add err\n\r"); + } + } ++ ++void dt_fw_node_init(int enable) ++{ ++ int fw_node; ++ ++ VAL_TYPE regions[] = { ++ /* code region: start, end, ro, x, cachable */ ++ (VAL_TYPE)firmware_start, ++ (VAL_TYPE)(firmware_data - firmware_start), ++ /* data region: start, end, rw, xn, cachable */ ++ (VAL_TYPE)firmware_data, ++ (VAL_TYPE)(firmware_end - firmware_data), ++ }; ++ int regions_num = sizeof(regions) / sizeof(VAL_TYPE); ++ char regions_permission[] = "RX\0RW"; ++ char regions_cache[] = "Cache\0Cache"; ++ ++ if (!enable) ++ return; ++ ++ print_string("Prepare "FW_NODE_NAME" node\n\r"); ++ ++ blob = (void*)&dtb; ++ ++ if(fdt_path_offset(blob, "/psci") < 0) { ++ print_string("/psci node not found\n\r"); ++ return; ++ } ++ ++ fw_node = dt_create_fw_node(); ++ ++ if(fw_node < 0) { ++ print_string(FW_NODE_NAME" node create err\n\r"); ++ } ++ ++ dt_set_prop(fw_node, "compatible", FW_COMPAT, sizeof(FW_COMPAT)); ++ dt_set_prop(fw_node, "version", FW_INFO_VER, sizeof(FW_INFO_VER)); ++ ++ dt_set_prop_u32(fw_node, "address-cells", CELL_NUM); ++ dt_set_prop_u32(fw_node, "size-cells", CELL_NUM); ++ dt_set_prop(fw_node, "regions-permission", regions_permission, ++ sizeof(regions_permission)); ++ dt_set_prop(fw_node, "regions-cache", regions_cache, ++ sizeof(regions_cache)); ++ ++#ifdef BOOTWRAPPER_32 ++ dt_set_prop_u32_array(fw_node, "regions", regions, regions_num); ++ dt_set_prop_u32(fw_node, "function_entry", (VAL_TYPE)smc_fn_entry); ++#else ++ dt_set_prop_u64_array(fw_node, "regions", regions, regions_num); ++ dt_set_prop_u64(fw_node, "function_entry", (VAL_TYPE)smc_fn_entry); ++#endif ++ ++ fdt_pack(blob); ++ ++ dt_dump_all(fw_node); ++} +-- +2.25.1 + diff --git a/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0021-boot-Enable-firmware-node-initialization.patch b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0021-boot-Enable-firmware-node-initialization.patch new file mode 100644 index 0000000..943afde --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0021-boot-Enable-firmware-node-initialization.patch @@ -0,0 +1,98 @@ +From 6dfc937d1ae54d2ae9f8c60ca29ba73ca14dc8c4 Mon Sep 17 00:00:00 2001 +From: Jaxson Han +Date: Wed, 29 Dec 2021 15:33:17 +0800 +Subject: [PATCH] boot: Enable firmware node initialization + +Enable the firmware node initialization, so that the next stage +(hypervisor) could share the EL2 with firmware (boot-wrapper). The next +stage (hypervisor) get the smccc entry point, code/data sections, the +sections attrs and firmware node version and so on. +It is worth noting that this EL2 sharing mechanism is only for Armv8R +AArch64, thus add flag_v8r to record if the arch is Armv8R AArch64. +Enable the firmware node initialization only if it is Armv8R AArch64. +Also, we increase the stack size to 1024 to fix the stack overflow issue +when using the libfdt. + +Add -fno-builtin options to CFLAGS to avoid the issue that the 'memset' +in common/lib.c conflicts with builtin 'memset' function. GCC version +>= 10 will have an incorrect compilation without -fno-builtin; + +Issue-Id: SCM-3816 +Upstream-Status: Inappropriate [other] + Implementation pending further discussion +Signed-off-by: Jaxson Han +Change-Id: Ib274485a34d26215595fd0cd737be86610289817 +--- + Makefile.am | 4 ++-- + arch/aarch64/boot.S | 6 ++++++ + common/boot.c | 4 ++++ + 3 files changed, 12 insertions(+), 2 deletions(-) + +diff --git a/Makefile.am b/Makefile.am +index 054becd..b01809c 100644 +--- a/Makefile.am ++++ b/Makefile.am +@@ -23,7 +23,7 @@ DEFINES += -DCPU_IDS=$(CPU_IDS) + DEFINES += -DNR_CPUS=$(NR_CPUS) + DEFINES += $(if $(SYSREGS_BASE), -DSYSREGS_BASE=$(SYSREGS_BASE), ) + DEFINES += -DUART_BASE=$(UART_BASE) +-DEFINES += -DSTACK_SIZE=256 ++DEFINES += -DSTACK_SIZE=1024 + + if KERNEL_32 + DEFINES += -DKERNEL_32 +@@ -132,7 +132,7 @@ CHOSEN_NODE := chosen { \ + CPPFLAGS += $(INITRD_FLAGS) + CFLAGS += -I$(top_srcdir)/include/ -I$(top_srcdir)/$(ARCH_SRC)/include/ + CFLAGS += -Wall -fomit-frame-pointer +-CFLAGS += -fno-stack-protector ++CFLAGS += -fno-stack-protector -fno-builtin + CFLAGS += -ffunction-sections -fdata-sections + CFLAGS += -fno-pic -fno-pie + LDFLAGS += --gc-sections +diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S +index 157c097..f310387 100644 +--- a/arch/aarch64/boot.S ++++ b/arch/aarch64/boot.S +@@ -240,6 +240,10 @@ el2_init: + #endif + ldr x1, =spsr_to_elx + str w0, [x1] ++ ++ mov w0, #1 ++ ldr x1, =flag_v8r ++ str w0, [x1] + // fall through + + el_max_init: +@@ -319,3 +323,5 @@ flag_keep_el: + .long 0 + ASM_DATA(spsr_to_elx) + .long 0 ++ASM_DATA(flag_v8r) ++ .long 0 +diff --git a/common/boot.c b/common/boot.c +index ee2bea0..38b2dca 100644 +--- a/common/boot.c ++++ b/common/boot.c +@@ -11,6 +11,9 @@ + + extern unsigned long entrypoint; + extern unsigned long dtb; ++extern unsigned int flag_v8r; ++ ++extern void dt_fw_node_init(int enable); + + void init_platform(void); + +@@ -64,6 +67,7 @@ void __noreturn first_spin(unsigned int cpu, unsigned long *mbox, + if (cpu == 0) { + init_platform(); + dt_add_memreserve(); ++ dt_fw_node_init(flag_v8r == 1); + + *mbox = (unsigned long)&entrypoint; + sevl(); +-- +2.25.1 + From patchwork Fri Apr 22 16:08:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Hoyes X-Patchwork-Id: 7043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90037C636C9 for ; Fri, 22 Apr 2022 16:52:02 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.10744.1650643784494331190 for ; Fri, 22 Apr 2022 09:09:44 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: peter.hoyes@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2A3101FB; Fri, 22 Apr 2022 09:09:44 -0700 (PDT) Received: from e125920.arm.com (unknown [10.57.95.219]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5300C3F5A1; Fri, 22 Apr 2022 09:09:43 -0700 (PDT) From: Peter Hoyes To: meta-arm@lists.yoctoproject.org Cc: diego.sueiro@arm.com, Peter Hoyes Subject: [PATCH 5/6] arm-bsp/u-boot: Fix fvp-baser-aemv8r64 fdt memory configuration issue Date: Fri, 22 Apr 2022 17:08:59 +0100 Message-Id: <20220422160900.1861031-5-peter.hoyes@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220422160900.1861031-1-peter.hoyes@arm.com> References: <20220422160900.1861031-1-peter.hoyes@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 22 Apr 2022 16:52:02 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/3290 From: Peter Hoyes Add additional fvp-baser-aemv8r64-specific patch for U-Boot, which fixes an issue where U-Boot was ignoring the `memory` node in the device tree. Issue-Id: SCM-4386 Signed-off-by: Peter Hoyes Change-Id: I1382992fffa159c4bd6325db4f1b26c6478cf391 --- .../documentation/fvp-baser-aemv8r64.md | 2 + ...4-Configure-memory-using-device-tree.patch | 88 +++++++++++++++++++ .../recipes-bsp/u-boot/u-boot_%.bbappend | 1 + 3 files changed, 91 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0012-vexpress64-Configure-memory-using-device-tree.patch diff --git a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md index 4cd18f0..2638502 100644 --- a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md +++ b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md @@ -234,6 +234,8 @@ Known Issues and Limitations Change Log ---------- +- Fixed bug in U-Boot that caused changes to the `memory` node in the device + tree to be ignored. - Added boot-wrapper-aarch64 support for booting SMP payloads at S-EL2. - Enabled testimage support by default. - Added virtio\_rng to improve random number generation. diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0012-vexpress64-Configure-memory-using-device-tree.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0012-vexpress64-Configure-memory-using-device-tree.patch new file mode 100644 index 0000000..f9b422a --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0012-vexpress64-Configure-memory-using-device-tree.patch @@ -0,0 +1,88 @@ +From 90db3d923adcade13d9a8aa50305e5c9c32737af Mon Sep 17 00:00:00 2001 +From: Peter Hoyes +Date: Thu, 17 Feb 2022 17:02:34 +0000 +Subject: [PATCH 1/2] vexpress64: Configure memory using device tree + +The memory size and memory banks were previously configured statically, +using #defines in the vexpress header file, which could conflict with +the information in the device tree. Instead, use +fdtdec_setup_mem_size_base() to configure the RAM size and +fdtdec_setup_memory_banksize() to set up the memory banks. + +Issue-Id: SCM-3874 +Upstream-Status: Inappropriate [other] + Implementation pending further discussion +Signed-off-by: Peter Hoyes +Change-Id: I4add8258cb99dac87f078435272410b562b6fdc7 +--- + board/armltd/vexpress64/vexpress64.c | 14 ++------------ + include/configs/vexpress_aemv8.h | 17 ----------------- + 2 files changed, 2 insertions(+), 29 deletions(-) + +diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c +index 270618a0ff..3f1ac04bac 100644 +--- a/board/armltd/vexpress64/vexpress64.c ++++ b/board/armltd/vexpress64/vexpress64.c +@@ -24,8 +24,6 @@ + #include + #endif + +-DECLARE_GLOBAL_DATA_PTR; +- + static const struct pl01x_serial_plat serial_plat = { + .base = V2M_UART0, + .type = TYPE_PL011, +@@ -128,20 +126,12 @@ int board_init(void) + + int dram_init(void) + { +- gd->ram_size = PHYS_SDRAM_1_SIZE; +- return 0; ++ return fdtdec_setup_mem_size_base(); + } + + int dram_init_banksize(void) + { +- gd->bd->bi_dram[0].start = PHYS_SDRAM_1; +- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +-#ifdef PHYS_SDRAM_2 +- gd->bd->bi_dram[1].start = PHYS_SDRAM_2; +- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +-#endif +- +- return 0; ++ return fdtdec_setup_memory_banksize(); + } + + /* Assigned in lowlevel_init.S +diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h +index a9086879c9..15a1ae60bf 100644 +--- a/include/configs/vexpress_aemv8.h ++++ b/include/configs/vexpress_aemv8.h +@@ -106,23 +106,6 @@ + /* BOOTP options */ + #define CONFIG_BOOTP_BOOTFILESIZE + +-/* Miscellaneous configurable options */ +- +-/* Physical Memory Map */ +-#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +-/* Top 16MB reserved for secure world use */ +-#define DRAM_SEC_SIZE 0x01000000 +-#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE +-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +- +-#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +-#define PHYS_SDRAM_2 (0x880000000) +-#define PHYS_SDRAM_2_SIZE 0x180000000 +-#elif CONFIG_NR_DRAM_BANKS == 2 +-#define PHYS_SDRAM_2 (0x880000000) +-#define PHYS_SDRAM_2_SIZE 0x80000000 +-#endif +- + /* Enable memtest */ + + /* Initial environment variables */ +-- +2.25.1 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend index 879b4a7..db395fe 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend @@ -71,6 +71,7 @@ SRC_URI:append:fvp-baser-aemv8r64 = " \ file://0009-armv8-Make-disabling-HVC-configurable-when-switching.patch \ file://0010-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch \ file://0011-vexpress64-Add-BASER_FVP-vexpress-board-variant.patch \ + file://0012-vexpress64-Configure-memory-using-device-tree.patch \ " # From patchwork Fri Apr 22 16:09:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Hoyes X-Patchwork-Id: 7045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9052DC636D5 for ; Fri, 22 Apr 2022 16:52:02 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.10723.1650643788278888037 for ; Fri, 22 Apr 2022 09:09:48 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: peter.hoyes@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EAA441FB; Fri, 22 Apr 2022 09:09:47 -0700 (PDT) Received: from e125920.arm.com (unknown [10.57.95.219]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1F7303F5A1; Fri, 22 Apr 2022 09:09:46 -0700 (PDT) From: Peter Hoyes To: meta-arm@lists.yoctoproject.org Cc: diego.sueiro@arm.com, Peter Hoyes Subject: [PATCH 6/6] arm-bsp/u-boot: Enable fdt overlays for fvp-baser-aemv8r64 Date: Fri, 22 Apr 2022 17:09:00 +0100 Message-Id: <20220422160900.1861031-6-peter.hoyes@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220422160900.1861031-1-peter.hoyes@arm.com> References: <20220422160900.1861031-1-peter.hoyes@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 22 Apr 2022 16:52:02 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/3291 From: Peter Hoyes Enable the OF_LIBFDT_OVERLAY configuration flag so that U-Boot can apply fdt overlays using the "fdt apply" command. This can be used to modify the device tree at runtime to boot a different payload without changing the firmware. Issue-Id: SCM-4386 Signed-off-by: Peter Hoyes Change-Id: I6e32c5ce833ca7c61f0f73fc256031564e55f1b8 --- .../documentation/fvp-baser-aemv8r64.md | 1 + ...e-LIBFDT_OVERLAY-in-the-vexpress_aem.patch | 27 +++++++++++++++++++ .../recipes-bsp/u-boot/u-boot_%.bbappend | 1 + 3 files changed, 29 insertions(+) create mode 100644 meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0013-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch diff --git a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md index 2638502..4e98e42 100644 --- a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md +++ b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md @@ -234,6 +234,7 @@ Known Issues and Limitations Change Log ---------- +- Enabled the ability for U-Boot to apply device tree overlays - Fixed bug in U-Boot that caused changes to the `memory` node in the device tree to be ignored. - Added boot-wrapper-aarch64 support for booting SMP payloads at S-EL2. diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0013-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0013-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch new file mode 100644 index 0000000..2824acc --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0013-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch @@ -0,0 +1,27 @@ +From 0ca75ef2a29f8b37f356af005dac3c83c9b50e2a Mon Sep 17 00:00:00 2001 +From: Peter Hoyes +Date: Tue, 22 Feb 2022 15:32:51 +0000 +Subject: [PATCH 2/2] vexpress64: Enable LIBFDT_OVERLAY in the vexpress_aemv8r + defconfig + +Issue-Id: SCM-3874 +Upstream-Status: Inappropriate [other] + Implementation pending further discussion +Signed-off-by: Peter Hoyes +Change-Id: Ide0532cf2de89f1bca9c8d4bd2ed0c1a1c57599f +--- + configs/vexpress_aemv8r_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig +index 37c393b66f..aff34e86b0 100644 +--- a/configs/vexpress_aemv8r_defconfig ++++ b/configs/vexpress_aemv8r_defconfig +@@ -25,3 +25,4 @@ CONFIG_ARMV8_SWITCH_TO_EL1=y + CONFIG_ARMV8_DISABLE_HVC=n + CONFIG_ARMV8_EXCEPTION_VECTORS=n + CONFIG_ARCH_FIXUP_FDT_MEMORY=n ++CONFIG_OF_LIBFDT_OVERLAY=y +-- +2.25.1 + diff --git a/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend index db395fe..f7336ad 100644 --- a/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend +++ b/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend @@ -72,6 +72,7 @@ SRC_URI:append:fvp-baser-aemv8r64 = " \ file://0010-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch \ file://0011-vexpress64-Add-BASER_FVP-vexpress-board-variant.patch \ file://0012-vexpress64-Configure-memory-using-device-tree.patch \ + file://0013-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch \ " #