From patchwork Mon Nov 27 21:58:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LCPD Automation Script X-Patchwork-Id: 35259 X-Patchwork-Delegate: reatmon@ti.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC1E9C10DAA for ; Mon, 27 Nov 2023 21:58:41 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by mx.groups.io with SMTP id smtpd.web11.113353.1701122318383467536 for ; Mon, 27 Nov 2023 13:58:38 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: list.ti.com, ip: 198.47.23.248, mailfrom: lcpdbld@list.ti.com) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3ARLwans067429; Mon, 27 Nov 2023 15:58:36 -0600 Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3ARLwauf022233 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Nov 2023 15:58:36 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 27 Nov 2023 15:58:36 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 27 Nov 2023 15:58:36 -0600 Received: from fllvdckhpci028.itg.ti.com (fllvdckhpci028.itg.ti.com [10.248.130.161]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3ARLwaGK060312; Mon, 27 Nov 2023 15:58:36 -0600 Received: by fllvdckhpci028.itg.ti.com (Postfix, from userid 60899) id 97D3410BB70B; Mon, 27 Nov 2023 15:58:36 -0600 (CST) From: LCPD Automation Script To: Ryan Eatmon , Praneeth Bajjuri , Denys Dmytriyenko , Subject: [meta-ti][kirkstone][PATCH 1/4] pru-icss_git.bb: update to PSSP v6.3.0 Date: Mon, 27 Nov 2023 15:58:33 -0600 Message-ID: <1701122316-142436-2-git-send-email-lcpdbld@list.ti.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1701122316-142436-1-git-send-email-lcpdbld@list.ti.com> References: <1701122316-142436-1-git-send-email-lcpdbld@list.ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 27 Nov 2023 21:58:41 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-ti/message/17332 From: Praneeth Bajjuri Upgrade to v6.3.0 version. This release adds resources for using AM243x & AM64x PRU cores with cores running FreeRTOS: * The RTOS Getting Started Labs * Examples for using PRU GPIO and the broadside interface * SORTE_G example (a custom networking interface) Bug fixes: * AM64x & AM65x header files, fix the names of extended sections to be in the format of ConstantsTableName_0x100 Signed-off-by: Praneeth Bajjuri Signed-off-by: Nick Saulnier Signed-off-by: Ryan Eatmon --- meta-ti-extras/recipes-bsp/pru/pru-icss_git.bb | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/meta-ti-extras/recipes-bsp/pru/pru-icss_git.bb b/meta-ti-extras/recipes-bsp/pru/pru-icss_git.bb index 6acce94..b01dd6a 100644 --- a/meta-ti-extras/recipes-bsp/pru/pru-icss_git.bb +++ b/meta-ti-extras/recipes-bsp/pru/pru-icss_git.bb @@ -8,10 +8,9 @@ inherit update-alternatives BRANCH = "master" SRC_URI = "git://git.ti.com/git/pru-software-support-package/pru-software-support-package.git;protocol=https;branch=${BRANCH}" -SRCREV = "3d0e311580d8967d0854ca789e9069e2810e9c1a" +SRCREV = "00a5efa5157feb84cb2e4bf50b481f7082acca82" -PV = "6.2.0" -PR = "r1" +PV = "6.3.0" require recipes-ti/includes/ti-paths.inc From patchwork Mon Nov 27 21:58:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LCPD Automation Script X-Patchwork-Id: 35257 X-Patchwork-Delegate: reatmon@ti.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89724C46CA0 for ; Mon, 27 Nov 2023 21:58:41 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by mx.groups.io with SMTP id smtpd.web10.113702.1701122318284083078 for ; Mon, 27 Nov 2023 13:58:38 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: list.ti.com, ip: 198.47.23.248, mailfrom: lcpdbld@list.ti.com) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3ARLwbLm067431; Mon, 27 Nov 2023 15:58:37 -0600 Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3ARLwaPK016807 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Nov 2023 15:58:36 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 27 Nov 2023 15:58:36 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 27 Nov 2023 15:58:36 -0600 Received: from fllvdckhpci028.itg.ti.com (fllvdckhpci028.itg.ti.com [10.248.130.161]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3ARLwa2W096883; Mon, 27 Nov 2023 15:58:36 -0600 Received: by fllvdckhpci028.itg.ti.com (Postfix, from userid 60899) id 9AF4810D08DD; Mon, 27 Nov 2023 15:58:36 -0600 (CST) From: LCPD Automation Script To: Ryan Eatmon , Praneeth Bajjuri , Denys Dmytriyenko , Subject: [meta-ti][kirkstone][PATCH 2/4] mesa-pvr: use different srcrev for Rogue and SGX GPU platforms Date: Mon, 27 Nov 2023 15:58:34 -0600 Message-ID: <1701122316-142436-3-git-send-email-lcpdbld@list.ti.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1701122316-142436-1-git-send-email-lcpdbld@list.ti.com> References: <1701122316-142436-1-git-send-email-lcpdbld@list.ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 27 Nov 2023 21:58:41 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-ti/message/17331 From: Darren Etheridge A bug was introduced while trying to unify the Mesa version that is used on SGX GPU's and Rogue GPU's. It manifests itself as an immediate segfault whenever you try and run something like glmark2-es2-wayland or weston-simple-egl on certain Rogue based platforms (specifically am62x). Use different srcrev for Rogue GPU and SGX GPU platforms. The SGX GPU platforms will use the latest commit. Rogue GPU platforms will use the last good working commit before SGX related changes were introduced. This change will be reverted once the issue is rootcaused and a common solution is found for both Rogue and SGX based GPU platforms. Signed-off-by: Darren Etheridge Signed-off-by: Anand Balagopalakrishnan Signed-off-by: Ryan Eatmon --- meta-ti-bsp/recipes-graphics/mesa/mesa-pvr_22.3.5.bb | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/meta-ti-bsp/recipes-graphics/mesa/mesa-pvr_22.3.5.bb b/meta-ti-bsp/recipes-graphics/mesa/mesa-pvr_22.3.5.bb index 98d30c5..55dad41 100644 --- a/meta-ti-bsp/recipes-graphics/mesa/mesa-pvr_22.3.5.bb +++ b/meta-ti-bsp/recipes-graphics/mesa/mesa-pvr_22.3.5.bb @@ -23,13 +23,17 @@ SRC_URI = " \ S = "${WORKDIR}/git" -SRCREV = "7c9522a4147836064f582278e4f7115735c16868" - PACKAGECONFIG:append = " \ ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/gpudriver', 'ti-img-rogue-driver', 'pvr', '', d)} \ ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/gpudriver', 'ti-sgx-ddk-km', 'sgx', '', d)} \ " +# Temporary work around to use a different SRCREV for SGX Mesa, vs Rogue Mesa +# Idea is these two should be the same, but currently a segfault is happening +# on certain platforms if the sgx commit is used. +SRCREV = "${@bb.utils.contains('PACKAGECONFIG', 'sgx', '7c9522a4147836064f582278e4f7115735c16868', '54fd9d7dea098b6f11c2a244b0c6763dc8c5690c', d)}" +PR = "sgxrgx-${SRCREV}" + PVR_DISPLAY_CONTROLLER_ALIAS ??= "tidss" PACKAGECONFIG[pvr] = "-Dgallium-pvr-alias=${PVR_DISPLAY_CONTROLLER_ALIAS}," PACKAGECONFIG[sgx] = "-Dgallium-sgx-alias=${PVR_DISPLAY_CONTROLLER_ALIAS}," From patchwork Mon Nov 27 21:58:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LCPD Automation Script X-Patchwork-Id: 35258 X-Patchwork-Delegate: reatmon@ti.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88199C4167B for ; Mon, 27 Nov 2023 21:58:41 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by mx.groups.io with SMTP id smtpd.web11.113354.1701122318449130626 for ; Mon, 27 Nov 2023 13:58:38 -0800 Authentication-Results: mx.groups.io; dkim=none (message not signed); spf=pass (domain: list.ti.com, ip: 198.47.23.249, mailfrom: lcpdbld@list.ti.com) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3ARLwaUk089302; Mon, 27 Nov 2023 15:58:36 -0600 Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3ARLwaS6016806 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Nov 2023 15:58:36 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 27 Nov 2023 15:58:36 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 27 Nov 2023 15:58:36 -0600 Received: from fllvdckhpci028.itg.ti.com (fllvdckhpci028.itg.ti.com [10.248.130.161]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3ARLwaS3060315; Mon, 27 Nov 2023 15:58:36 -0600 Received: by fllvdckhpci028.itg.ti.com (Postfix, from userid 60899) id 9E2EA10D08DE; Mon, 27 Nov 2023 15:58:36 -0600 (CST) From: LCPD Automation Script To: Ryan Eatmon , Praneeth Bajjuri , Denys Dmytriyenko , Subject: [meta-ti][kirkstone][PATCH 3/4] ti-extras: Add support for extra kernel/u-boot features for am62pxx Date: Mon, 27 Nov 2023 15:58:35 -0600 Message-ID: <1701122316-142436-4-git-send-email-lcpdbld@list.ti.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1701122316-142436-1-git-send-email-lcpdbld@list.ti.com> References: <1701122316-142436-1-git-send-email-lcpdbld@list.ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Mon, 27 Nov 2023 21:58:41 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-ti/message/17335 From: Paresh Bhagat Add support for ti-extras for am62pxx to control the kernel and u-boot repos, branches, and srcrevs via the TI_EXTRAS variable in the local.conf file. Also add am62pxx as compatble machine in jailhouse recipe. So the am62pxx jailhouse build can be done by adding TI_EXTRAS=tie-jailhouse in local.conf. Signed-off-by: Paresh Bhagat Signed-off-by: Ryan Eatmon --- meta-ti-bsp/conf/machine/am62pxx-evm-k3r5.conf | 1 + meta-ti-bsp/conf/machine/am62pxx-evm.conf | 1 + meta-ti-bsp/recipes-bsp/u-boot/ti-extras.inc | 2 +- meta-ti-bsp/recipes-kernel/linux/ti-extras-rt.inc | 2 +- meta-ti-bsp/recipes-kernel/linux/ti-extras.inc | 2 +- meta-ti-extras/recipes-ti/jailhouse/jailhouse_git.bb | 6 +++++- 6 files changed, 10 insertions(+), 4 deletions(-) diff --git a/meta-ti-bsp/conf/machine/am62pxx-evm-k3r5.conf b/meta-ti-bsp/conf/machine/am62pxx-evm-k3r5.conf index 33254bf..3691538 100644 --- a/meta-ti-bsp/conf/machine/am62pxx-evm-k3r5.conf +++ b/meta-ti-bsp/conf/machine/am62pxx-evm-k3r5.conf @@ -3,6 +3,7 @@ #@DESCRIPTION: Machine configuration for the TI AM62Px EVM (R5F core) require conf/machine/include/k3r5.inc +require conf/machine/include/ti-extras.inc SYSFW_SOC = "am62px" SYSFW_CONFIG = "evm" diff --git a/meta-ti-bsp/conf/machine/am62pxx-evm.conf b/meta-ti-bsp/conf/machine/am62pxx-evm.conf index 931de95..d7c9f58 100644 --- a/meta-ti-bsp/conf/machine/am62pxx-evm.conf +++ b/meta-ti-bsp/conf/machine/am62pxx-evm.conf @@ -3,6 +3,7 @@ #@DESCRIPTION: Machine configuration for the TI AM62PX EVM require conf/machine/include/am62pxx.inc +require conf/machine/include/ti-extras.inc KERNEL_DEVICETREE_PREFIX = " \ ti/k3-am62p5 \ diff --git a/meta-ti-bsp/recipes-bsp/u-boot/ti-extras.inc b/meta-ti-bsp/recipes-bsp/u-boot/ti-extras.inc index e0a94ea..d32c652 100644 --- a/meta-ti-bsp/recipes-bsp/u-boot/ti-extras.inc +++ b/meta-ti-bsp/recipes-bsp/u-boot/ti-extras.inc @@ -1,7 +1,7 @@ # This will have priority over generic uboot path -COMPATIBLE_MACHINE = "am62xx" +COMPATIBLE_MACHINE = "am62xx|am62pxx" BRANCH = "ti-u-boot-2023.04" BRANCH:tie-jailhouse = "ti-u-boot-2023.04-jailhouse" diff --git a/meta-ti-bsp/recipes-kernel/linux/ti-extras-rt.inc b/meta-ti-bsp/recipes-kernel/linux/ti-extras-rt.inc index 1fc4093..530a178 100644 --- a/meta-ti-bsp/recipes-kernel/linux/ti-extras-rt.inc +++ b/meta-ti-bsp/recipes-kernel/linux/ti-extras-rt.inc @@ -2,7 +2,7 @@ # Use different commit, repo and branch for TI extras build # This will have priority over generic rt path -COMPATIBLE_MACHINE = "am62xx" +COMPATIBLE_MACHINE = "am62xx|am62pxx" BRANCH = "ti-rt-linux-6.1.y" BRANCH:tie-jailhouse = "ti-rt-linux-6.1.y-jailhouse" diff --git a/meta-ti-bsp/recipes-kernel/linux/ti-extras.inc b/meta-ti-bsp/recipes-kernel/linux/ti-extras.inc index 076a67d..0b22aca 100644 --- a/meta-ti-bsp/recipes-kernel/linux/ti-extras.inc +++ b/meta-ti-bsp/recipes-kernel/linux/ti-extras.inc @@ -2,7 +2,7 @@ # Use different commit, repo and branch for TI extras build # This will have priority over generic rt path -COMPATIBLE_MACHINE = "am62xx" +COMPATIBLE_MACHINE = "am62xx|am62pxx" BRANCH = "ti-linux-6.1.y" BRANCH:tie-jailhouse = "ti-linux-6.1.y-jailhouse" diff --git a/meta-ti-extras/recipes-ti/jailhouse/jailhouse_git.bb b/meta-ti-extras/recipes-ti/jailhouse/jailhouse_git.bb index a96a783..ca82998 100644 --- a/meta-ti-extras/recipes-ti/jailhouse/jailhouse_git.bb +++ b/meta-ti-extras/recipes-ti/jailhouse/jailhouse_git.bb @@ -10,7 +10,7 @@ LIC_FILES_CHKSUM = " \ file://COPYING;md5=9fa7f895f96bde2d47fd5b7d95b6ba4d \ " -COMPATIBLE_MACHINE = "am62xx" +COMPATIBLE_MACHINE = "am62xx|am62pxx" TARGET_CC_ARCH += "${LDFLAGS}" @@ -55,18 +55,21 @@ JH_CELL_FILES:k3 ?= "k3-*.cell" JH_INMATE_DTB ?= "" JH_INMATE_DTB:am62xx ?= "inmate-k3-am625-sk.dtb" JH_INMATE_DTB:am65xx ?= "inmate-k3-am654-idk.dtb" +JH_INMATE_DTB:am62pxx ?= "inmate-k3-am62p5-sk.dtb" JH_INMATE_DTB:j7 ?= "inmate-k3-j721e-evm.dtb" JH_INMATE_DTB:j7200-evm ?= "inmate-k3-j7200-evm.dtb" JH_LINUX_DEMO_CELL ?= "" JH_LINUX_DEMO_CELL:am62xx ?= "k3-am625-sk-linux-demo.cell" JH_LINUX_DEMO_CELL:am65xx ?= "k3-am654-idk-linux-demo.cell" +JH_LINUX_DEMO_CELL:am62pxx ?= "k3-am62p5-sk-linux-demo.cell" JH_LINUX_DEMO_CELL:j7 ?= "k3-j721e-evm-linux-demo.cell" JH_LINUX_DEMO_CELL:j7200-evm ?= "k3-j7200-evm-linux-demo.cell" JH_SYSCONFIG_CELL ?= "" JH_SYSCONFIG_CELL:am62xx ?= "k3-am625-sk.cell" JH_SYSCONFIG_CELL:am65xx ?= "k3-am654-idk.cell" +JH_SYSCONFIG_CELL:am62pxx ?= "k3-am62p5-sk.cell" JH_SYSCONFIG_CELL:j7 ?= "k3-j721e-evm.cell" JH_SYSCONFIG_CELL:j7200-evm ?= "k3-j7200-evm.cell" @@ -75,6 +78,7 @@ JH_RAMFS_IMAGE ?= "${INITRAMFS_IMAGE}" JH_CMDLINE ?= "" JH_CMDLINE:am62xx ?= "console=ttyS3,115200n8 earlycon=ns16550a,mmio32,0x02810000" +JH_CMDLINE:am62pxx ?= "console=ttyS1,115200n8" JH_CMDLINE:am65xx ?= "console=ttyS1,115200n8" JH_CMDLINE:j7 ?= "console=ttyS3,115200n8" JH_CMDLINE:j7200-evm ?= "console=ttyS3,115200n8" From patchwork Mon Nov 27 21:58:36 2023 Content-Type: text/plain; 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Mon, 27 Nov 2023 21:58:41 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-ti/message/17333 Updated the value(s) for: ti-linux-fw: CNM_WAVE521_FW_VERSION,PRUETH_FW_AM65X_SR2_VERSION,TI_DM_FW_VERSION,TI_LINUX_FW_SRCREV,TI_SYSFW_VERSION u-boot-ti-staging_2023.04: SRCREV linux-ti-staging-rt_6.1: SRCREV linux-ti-staging_6.1: SRCREV Signed-off-by: LCPD Automation Script --- meta-ti-bsp/recipes-bsp/ti-linux-fw/ti-linux-fw.inc | 10 +++++----- meta-ti-bsp/recipes-bsp/u-boot/u-boot-ti-staging_2023.04.bb | 2 +- meta-ti-bsp/recipes-kernel/linux/linux-ti-staging-rt_6.1.bb | 2 +- meta-ti-bsp/recipes-kernel/linux/linux-ti-staging_6.1.bb | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/meta-ti-bsp/recipes-bsp/ti-linux-fw/ti-linux-fw.inc b/meta-ti-bsp/recipes-bsp/ti-linux-fw/ti-linux-fw.inc index 65edb73..cee23b1 100644 --- a/meta-ti-bsp/recipes-bsp/ti-linux-fw/ti-linux-fw.inc +++ b/meta-ti-bsp/recipes-bsp/ti-linux-fw/ti-linux-fw.inc @@ -9,15 +9,15 @@ INC_PR = "r4" # Firmware versions CORESDK_RTOS_VERSION = "08.02.00.04" PRUETH_FW_AM65X_VERSION = "08.00.00.20" -PRUETH_FW_AM65X_SR2_VERSION = "02.02.11.02" +PRUETH_FW_AM65X_SR2_VERSION = "02.02.12.08" GOODIX_FW_VERSION = "1.0.0.0" CADENCE_MHDP_FW_VERSION = "2.1.0" IMG_DEC_FW_VERSION = "1.0" -CNM_WAVE521_FW_VERSION = "1.0.00" -TI_DM_FW_VERSION = "08.06.04" -TI_SYSFW_VERSION = "08.06.04" +CNM_WAVE521_FW_VERSION = "1.0.3" +TI_DM_FW_VERSION = "09.01.02" +TI_SYSFW_VERSION = "09.01.07" -TI_LINUX_FW_SRCREV ?= "a2d8865df39e9021001fcf06e5daaeab81ba608c" +TI_LINUX_FW_SRCREV ?= "6dc47e330f11d01493d24e3ffb8ab369c15068eb" SRCREV = "${TI_LINUX_FW_SRCREV}" BRANCH ?= "ti-linux-firmware" diff --git a/meta-ti-bsp/recipes-bsp/u-boot/u-boot-ti-staging_2023.04.bb b/meta-ti-bsp/recipes-bsp/u-boot/u-boot-ti-staging_2023.04.bb index 4456a17..23dee3e 100644 --- a/meta-ti-bsp/recipes-bsp/u-boot/u-boot-ti-staging_2023.04.bb +++ b/meta-ti-bsp/recipes-bsp/u-boot/u-boot-ti-staging_2023.04.bb @@ -6,7 +6,7 @@ PR = "r0" BRANCH = "ti-u-boot-2023.04" -SRCREV = "8c121e6e3c7fd7be6e727ddd41880c202fb6e223" +SRCREV = "71b8c840ca61a4e11b2cdf63b0e6580ecb427912" do_install:append:am62xx() { install -d ${D}/boot diff --git a/meta-ti-bsp/recipes-kernel/linux/linux-ti-staging-rt_6.1.bb b/meta-ti-bsp/recipes-kernel/linux/linux-ti-staging-rt_6.1.bb index 3c82270..7f0df73 100644 --- a/meta-ti-bsp/recipes-kernel/linux/linux-ti-staging-rt_6.1.bb +++ b/meta-ti-bsp/recipes-kernel/linux/linux-ti-staging-rt_6.1.bb @@ -6,7 +6,7 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}-6.1:" BRANCH = "ti-rt-linux-6.1.y" -SRCREV = "2f5db0e70b5e1ea128754128ff87560ff0c7ffbb" +SRCREV = "a135c15322cfd7f341bde5de4df28208c1784d59" include ${@ 'recipes-kernel/linux/ti-extras-rt.inc' if d.getVar('TI_EXTRAS') else ''} diff --git a/meta-ti-bsp/recipes-kernel/linux/linux-ti-staging_6.1.bb b/meta-ti-bsp/recipes-kernel/linux/linux-ti-staging_6.1.bb index 45a43a9..e1ab980 100644 --- a/meta-ti-bsp/recipes-kernel/linux/linux-ti-staging_6.1.bb +++ b/meta-ti-bsp/recipes-kernel/linux/linux-ti-staging_6.1.bb @@ -23,7 +23,7 @@ S = "${WORKDIR}/git" BRANCH ?= "ti-linux-6.1.y" -SRCREV ?= "3db9a45004a01caba21d64b397814abadcc841b0" +SRCREV ?= "5892b80d6b7786cb1a78aba8147c3f844e063119" PV = "6.1.46+git${SRCPV}" # Append to the MACHINE_KERNEL_PR so that a new SRCREV will cause a rebuild