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[honister,1/3] arm-bsp/docs: Improve fvp-baser-aemv864 limitation

Message ID 20220304095611.217114-1-peter.hoyes@arm.com
State New
Headers show
Series [honister,1/3] arm-bsp/docs: Improve fvp-baser-aemv864 limitation | expand

Commit Message

Peter Hoyes March 4, 2022, 9:56 a.m. UTC 
From: Peter Hoyes <Peter.Hoyes@arm.com>

Add more details about the cache_state_modelled limitation, which can
worked around by setting cci400.force_on_from_start=1

Issue-Id: SCM-3871
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Change-Id: Idde23278a87316dae842c6c3793b9836482e8c3a
---
 meta-arm-bsp/documentation/fvp-baser-aemv8r64.md | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
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Patch

diff --git a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md
index 98ede27..4f207ba 100644
--- a/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md
+++ b/meta-arm-bsp/documentation/fvp-baser-aemv8r64.md
@@ -217,8 +217,11 @@  Known Issues and Limitations
 - Only PSCI CPU\_ON and CPU\_OFF functions are supported
 - Linux kernel does not support booting from secure EL2 on Armv8-R AArch64
 - Linux KVM does not support Armv8-R AArch64
-- Enabling the FVP parameter `cache_state_modelled` is incompatible with virtio
-  devices
+- Device DMA memory cache-coherence issue: the FVP cache_state_modelled
+  parameter will affect the cache coherence behavior of peripherals’ DMA. When
+  users set cache_state_modelled=1, they also have to set
+  cci400.force_on_from_start=1 to force the FVP to enable snooping on upstream
+  ports.
 
 Change Log
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