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[honister,1/8] arm-bsp/fvp-baser-aemv8r64: Fix PL011 and SP805 register sizes

Message ID 20220224112244.1521611-2-peter.hoyes@arm.com
State New
Headers show
Series Add UEFI to fvp-baser-aemv8r64 using U-Boot | expand

Commit Message

Peter Hoyes Feb. 24, 2022, 11:22 a.m. UTC 
From: Peter Hoyes <Peter.Hoyes@arm.com>

The Linux kernel expects the peripheral ID register to be just below the
end of the address range, which for the PL011 and SP805 is at 0xFE0 not
0xFFE0, so set the size to 0x1000.

Issue-Id: SCM-3881
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Change-Id: Iada28e8192d72b1647822c33d13deffe507043b5
---
 .../files/fvp-baser-aemv8r64/fvp-baser-aemv8r64.dts    | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
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Patch

diff --git a/meta-arm-bsp/recipes-kernel/linux/files/fvp-baser-aemv8r64/fvp-baser-aemv8r64.dts b/meta-arm-bsp/recipes-kernel/linux/files/fvp-baser-aemv8r64/fvp-baser-aemv8r64.dts
index dfc6f7e..4d6640a 100644
--- a/meta-arm-bsp/recipes-kernel/linux/files/fvp-baser-aemv8r64/fvp-baser-aemv8r64.dts
+++ b/meta-arm-bsp/recipes-kernel/linux/files/fvp-baser-aemv8r64/fvp-baser-aemv8r64.dts
@@ -111,7 +111,7 @@ 
 
         uart@9c090000 {
                 compatible = "arm,pl011", "arm,primecell";
-                reg = <0x0 0x9c090000 0x0 0x10000>;
+                reg = <0x0 0x9c090000 0x0 0x1000>;
                 interrupts = <0x0 5 0x4>;
                 clocks = <&refclk24mhz>, <&refclk100mhz>;
                 clock-names = "uartclk", "apb_pclk";
@@ -119,7 +119,7 @@ 
 
         uart@9c0a0000 {
                 compatible = "arm,pl011", "arm,primecell";
-                reg = <0x0 0x9c0a0000 0x0 0x10000>;
+                reg = <0x0 0x9c0a0000 0x0 0x1000>;
                 interrupts = <0x0 6 0x4>;
                 clocks = <&refclk24mhz>, <&refclk100mhz>;
                 clock-names = "uartclk", "apb_pclk";
@@ -127,7 +127,7 @@ 
 
         uart@9c0b0000 {
                 compatible = "arm,pl011", "arm,primecell";
-                reg = <0x0 0x9c0b0000 0x0 0x10000>;
+                reg = <0x0 0x9c0b0000 0x0 0x1000>;
                 interrupts = <0x0 7 0x4>;
                 clocks = <&refclk24mhz>, <&refclk100mhz>;
                 clock-names = "uartclk", "apb_pclk";
@@ -135,7 +135,7 @@ 
 
         uart@9c0c0000 {
                 compatible = "arm,pl011", "arm,primecell";
-                reg = <0x0 0x9c0c0000 0x0 0x10000>;
+                reg = <0x0 0x9c0c0000 0x0 0x1000>;
                 interrupts = <0x0 8 0x4>;
                 clocks = <&refclk24mhz>, <&refclk100mhz>;
                 clock-names = "uartclk", "apb_pclk";
@@ -143,7 +143,7 @@ 
 
         wdt@9c0f0000 {
                 compatible = "arm,sp805", "arm,primecell";
-                reg = <0x0 0x9c0f0000 0x0 0x10000>;
+                reg = <0x0 0x9c0f0000 0x0 0x1000>;
                 interrupts = <0x0 0 0x4>;
                 clocks = <&refclk24mhz>, <&refclk100mhz>;
                 clock-names = "wdog_clk", "apb_pclk";