diff mbox series

[nanbield,1/1] corstone1000:arm-bsp/tftf: Fix tftf tests on mps3

Message ID 20240118102437.106769-1-emekcan.aras@arm.com
State New
Headers show
Series [nanbield,1/1] corstone1000:arm-bsp/tftf: Fix tftf tests on mps3 | expand

Commit Message

Emekcan Aras Jan. 18, 2024, 10:24 a.m. UTC 
From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

The tftf tests were getting crashed on the MPS3 and two issues were found
during investigation. This change set provide fix for those issues:
1. The tftf tests were getting crashed on the MPS3 when compiled with
LOG_LEVEL=50. So, reducing the log level and aligning it with the TF-A
allows us to get rid of the crash.

2. Once the above crash got resolved, it has been found that tftf tests
were getting asserted while reading the value of the register
GICD_ITARGETSR. The reason for the crash is that the value of this register
is zero. As per the GIC documentation, this register is RAZ/WI for uniprocessor
implementation and corstone1000 is uniprocessor implementation for FPGA.
So, this change compiles the tftf tests in release mode which allows us
to compile out the assert definitions.

Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>
---
 .../recipes-bsp/trusted-firmware-a/tf-a-tests_%.bbappend     | 3 +++
 .../recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bb       | 5 ++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

Comments

Jon Mason Jan. 19, 2024, 1:53 p.m. UTC | #1 
On Thu, 18 Jan 2024 10:24:37 +0000, emekcan.aras@arm.com wrote:
> The tftf tests were getting crashed on the MPS3 and two issues were found
> during investigation. This change set provide fix for those issues:
> 1. The tftf tests were getting crashed on the MPS3 when compiled with
> LOG_LEVEL=50. So, reducing the log level and aligning it with the TF-A
> allows us to get rid of the crash.
> 
> 2. Once the above crash got resolved, it has been found that tftf tests
> were getting asserted while reading the value of the register
> GICD_ITARGETSR. The reason for the crash is that the value of this register
> is zero. As per the GIC documentation, this register is RAZ/WI for uniprocessor
> implementation and corstone1000 is uniprocessor implementation for FPGA.
> So, this change compiles the tftf tests in release mode which allows us
> to compile out the assert definitions.
> 
> [...]

Applied, thanks!

[1/1] corstone1000:arm-bsp/tftf: Fix tftf tests on mps3
      commit: 987d685ed0689808f11a0fd855d47921cddb926d

Best regards,
diff mbox series

Patch

diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_%.bbappend b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_%.bbappend
index 074bc683..eef21b93 100644
--- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_%.bbappend
+++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_%.bbappend
@@ -2,5 +2,8 @@ 
 
 COMPATIBLE_MACHINE:corstone1000 = "corstone1000"
 SRCREV:corstone1000 = "5f591f67738a1bbe6b262c53d9dad46ed8bbcd67"
+EXTRA_OEMAKE:append:corstone1000 = " DEBUG=0"
+EXTRA_OEMAKE:append:corstone1000 = " LOG_LEVEL=30"
+TFTF_MODE:corstone1000 = "release"
 
 COMPATIBLE_MACHINE:n1sdp = "n1sdp"
diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bb b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bb
index ed3b3499..160ada67 100644
--- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bb
+++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bb
@@ -19,6 +19,9 @@  EXTRA_OEMAKE += "USE_NVM=0"
 EXTRA_OEMAKE += "SHELL_COLOR=1"
 EXTRA_OEMAKE += "DEBUG=1"
 
+# Modify mode based on debug or release mode
+TFTF_MODE ?= "debug"
+
 # Platform must be set for each machine
 TFA_PLATFORM ?= "invalid"
 
@@ -45,7 +48,7 @@  SYSROOT_DIRS += "/firmware"
 
 do_install() {
     install -d -m 755 ${D}/firmware
-    install -m 0644 ${B}/${TFA_PLATFORM}/debug/tftf.bin ${D}/firmware/tftf.bin
+    install -m 0644 ${B}/${TFA_PLATFORM}/${TFTF_MODE}/tftf.bin ${D}/firmware/tftf.bin
 }
 
 do_deploy() {