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Tue, 11 Jul 2023 09:22:19 -0700 (PDT) Received: from megalith.cgocable.net ([2001:1970:5b1f:ab00:fc4e:ec42:7e5d:48dd]) by smtp.gmail.com with ESMTPSA id q11-20020ac8450b000000b003f7fd3ce69fsm1238605qtn.59.2023.07.11.09.22.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 09:22:18 -0700 (PDT) From: Trevor Gamblin To: openembedded-core@lists.openembedded.org Subject: [OE-core][PATCH] qemu: upgrade 8.0.0 -> 8.0.3 Date: Tue, 11 Jul 2023 12:22:15 -0400 Message-ID: <20230711162217.4110128-1-tgamblin@baylibre.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 11 Jul 2023 16:22:27 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/184146 ppc.patch is removed because it is included in 8.0.3: https://github.com/qemu/qemu/commit/864ce70c1c747898063cc2df854920d354b1b78f General changelog for 8.x: https://wiki.qemu.org/ChangeLog/8.0 Signed-off-by: Trevor Gamblin --- ...u-native_8.0.0.bb => qemu-native_8.0.3.bb} | 0 ...e_8.0.0.bb => qemu-system-native_8.0.3.bb} | 0 meta/recipes-devtools/qemu/qemu.inc | 3 +- meta/recipes-devtools/qemu/qemu/ppc.patch | 148 ------------------ .../qemu/{qemu_8.0.0.bb => qemu_8.0.3.bb} | 0 5 files changed, 1 insertion(+), 150 deletions(-) rename meta/recipes-devtools/qemu/{qemu-native_8.0.0.bb => qemu-native_8.0.3.bb} (100%) rename meta/recipes-devtools/qemu/{qemu-system-native_8.0.0.bb => qemu-system-native_8.0.3.bb} (100%) delete mode 100644 meta/recipes-devtools/qemu/qemu/ppc.patch rename meta/recipes-devtools/qemu/{qemu_8.0.0.bb => qemu_8.0.3.bb} (100%) diff --git a/meta/recipes-devtools/qemu/qemu-native_8.0.0.bb b/meta/recipes-devtools/qemu/qemu-native_8.0.3.bb similarity index 100% rename from meta/recipes-devtools/qemu/qemu-native_8.0.0.bb rename to meta/recipes-devtools/qemu/qemu-native_8.0.3.bb diff --git a/meta/recipes-devtools/qemu/qemu-system-native_8.0.0.bb b/meta/recipes-devtools/qemu/qemu-system-native_8.0.3.bb similarity index 100% rename from meta/recipes-devtools/qemu/qemu-system-native_8.0.0.bb rename to meta/recipes-devtools/qemu/qemu-system-native_8.0.3.bb diff --git a/meta/recipes-devtools/qemu/qemu.inc b/meta/recipes-devtools/qemu/qemu.inc index a5bdeef66d..f343dba75d 100644 --- a/meta/recipes-devtools/qemu/qemu.inc +++ b/meta/recipes-devtools/qemu/qemu.inc @@ -30,11 +30,10 @@ SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \ file://0001-tracetool-use-relative-paths-for-line-preprocessor-d.patch \ file://qemu-guest-agent.init \ file://qemu-guest-agent.udev \ - file://ppc.patch \ " UPSTREAM_CHECK_REGEX = "qemu-(?P\d+(\.\d+)+)\.tar" -SRC_URI[sha256sum] = "bb60f0341531181d6cc3969dd19a013d0427a87f918193970d9adb91131e56d0" +SRC_URI[sha256sum] = "ecf4d32cbef9d397bfc8cc50e4d1e92a1b30253bf32e8ee73c7a8dcf9a232b09" SRC_URI:append:class-target = " file://cross.patch" SRC_URI:append:class-nativesdk = " file://cross.patch" diff --git a/meta/recipes-devtools/qemu/qemu/ppc.patch b/meta/recipes-devtools/qemu/qemu/ppc.patch deleted file mode 100644 index e14c48cf85..0000000000 --- a/meta/recipes-devtools/qemu/qemu/ppc.patch +++ /dev/null @@ -1,148 +0,0 @@ -From 31f02021ac17442c514593f7b9ed750ea87c21b1 Mon Sep 17 00:00:00 2001 -From: Richard Purdie -Date: Sat, 6 May 2023 07:42:35 +0100 -Cc: Víctor Colombo -Cc: Matheus Ferst -Cc: Daniel Henrique Barboza -Cc: Richard Henderson -Cc: Philippe Mathieu-Daudé -Subject: [PATCH v3] target/ppc: Fix fallback to MFSS for MFFS* instructions on - pre 3.0 ISAs - -The following commits changed the code such that the fallback to MFSS for MFFSCRN, -MFFSCRNI, MFFSCE and MFFSL on pre 3.0 ISAs was removed and became an illegal instruction: - - bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to decodetree - 394c2e2fda70da722f20fb60412d6c0ca4bfaa03 - target/ppc: Move mffsce to decodetree - 3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to decodetree - -The hardware will handle them as a MFFS instruction as the code did previously. -This means applications that were segfaulting under qemu when encountering these -instructions which is used in glibc libm functions for example. - -The fallback for MFFSCDRN and MFFSCDRNI added in a later patch was also missing. - -This patch restores the fallback to MFSS for these instructions on pre 3.0s ISAs -as the hardware decoder would, fixing the segfaulting libm code. It doesn't have -the fallback for 3.0 onwards to match hardware behaviour. - -Signed-off-by: Richard Purdie ---- - target/ppc/insn32.decode | 20 +++++++++++++------- - target/ppc/translate/fp-impl.c.inc | 22 ++++++++++++++++------ - 2 files changed, 29 insertions(+), 13 deletions(-) - -v3 - drop fallback to MFFS for 3.0 ISA to match hardware -v2 - switch to use decodetree pattern groups per feedback - -Upstream-Status: Submitted [https://lore.kernel.org/qemu-devel/20230506065240.3177798-1-richard.purdie@linuxfoundation.org/] - -diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode -index f8f589e9fd..4fcf3af8d0 100644 ---- a/target/ppc/insn32.decode -+++ b/target/ppc/insn32.decode -@@ -390,13 +390,19 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi - - ### Move To/From FPSCR - --MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc --MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t --MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb --MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb --MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2 --MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3 --MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t -+{ -+ # Before Power ISA v3.0, MFFS bits 11~15 were reserved and should be ignored -+ MFFS_ISA207 111111 ..... ----- ----- 1001000111 . @X_t_rc -+ [ -+ MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc -+ MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t -+ MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb -+ MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb -+ MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2 -+ MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3 -+ MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t -+ ] -+} - - ### Decimal Floating-Point Arithmetic Instructions - -diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc -index 57d8437851..874774eade 100644 ---- a/target/ppc/translate/fp-impl.c.inc -+++ b/target/ppc/translate/fp-impl.c.inc -@@ -568,6 +568,22 @@ static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t clear_mask, - gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask); - } - -+static bool trans_MFFS_ISA207(DisasContext *ctx, arg_X_t_rc *a) -+{ -+ if (!(ctx->insns_flags2 & PPC2_ISA300)) { -+ /* -+ * Before Power ISA v3.0, MFFS bits 11~15 were reserved, any instruction -+ * with OPCD=63 and XO=583 should be decoded as MFFS. -+ */ -+ return trans_MFFS(ctx, a); -+ } -+ /* -+ * For Power ISA v3.0+, return false and let the pattern group -+ * select the correct instruction. -+ */ -+ return false; -+} -+ - static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a) - { - REQUIRE_FPU(ctx); -@@ -584,7 +600,6 @@ static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a) - { - TCGv_i64 fpscr; - -- REQUIRE_INSNS_FLAGS2(ctx, ISA300); - REQUIRE_FPU(ctx); - - gen_reset_fpstatus(); -@@ -597,7 +612,6 @@ static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a) - { - TCGv_i64 t1, fpscr; - -- REQUIRE_INSNS_FLAGS2(ctx, ISA300); - REQUIRE_FPU(ctx); - - t1 = tcg_temp_new_i64(); -@@ -614,7 +628,6 @@ static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb *a) - { - TCGv_i64 t1, fpscr; - -- REQUIRE_INSNS_FLAGS2(ctx, ISA300); - REQUIRE_FPU(ctx); - - t1 = tcg_temp_new_i64(); -@@ -631,7 +644,6 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a) - { - TCGv_i64 t1, fpscr; - -- REQUIRE_INSNS_FLAGS2(ctx, ISA300); - REQUIRE_FPU(ctx); - - t1 = tcg_temp_new_i64(); -@@ -647,7 +659,6 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a) - { - TCGv_i64 t1, fpscr; - -- REQUIRE_INSNS_FLAGS2(ctx, ISA300); - REQUIRE_FPU(ctx); - - t1 = tcg_temp_new_i64(); -@@ -661,7 +672,6 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a) - - static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a) - { -- REQUIRE_INSNS_FLAGS2(ctx, ISA300); - REQUIRE_FPU(ctx); - - gen_reset_fpstatus(); --- -2.39.2 - diff --git a/meta/recipes-devtools/qemu/qemu_8.0.0.bb b/meta/recipes-devtools/qemu/qemu_8.0.3.bb similarity index 100% rename from meta/recipes-devtools/qemu/qemu_8.0.0.bb rename to meta/recipes-devtools/qemu/qemu_8.0.3.bb