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[72.234.106.30]) by smtp.gmail.com with ESMTPSA id x14-20020aa784ce000000b006475f831838sm981877pfn.30.2023.05.14.09.31.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 May 2023 09:31:51 -0700 (PDT) From: Steve Sakoman To: openembedded-core@lists.openembedded.org Subject: [OE-core][mickledore 03/15] qemu: Update ppc instruction fix to match revised upstream version Date: Sun, 14 May 2023 06:31:28 -1000 Message-Id: <411e3f76840c06580fa8d2e764ae504b8f0ad46b.1684081748.git.steve@sakoman.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Sun, 14 May 2023 16:31:57 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/181204 From: Richard Purdie Upstream asked for some changes, this updates our patch to match. The differences likely don't change our real world use. Signed-off-by: Richard Purdie (cherry picked from commit 42591e07a469cff881fa087d5251a8c783897634) Signed-off-by: Steve Sakoman --- meta/recipes-devtools/qemu/qemu/ppc.patch | 127 +++++++++++++++++----- 1 file changed, 102 insertions(+), 25 deletions(-) diff --git a/meta/recipes-devtools/qemu/qemu/ppc.patch b/meta/recipes-devtools/qemu/qemu/ppc.patch index 395cdb814f..4fce3c81ac 100644 --- a/meta/recipes-devtools/qemu/qemu/ppc.patch +++ b/meta/recipes-devtools/qemu/qemu/ppc.patch @@ -1,70 +1,147 @@ -target/ppc: Fix fallback to MFSS for MFFSCRN, MFFSCRNI, MFFSCE and MFFSL +From d92b63b7d15d4fd202c5802dfe444a96f5d8109c Mon Sep 17 00:00:00 2001 +From: Richard Purdie +Date: Sat, 6 May 2023 07:42:35 +0100 +Cc: Víctor Colombo +Cc: Matheus Ferst +Cc: Daniel Henrique Barboza +Cc: Richard Henderson +Subject: [PATCH v2] target/ppc: Fix fallback to MFSS for MFFS* instructions on + pre 3.0 ISAs -The following commits changed the code such that these instructions became invalid -on pre 3.0 ISAs: +The following commits changed the code such that the fallback to MFSS for MFFSCRN, +MFFSCRNI, MFFSCE and MFFSL on pre 3.0 ISAs was removed and became an illegal instruction: - bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to decodetree + bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to decodetree 394c2e2fda70da722f20fb60412d6c0ca4bfaa03 - target/ppc: Move mffsce to decodetree - 3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to decodetree + 3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to decodetree The hardware will handle them as a MFFS instruction as the code did previously. -Restore that behaviour. This means applications that were segfaulting under qemu -when encountering these instructions now operate correctly. The instruction -is used in glibc libm functions for example. +This means applications that were segfaulting under qemu when encountering these +instructions which is used in glibc libm functions for example. -Upstream-Status: Submitted [https://lore.kernel.org/qemu-devel/20230504110150.3044402-1-richard.purdie@linuxfoundation.org/] +The fallback for MFFSCDRN and MFFSCDRNI added in a later patch was also missing. + +This patch restores the fallback to MFSS for these instructions on pre 3.0s ISAs +as the hardware decoder would, fixing the segfaulting libm code. It and also ensures +the MFSS instruction is used for currently reserved bits to handle other potential +ISA additions more correctly. + +Upstream-Status: Submitted [https://lore.kernel.org/qemu-devel/20230506065240.3177798-1-richard.purdie@linuxfoundation.org/] Signed-off-by: Richard Purdie +--- + target/ppc/insn32.decode | 19 ++++++++++++------- + target/ppc/translate/fp-impl.c.inc | 30 ++++++++++++++++++++++++------ + 2 files changed, 36 insertions(+), 13 deletions(-) -Index: qemu-8.0.0/target/ppc/translate/fp-impl.c.inc -=================================================================== ---- qemu-8.0.0.orig/target/ppc/translate/fp-impl.c.inc -+++ qemu-8.0.0/target/ppc/translate/fp-impl.c.inc -@@ -584,7 +584,10 @@ static bool trans_MFFSCE(DisasContext *c +v2 - switch to use decodetree pattern groups per feedback + +diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode +index f8f589e9fd..3c4e2c2fc2 100644 +--- a/target/ppc/insn32.decode ++++ b/target/ppc/insn32.decode +@@ -390,13 +390,18 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi + + ### Move To/From FPSCR + +-MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc +-MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t +-MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb +-MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb +-MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2 +-MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3 +-MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t ++{ ++ # Before Power ISA v3.0, MFFS bits 11~15 were reserved and should be ignored ++ [ ++ MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t ++ MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb ++ MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb ++ MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2 ++ MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3 ++ MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t ++ ] ++ MFFS 111111 ..... ----- ----- 1001000111 . @X_t_rc ++} + + ### Decimal Floating-Point Arithmetic Instructions + +diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc +index 57d8437851..10dfd91aa4 100644 +--- a/target/ppc/translate/fp-impl.c.inc ++++ b/target/ppc/translate/fp-impl.c.inc +@@ -584,7 +584,10 @@ static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a) { TCGv_i64 fpscr; - REQUIRE_INSNS_FLAGS2(ctx, ISA300); -+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { -+ return trans_MFFS(ctx, a); ++ if (!(ctx->insns_flags2 & PPC2_ISA300)) { ++ return false; + } + REQUIRE_FPU(ctx); gen_reset_fpstatus(); -@@ -597,7 +600,10 @@ static bool trans_MFFSCRN(DisasContext * +@@ -597,7 +600,10 @@ static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a) + { + TCGv_i64 t1, fpscr; + +- REQUIRE_INSNS_FLAGS2(ctx, ISA300); ++ if (!(ctx->insns_flags2 & PPC2_ISA300)) { ++ return false; ++ } ++ + REQUIRE_FPU(ctx); + + t1 = tcg_temp_new_i64(); +@@ -614,7 +620,10 @@ static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb *a) { TCGv_i64 t1, fpscr; - REQUIRE_INSNS_FLAGS2(ctx, ISA300); -+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { -+ return trans_MFFS(ctx, a); ++ if (!(ctx->insns_flags2 & PPC2_ISA300)) { ++ return false; + } + REQUIRE_FPU(ctx); t1 = tcg_temp_new_i64(); -@@ -631,7 +637,10 @@ static bool trans_MFFSCRNI(DisasContext +@@ -631,7 +640,10 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a) { TCGv_i64 t1, fpscr; - REQUIRE_INSNS_FLAGS2(ctx, ISA300); -+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { -+ return trans_MFFS(ctx, a); ++ if (!(ctx->insns_flags2 & PPC2_ISA300)) { ++ return false; + } + REQUIRE_FPU(ctx); t1 = tcg_temp_new_i64(); -@@ -661,7 +670,10 @@ static bool trans_MFFSCDRNI(DisasContext +@@ -647,7 +659,10 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a) + { + TCGv_i64 t1, fpscr; + +- REQUIRE_INSNS_FLAGS2(ctx, ISA300); ++ if (!(ctx->insns_flags2 & PPC2_ISA300)) { ++ return false; ++ } ++ + REQUIRE_FPU(ctx); + + t1 = tcg_temp_new_i64(); +@@ -661,7 +676,10 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a) { TCGv_i64 fpscr; - REQUIRE_INSNS_FLAGS2(ctx, ISA300); -+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { -+ return trans_MFFS(ctx, a); ++ if (!(ctx->insns_flags2 & PPC2_ISA300)) { ++ return false; + } + REQUIRE_FPU(ctx); gen_reset_fpstatus(); +-- +2.39.2 +