drivers: dspi: fsl: fix dspi transfer hang issue

Submitted by Zhantao Tang on June 4, 2021, 5:41 a.m. | Patch ID: 179828

Details

Message ID 20210604054122.2732003-2-zhantao.tang@windriver.com
State New
Headers show

Commit Message

Zhantao Tang June 4, 2021, 5:41 a.m.
On NXP S32G RDB2, there is an sja1110 switch, which can be accessed
using dspi interface, but if users use the following commands to test
the switch, the board will hang there.

	$ echo 30 > /sys/class/gpio/export
	$ echo out > /sys/class/gpio/gpio30/direction
	$ echo 0 > /sys/class/gpio/gpio30/value
	$ echo -n -e '\x02\x00\x00\x00\x00\x00\x00\x00' | spi-pipe -d /dev/spidev5.1 -b 4 | hexdump -C

The reason is that, the dspi driver wrongly sets the HALT flag in
the register, and the while loop will run forever, so the board hang
there. This patch is to fix this issue.

Signed-off-by: Zhantao Tang <zhantao.tang@windriver.com>
---
 drivers/spi/spi-fsl-dspi.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

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diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 063cf4a60ed3..c20cce466bf7 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -965,10 +965,8 @@  static int dspi_transfer_one_message(struct spi_controller *ctlr,
 		dspi->progress = 0;
 
 		regmap_update_bits(dspi->regmap, SPI_MCR,
-				SPI_MCR_HALT, SPI_MCR_HALT);
-		while (regmap_read(dspi->regmap, SPI_SR, &val) >= 0 &&
-				val & SPI_SR_TXRXS)
-			;
+				   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
+				   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
 
 		spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
 				       dspi->progress, !dspi->irq);
@@ -987,10 +985,6 @@  static int dspi_transfer_one_message(struct spi_controller *ctlr,
 				} while (status == -EINPROGRESS);
 			}
 		}
-		regmap_update_bits(dspi->regmap, SPI_MCR,
-				SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF |
-				SPI_MCR_HALT,
-				SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
 		if (status)
 			break;