[3rdparty,v2,master,3/4] linux-fslc: Add support for the ConnectCore 6UL SoM and SBC Express

Submitted by Gonzalez, Alex on Nov. 23, 2018, 4:54 p.m. | Patch ID: 156593

Details

Message ID 1542992056-16014-4-git-send-email-alex.gonzalez@digi.com
State New
Headers show

Commit Message

Gonzalez, Alex Nov. 23, 2018, 4:54 p.m.
The support for the ConnectCore 6UL SOM and SBC Express is available in
v4.19 so it is added as patches here.

The GPMI BCH layout change is needed to match the kernel with the
NXP IMX vendor based U-Boot used in the ConnectCore 6UL SOM.

Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
---
 ...-mtd-gpmi-change-the-BCH-layout-setting-f.patch | 553 +++++++++++++++++++++
 ...6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch | 115 +++++
 ...6ul-use-nvmem-cells-for-cpu-speed-grading.patch |  39 ++
 ...6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch | 236 +++++++++
 ...6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch | 244 +++++++++
 recipes-kernel/linux/linux-fslc_%.bbappend         |   8 +
 6 files changed, 1195 insertions(+)
 create mode 100644 recipes-kernel/linux/linux-fslc/ccimx6ul/0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch
 create mode 100644 recipes-kernel/linux/linux-fslc/ccimx6ul/0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch
 create mode 100644 recipes-kernel/linux/linux-fslc/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch
 create mode 100644 recipes-kernel/linux/linux-fslc/ccimx6ul/0004-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch
 create mode 100644 recipes-kernel/linux/linux-fslc/ccimx6ul/0005-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch

Patch hide | download patch | download mbox

diff --git a/recipes-kernel/linux/linux-fslc/ccimx6ul/0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch b/recipes-kernel/linux/linux-fslc/ccimx6ul/0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch
new file mode 100644
index 000000000000..82d15a2538d2
--- /dev/null
+++ b/recipes-kernel/linux/linux-fslc/ccimx6ul/0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch
@@ -0,0 +1,553 @@ 
+From a736d243e0b552e2b1ae80fe6d9026a2754752e3 Mon Sep 17 00:00:00 2001
+From: Alex Gonzalez <alex.gonzalez@digi.com>
+Date: Fri, 24 Aug 2018 18:53:40 +0200
+Subject: [PATCH 1/5] MLK-11719-4: mtd: gpmi: change the BCH layout setting for
+ large oob NAND
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The cod change updated the NAND driver BCH ECC layout algorithm to
+support large oob size NAND chips(oob > 1024 bytes) and proposed a new
+way to set ECC layout.
+
+Current implementation requires each chunk size larger than oob size so
+the bad block marker (BBM) can be guaranteed located in data chunk. The
+ECC layout always using the unbalanced layout(Ecc for both meta and
+Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
+cannot support because BCH doesn’t support GF 15 for 2K chunk.
+
+The change keeps the data chunk no larger than 1k and adjust the ECC
+strength or ECC layout to locate the BBM in data chunk. General idea for
+large oob NAND chips is
+
+1.Try all ECC strength from the minimum value required by NAND spec to
+the maximum one that works, any ECC makes the BBM locate in data chunk
+can be chosen.
+
+2.If none of them works, using separate ECC for meta, which will add one
+extra ecc with the same ECC strength as other data chunks. This extra
+ECC can guarantee BBM located in data chunk, of course, we need to check
+if oob can afford it.
+
+Previous code has two methods for ECC layout setting, the
+legacy_set_geometry and set_geometry_by_ecc_info, the difference
+between these two methods is, legacy_set_geometry set the chunk size
+larger chan oob size and then set the maximum ECC strength that oob can
+afford. While the set_geometry_by_ecc_info set chunk size and ECC
+strength according to NAND spec. It has been proved that the first
+method cannot provide safe ECC strength for some modern NAND chips, so
+in current code,
+
+1. Driver read NAND parameters first and then chose the proper ECC
+layout setting method.
+
+2. If the oob is large or NAND required data chunk larger than oob size,
+chose set_geometry_for_large_oob, otherwise use set_geometry_by_ecc_info
+
+3. legacy_set_geometry only used for some NAND chips does not contains
+necessary information. So this is only a backup plan, it is NOT
+recommended to use these NAND chips.
+
+Signed-off-by: Han Xu <b45815@freescale.com>
+(cherry picked from commit 78e8beff734adb72185405ae2cb55e0097eb96cb)
+Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
+---
+ drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c  |  16 +-
+ drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 269 ++++++++++++++++++++++++-----
+ drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h |  12 +-
+ 3 files changed, 248 insertions(+), 49 deletions(-)
+
+diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c
+index 83697b8df871..921af1824590 100644
+--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c
++++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c
+@@ -225,7 +225,8 @@ void gpmi_dump_info(struct gpmi_nand_data *this)
+ 		"ECC Strength           : %u\n"
+ 		"Page Size in Bytes     : %u\n"
+ 		"Metadata Size in Bytes : %u\n"
+-		"ECC Chunk Size in Bytes: %u\n"
++		"ECC Chunk0 Size in Bytes: %u\n"
++		"ECC Chunkn Size in Bytes: %u\n"
+ 		"ECC Chunk Count        : %u\n"
+ 		"Payload Size in Bytes  : %u\n"
+ 		"Auxiliary Size in Bytes: %u\n"
+@@ -236,7 +237,8 @@ void gpmi_dump_info(struct gpmi_nand_data *this)
+ 		geo->ecc_strength,
+ 		geo->page_size,
+ 		geo->metadata_size,
+-		geo->ecc_chunk_size,
++		geo->ecc_chunk0_size,
++		geo->ecc_chunkn_size,
+ 		geo->ecc_chunk_count,
+ 		geo->payload_size,
+ 		geo->auxiliary_size,
+@@ -251,7 +253,8 @@ int bch_set_geometry(struct gpmi_nand_data *this)
+ 	struct resources *r = &this->resources;
+ 	struct bch_geometry *bch_geo = &this->bch_geometry;
+ 	unsigned int block_count;
+-	unsigned int block_size;
++	unsigned int block0_size;
++	unsigned int blockn_size;
+ 	unsigned int metadata_size;
+ 	unsigned int ecc_strength;
+ 	unsigned int page_size;
+@@ -263,7 +266,8 @@ int bch_set_geometry(struct gpmi_nand_data *this)
+ 		return ret;
+ 
+ 	block_count   = bch_geo->ecc_chunk_count - 1;
+-	block_size    = bch_geo->ecc_chunk_size;
++	block0_size    = bch_geo->ecc_chunk0_size;
++	blockn_size    = bch_geo->ecc_chunkn_size;
+ 	metadata_size = bch_geo->metadata_size;
+ 	ecc_strength  = bch_geo->ecc_strength >> 1;
+ 	page_size     = bch_geo->page_size;
+@@ -290,13 +294,13 @@ int bch_set_geometry(struct gpmi_nand_data *this)
+ 			| BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
+ 			| BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
+ 			| BF_BCH_FLASH0LAYOUT0_GF(gf_len, this)
+-			| BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this),
++			| BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block0_size, this),
+ 			r->bch_regs + HW_BCH_FLASH0LAYOUT0);
+ 
+ 	writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
+ 			| BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this)
+ 			| BF_BCH_FLASH0LAYOUT1_GF(gf_len, this)
+-			| BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this),
++			| BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(blockn_size, this),
+ 			r->bch_regs + HW_BCH_FLASH0LAYOUT1);
+ 
+ 	/* Set *all* chip selects to use layout 0. */
+diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
+index f6aa358a3452..8c0f2a83e2a3 100644
+--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
++++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
+@@ -192,6 +192,36 @@ static inline bool gpmi_check_ecc(struct gpmi_nand_data *this)
+ 	return geo->ecc_strength <= this->devdata->bch_max_ecc_strength;
+ }
+ 
++static inline bool bbm_in_data_chunk(struct gpmi_nand_data *this,
++		unsigned int *chunk_num)
++{
++	struct bch_geometry *geo = &this->bch_geometry;
++	struct mtd_info *mtd = &this->nand.mtd;
++	unsigned int i, j;
++
++	if (geo->ecc_chunk0_size != geo->ecc_chunkn_size) {
++		dev_err(this->dev, "The size of chunk0 must equal to chunkn\n");
++		return false;
++	}
++
++	i = (mtd->writesize * 8 - geo->metadata_size * 8) /
++		(geo->gf_len * geo->ecc_strength +
++				geo->ecc_chunkn_size * 8);
++
++	j = (mtd->writesize * 8 - geo->metadata_size * 8) -
++		(geo->gf_len * geo->ecc_strength +
++				geo->ecc_chunkn_size * 8) * i;
++
++	if (j < geo->ecc_chunkn_size * 8) {
++		*chunk_num = i+1;
++		dev_dbg(this->dev, "Set ecc to %d and bbm in chunk %d\n",
++				geo->ecc_strength, *chunk_num);
++		return true;
++	}
++
++	return false;
++}
++
+ /*
+  * If we can get the ECC information from the nand chip, we do not
+  * need to calculate them ourselves.
+@@ -220,13 +250,14 @@ static int set_geometry_by_ecc_info(struct gpmi_nand_data *this,
+ 			chip->ecc_strength_ds, chip->ecc_step_ds);
+ 		return -EINVAL;
+ 	}
+-	geo->ecc_chunk_size = ecc_step;
+-	geo->ecc_strength = round_up(ecc_strength, 2);
++	geo->ecc_chunk0_size = chip->ecc_step_ds;
++	geo->ecc_chunkn_size = chip->ecc_step_ds;
++	geo->ecc_strength = round_up(chip->ecc_strength_ds, 2);
+ 	if (!gpmi_check_ecc(this))
+ 		return -EINVAL;
+ 
+ 	/* Keep the C >= O */
+-	if (geo->ecc_chunk_size < mtd->oobsize) {
++	if (geo->ecc_chunkn_size < mtd->oobsize) {
+ 		dev_err(this->dev,
+ 			"unsupported nand chip. ecc size: %d, oob size : %d\n",
+ 			ecc_step, mtd->oobsize);
+@@ -236,7 +267,7 @@ static int set_geometry_by_ecc_info(struct gpmi_nand_data *this,
+ 	/* The default value, see comment in the legacy_set_geometry(). */
+ 	geo->metadata_size = 10;
+ 
+-	geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
++	geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size;
+ 
+ 	/*
+ 	 * Now, the NAND chip with 2K page(data chunk is 512byte) shows below:
+@@ -308,6 +339,129 @@ static int set_geometry_by_ecc_info(struct gpmi_nand_data *this,
+ 	return 0;
+ }
+ 
++static int set_geometry_for_large_oob(struct gpmi_nand_data *this)
++{
++	struct bch_geometry *geo = &this->bch_geometry;
++	struct mtd_info *mtd = &this->nand.mtd;
++	struct nand_chip *chip = mtd->priv;
++	unsigned int block_mark_bit_offset;
++	unsigned int max_ecc;
++	unsigned int bbm_chunk;
++	unsigned int i;
++
++
++	/* sanity check for the minimum ecc nand required */
++	if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
++		return -EINVAL;
++	geo->ecc_strength = chip->ecc_strength_ds;
++
++	/* check if platform can support this nand */
++	if (!gpmi_check_ecc(this)) {
++		dev_err(this->dev, "unsupported NAND chip, minimum ecc required %d\n"
++				, geo->ecc_strength);
++		return -EINVAL;
++	}
++
++	/* calculate the maximum ecc platform can support*/
++	geo->metadata_size = 10;
++	geo->gf_len = 14;
++	geo->ecc_chunk0_size = 1024;
++	geo->ecc_chunkn_size = 1024;
++	geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size;
++	max_ecc = min(get_ecc_strength(this),
++			this->devdata->bch_max_ecc_strength);
++
++	/* search a supported ecc strength that makes bbm */
++	/* located in data chunk  */
++	geo->ecc_strength = chip->ecc_strength_ds;
++	while (!(geo->ecc_strength > max_ecc)) {
++		if (bbm_in_data_chunk(this, &bbm_chunk))
++			goto geo_setting;
++		geo->ecc_strength += 2;
++	}
++
++	/* if none of them works, keep using the minimum ecc */
++	/* nand required but changing ecc page layout  */
++	geo->ecc_strength = chip->ecc_strength_ds;
++	/* add extra ecc for meta data */
++	geo->ecc_chunk0_size = 0;
++	geo->ecc_chunk_count = (mtd->writesize / geo->ecc_chunkn_size) + 1;
++	geo->ecc_for_meta = 1;
++	/* check if oob can afford this extra ecc chunk */
++	if (mtd->oobsize * 8 < geo->metadata_size * 8 +
++			geo->gf_len * geo->ecc_strength
++			* geo->ecc_chunk_count) {
++		dev_err(this->dev, "unsupported NAND chip with new layout\n");
++		return -EINVAL;
++	}
++
++	/* calculate in which chunk bbm located */
++	bbm_chunk = (mtd->writesize * 8 - geo->metadata_size * 8 -
++		geo->gf_len * geo->ecc_strength) /
++		(geo->gf_len * geo->ecc_strength +
++				geo->ecc_chunkn_size * 8) + 1;
++
++geo_setting:
++
++	geo->page_size = mtd->writesize + mtd->oobsize;
++	geo->payload_size = mtd->writesize;
++
++	/*
++	 * The auxiliary buffer contains the metadata and the ECC status. The
++	 * metadata is padded to the nearest 32-bit boundary. The ECC status
++	 * contains one byte for every ECC chunk, and is also padded to the
++	 * nearest 32-bit boundary.
++	 */
++	geo->auxiliary_status_offset = ALIGN(geo->metadata_size, 4);
++	geo->auxiliary_size = ALIGN(geo->metadata_size, 4)
++				+ ALIGN(geo->ecc_chunk_count, 4);
++
++	if (!this->swap_block_mark)
++		return 0;
++
++	/* calculate the number of ecc chunk behind the bbm */
++	i = (mtd->writesize / geo->ecc_chunkn_size) - bbm_chunk + 1;
++
++	block_mark_bit_offset = mtd->writesize * 8 -
++		(geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - i)
++				+ geo->metadata_size * 8);
++
++	geo->block_mark_byte_offset = block_mark_bit_offset / 8;
++	geo->block_mark_bit_offset  = block_mark_bit_offset % 8;
++
++	dev_dbg(this->dev, "BCH Geometry :\n"
++		"GF length              : %u\n"
++		"ECC Strength           : %u\n"
++		"Page Size in Bytes     : %u\n"
++		"Metadata Size in Bytes : %u\n"
++		"ECC Chunk0 Size in Bytes: %u\n"
++		"ECC Chunkn Size in Bytes: %u\n"
++		"ECC Chunk Count        : %u\n"
++		"Payload Size in Bytes  : %u\n"
++		"Auxiliary Size in Bytes: %u\n"
++		"Auxiliary Status Offset: %u\n"
++		"Block Mark Byte Offset : %u\n"
++		"Block Mark Bit Offset  : %u\n"
++		"Block Mark in chunk	: %u\n"
++		"Ecc for Meta data	: %u\n",
++		geo->gf_len,
++		geo->ecc_strength,
++		geo->page_size,
++		geo->metadata_size,
++		geo->ecc_chunk0_size,
++		geo->ecc_chunkn_size,
++		geo->ecc_chunk_count,
++		geo->payload_size,
++		geo->auxiliary_size,
++		geo->auxiliary_status_offset,
++		geo->block_mark_byte_offset,
++		geo->block_mark_bit_offset,
++		bbm_chunk,
++		geo->ecc_for_meta);
++
++	return 0;
++}
++
+ static int legacy_set_geometry(struct gpmi_nand_data *this)
+ {
+ 	struct bch_geometry *geo = &this->bch_geometry;
+@@ -327,13 +481,15 @@ static int legacy_set_geometry(struct gpmi_nand_data *this)
+ 	geo->gf_len = 13;
+ 
+ 	/* The default for chunk size. */
+-	geo->ecc_chunk_size = 512;
+-	while (geo->ecc_chunk_size < mtd->oobsize) {
+-		geo->ecc_chunk_size *= 2; /* keep C >= O */
++	geo->ecc_chunk0_size = 512;
++	geo->ecc_chunkn_size = 512;
++	while (geo->ecc_chunkn_size < mtd->oobsize) {
++		geo->ecc_chunk0_size *= 2; /* keep C >= O */
++		geo->ecc_chunkn_size *= 2; /* keep C >= O */
+ 		geo->gf_len = 14;
+ 	}
+ 
+-	geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
++	geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size;
+ 
+ 	/* We use the same ECC strength for all chunks. */
+ 	geo->ecc_strength = get_ecc_strength(this);
+@@ -422,22 +578,25 @@ static int legacy_set_geometry(struct gpmi_nand_data *this)
+ 
+ int common_nfc_set_geometry(struct gpmi_nand_data *this)
+ {
+-	struct nand_chip *chip = &this->nand;
++	struct mtd_info *mtd = &this->nand.mtd;
++	struct nand_chip *chip = mtd_to_nand(mtd);
+ 
+-	if (chip->ecc.strength > 0 && chip->ecc.size > 0)
+-		return set_geometry_by_ecc_info(this, chip->ecc.strength,
+-						chip->ecc.size);
++	if (chip->ecc_strength_ds > this->devdata->bch_max_ecc_strength) {
++		dev_err(this->dev,
++			"unsupported NAND chip, minimum ecc required %d\n"
++			, chip->ecc_strength_ds);
++		return -EINVAL;
++	}
+ 
+-	if ((of_property_read_bool(this->dev->of_node, "fsl,use-minimum-ecc"))
+-				|| legacy_set_geometry(this)) {
+-		if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
+-			return -EINVAL;
++	if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) &&
++			!(mtd->oobsize > 1024))
++		return legacy_set_geometry(this);
+ 
+-		return set_geometry_by_ecc_info(this, chip->ecc_strength_ds,
+-						chip->ecc_step_ds);
+-	}
++	if (mtd->oobsize > 1024 || chip->ecc_step_ds < mtd->oobsize)
++		return set_geometry_for_large_oob(this);
+ 
+-	return 0;
++	return set_geometry_by_ecc_info(this, chip->ecc_strength_ds,
++			chip->ecc_step_ds);
+ }
+ 
+ struct dma_chan *get_dma_chan(struct gpmi_nand_data *this)
+@@ -1013,7 +1172,8 @@ static int gpmi_ecc_read_page_data(struct nand_chip *chip,
+ 
+ 			/* Read ECC bytes into our internal raw_buffer */
+ 			offset = nfc_geo->metadata_size * 8;
+-			offset += ((8 * nfc_geo->ecc_chunk_size) + eccbits) * (i + 1);
++			offset += ((8 * nfc_geo->ecc_chunkn_size) + eccbits) *
++				(i + 1);
+ 			offset -= eccbits;
+ 			bitoffset = offset % 8;
+ 			eccbytes = DIV_ROUND_UP(offset + eccbits, 8);
+@@ -1050,19 +1210,19 @@ static int gpmi_ecc_read_page_data(struct nand_chip *chip,
+ 			if (i == 0) {
+ 				/* The first block includes metadata */
+ 				flips = nand_check_erased_ecc_chunk(
+-						buf + i * nfc_geo->ecc_chunk_size,
+-						nfc_geo->ecc_chunk_size,
+-						eccbuf, eccbytes,
+-						this->auxiliary_virt,
+-						nfc_geo->metadata_size,
+-						nfc_geo->ecc_strength);
++					buf + i * nfc_geo->ecc_chunkn_size,
++					nfc_geo->ecc_chunkn_size,
++					eccbuf, eccbytes,
++					payload_virt,
++					nfc_geo->metadata_size,
++					nfc_geo->ecc_strength);
+ 			} else {
+ 				flips = nand_check_erased_ecc_chunk(
+-						buf + i * nfc_geo->ecc_chunk_size,
+-						nfc_geo->ecc_chunk_size,
+-						eccbuf, eccbytes,
+-						NULL, 0,
+-						nfc_geo->ecc_strength);
++					buf + i * nfc_geo->ecc_chunkn_size,
++					nfc_geo->ecc_chunkn_size,
++					eccbuf, eccbytes,
++					NULL, 0,
++					nfc_geo->ecc_strength);
+ 			}
+ 
+ 			if (flips > 0) {
+@@ -1150,9 +1310,24 @@ static int gpmi_ecc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
+ 		}
+ 	}
+ 
++	/*
++	 * if there is an ECC dedicate for meta:
++	 * - need to add an extra ECC size when calculating col and page_size,
++	 *   if the meta size is NOT zero.
++	 *
++	 * - chunk0 size need to set to the same size as other chunks,
++	 *   if the meta size is zero.
++	 */
++
+ 	meta = geo->metadata_size;
+ 	if (first) {
+-		col = meta + (size + ecc_parity_size) * first;
++		if (geo->ecc_for_meta)
++			col = meta + ecc_parity_size
++				+ (size + ecc_parity_size) * first;
++		else
++			col = meta + (size + ecc_parity_size) * first;
++
++		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+ 		meta = 0;
+ 		buf = buf + first * size;
+ 	}
+@@ -1165,21 +1340,37 @@ static int gpmi_ecc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
+ 
+ 	/* change the BCH registers and bch_geometry{} */
+ 	n = last - first + 1;
+-	page_size = meta + (size + ecc_parity_size) * n;
++
++	if (geo->ecc_for_meta && meta)
++		page_size = meta + ecc_parity_size
++			+ (size + ecc_parity_size) * n;
++	else
++		page_size = meta + (size + ecc_parity_size) * n;
+ 
+ 	r1_new &= ~(BM_BCH_FLASH0LAYOUT0_NBLOCKS |
+ 			BM_BCH_FLASH0LAYOUT0_META_SIZE);
+-	r1_new |= BF_BCH_FLASH0LAYOUT0_NBLOCKS(n - 1)
++	r1_new |= BF_BCH_FLASH0LAYOUT0_NBLOCKS(
++			(geo->ecc_for_meta && meta) ? n : n - 1)
+ 			| BF_BCH_FLASH0LAYOUT0_META_SIZE(meta);
++
++	/* set chunk0 size if meta size is 0 */
++	if (!meta) {
++		if (GPMI_IS_MX6(this))
++			r1_new &= ~MX6Q_BM_BCH_FLASH0LAYOUT0_DATA0_SIZE;
++		else
++			r1_new &= ~BM_BCH_FLASH0LAYOUT0_DATA0_SIZE;
++		r1_new |= BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(size, this);
++	}
+ 	writel(r1_new, bch_regs + HW_BCH_FLASH0LAYOUT0);
+ 
+ 	r2_new &= ~BM_BCH_FLASH0LAYOUT1_PAGE_SIZE;
+ 	r2_new |= BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size);
+ 	writel(r2_new, bch_regs + HW_BCH_FLASH0LAYOUT1);
+ 
+-	geo->ecc_chunk_count = n;
++	geo->ecc_chunk_count = (geo->ecc_for_meta && meta) ? n + 1 : n;
+ 	geo->payload_size = n * size;
+ 	geo->page_size = page_size;
++	geo->metadata_size = meta;
+ 	geo->auxiliary_status_offset = ALIGN(meta, 4);
+ 
+ 	dev_dbg(this->dev, "page:%d(%d:%d)%d, chunk:(%d:%d), BCH PG size:%d\n",
+@@ -1402,7 +1593,7 @@ static int gpmi_ecc_read_page_raw(struct mtd_info *mtd,
+ {
+ 	struct gpmi_nand_data *this = nand_get_controller_data(chip);
+ 	struct bch_geometry *nfc_geo = &this->bch_geometry;
+-	int eccsize = nfc_geo->ecc_chunk_size;
++	int eccsize = nfc_geo->ecc_chunkn_size;
+ 	int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len;
+ 	u8 *tmp_buf = this->raw_buffer;
+ 	size_t src_bit_off;
+@@ -1487,7 +1678,7 @@ static int gpmi_ecc_write_page_raw(struct mtd_info *mtd,
+ {
+ 	struct gpmi_nand_data *this = nand_get_controller_data(chip);
+ 	struct bch_geometry *nfc_geo = &this->bch_geometry;
+-	int eccsize = nfc_geo->ecc_chunk_size;
++	int eccsize = nfc_geo->ecc_chunkn_size;
+ 	int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len;
+ 	u8 *tmp_buf = this->raw_buffer;
+ 	uint8_t *oob = chip->oob_poi;
+@@ -1863,7 +2054,7 @@ static int gpmi_init_last(struct gpmi_nand_data *this)
+ 	ecc->read_oob_raw = gpmi_ecc_read_oob_raw;
+ 	ecc->write_oob_raw = gpmi_ecc_write_oob_raw;
+ 	ecc->mode	= NAND_ECC_HW;
+-	ecc->size	= bch_geo->ecc_chunk_size;
++	ecc->size	= bch_geo->ecc_chunkn_size;
+ 	ecc->strength	= bch_geo->ecc_strength;
+ 	mtd_set_ooblayout(mtd, &gpmi_ooblayout_ops);
+ 
+diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
+index 6aa10d6962d6..fb50520608ac 100644
+--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
++++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
+@@ -39,9 +39,9 @@ struct resources {
+  * @page_size:                The size, in bytes, of a physical page, including
+  *                            both data and OOB.
+  * @metadata_size:            The size, in bytes, of the metadata.
+- * @ecc_chunk_size:           The size, in bytes, of a single ECC chunk. Note
+- *                            the first chunk in the page includes both data and
+- *                            metadata, so it's a bit larger than this value.
++ * @ecc_chunk0_size:          The size, in bytes, of a first ECC chunk.
++ * @ecc_chunkn_size:          The size, in bytes, of a single ECC chunk after
++ *                            the first chunk in the page.
+  * @ecc_chunk_count:          The number of ECC chunks in the page,
+  * @payload_size:             The size, in bytes, of the payload buffer.
+  * @auxiliary_size:           The size, in bytes, of the auxiliary buffer.
+@@ -51,19 +51,23 @@ struct resources {
+  *                            which the underlying physical block mark appears.
+  * @block_mark_bit_offset:    The bit offset into the ECC-based page view at
+  *                            which the underlying physical block mark appears.
++ * @ecc_for_meta:             The flag to indicate if there is a dedicate ecc
++ *                            for meta.
+  */
+ struct bch_geometry {
+ 	unsigned int  gf_len;
+ 	unsigned int  ecc_strength;
+ 	unsigned int  page_size;
+ 	unsigned int  metadata_size;
+-	unsigned int  ecc_chunk_size;
++	unsigned int  ecc_chunk0_size;
++	unsigned int  ecc_chunkn_size;
+ 	unsigned int  ecc_chunk_count;
+ 	unsigned int  payload_size;
+ 	unsigned int  auxiliary_size;
+ 	unsigned int  auxiliary_status_offset;
+ 	unsigned int  block_mark_byte_offset;
+ 	unsigned int  block_mark_bit_offset;
++	unsigned int  ecc_for_meta; /* ECC for meta data */
+ };
+ 
+ /**
diff --git a/recipes-kernel/linux/linux-fslc/ccimx6ul/0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch b/recipes-kernel/linux/linux-fslc/ccimx6ul/0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch
new file mode 100644
index 000000000000..bcd42bb8f2a1
--- /dev/null
+++ b/recipes-kernel/linux/linux-fslc/ccimx6ul/0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch
@@ -0,0 +1,115 @@ 
+From d29d8485ed649d45aa11b4a6081fb121f65fb41a Mon Sep 17 00:00:00 2001
+From: Anson Huang <Anson.Huang@nxp.com>
+Date: Mon, 8 Oct 2018 14:07:34 +0800
+Subject: [PATCH 2/5] cpufreq: imx6q: read OCOTP through nvmem for
+ imx6ul/imx6ull
+
+On i.MX6UL/i.MX6ULL, accessing OCOTP directly is wrong because
+the ocotp clock needs to be enabled first. Add support for reading
+OCOTP through the nvmem API, and keep the old method there to
+support old dtb.
+
+Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
+Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+(cherry picked from commit 2733fb0d0699246711cf622e0e2faf02a05b69dc)
+---
+ drivers/cpufreq/imx6q-cpufreq.c | 52 +++++++++++++++++++++++++++--------------
+ 1 file changed, 35 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
+index 8b3c2a79ad6c..564bc23f709b 100644
+--- a/drivers/cpufreq/imx6q-cpufreq.c
++++ b/drivers/cpufreq/imx6q-cpufreq.c
+@@ -11,6 +11,7 @@
+ #include <linux/cpufreq.h>
+ #include <linux/err.h>
+ #include <linux/module.h>
++#include <linux/nvmem-consumer.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/pm_opp.h>
+@@ -269,20 +270,32 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
+ #define OCOTP_CFG3_6ULL_SPEED_792MHZ	0x2
+ #define OCOTP_CFG3_6ULL_SPEED_900MHZ	0x3
+ 
+-static void imx6ul_opp_check_speed_grading(struct device *dev)
++static int imx6ul_opp_check_speed_grading(struct device *dev)
+ {
+-	struct device_node *np;
+-	void __iomem *base;
+ 	u32 val;
++	int ret = 0;
+ 
+-	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
+-	if (!np)
+-		return;
++	if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
++		ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
++		if (ret)
++			return ret;
++	} else {
++		struct device_node *np;
++		void __iomem *base;
++
++		np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
++		if (!np)
++			return -ENOENT;
++
++		base = of_iomap(np, 0);
++		of_node_put(np);
++		if (!base) {
++			dev_err(dev, "failed to map ocotp\n");
++			return -EFAULT;
++		}
+ 
+-	base = of_iomap(np, 0);
+-	if (!base) {
+-		dev_err(dev, "failed to map ocotp\n");
+-		goto put_node;
++		val = readl_relaxed(base + OCOTP_CFG3);
++		iounmap(base);
+ 	}
+ 
+ 	/*
+@@ -293,7 +306,6 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
+ 	 * 2b'11: 900000000Hz on i.MX6ULL only;
+ 	 * We need to set the max speed of ARM according to fuse map.
+ 	 */
+-	val = readl_relaxed(base + OCOTP_CFG3);
+ 	val >>= OCOTP_CFG3_SPEED_SHIFT;
+ 	val &= 0x3;
+ 
+@@ -313,9 +325,7 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
+ 				dev_warn(dev, "failed to disable 900MHz OPP\n");
+ 	}
+ 
+-	iounmap(base);
+-put_node:
+-	of_node_put(np);
++	return ret;
+ }
+ 
+ static int imx6q_cpufreq_probe(struct platform_device *pdev)
+@@ -373,10 +383,18 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	if (of_machine_is_compatible("fsl,imx6ul") ||
+-	    of_machine_is_compatible("fsl,imx6ull"))
+-		imx6ul_opp_check_speed_grading(cpu_dev);
+-	else
++	    of_machine_is_compatible("fsl,imx6ull")) {
++		ret = imx6ul_opp_check_speed_grading(cpu_dev);
++		if (ret == -EPROBE_DEFER)
++			return ret;
++		if (ret) {
++			dev_err(cpu_dev, "failed to read ocotp: %d\n",
++				ret);
++			return ret;
++		}
++	} else {
+ 		imx6q_opp_check_speed_grading(cpu_dev);
++	}
+ 
+ 	/* Because we have added the OPPs here, we must free them */
+ 	free_opp = true;
diff --git a/recipes-kernel/linux/linux-fslc/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch b/recipes-kernel/linux/linux-fslc/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch
new file mode 100644
index 000000000000..27f4666d513b
--- /dev/null
+++ b/recipes-kernel/linux/linux-fslc/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch
@@ -0,0 +1,39 @@ 
+From 6e7242f21f0d9461e1ad3b13a4118c44e17cfa38 Mon Sep 17 00:00:00 2001
+From: Anson Huang <Anson.Huang@nxp.com>
+Date: Fri, 14 Sep 2018 10:59:21 +0800
+Subject: [PATCH 3/5] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
+
+On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
+needs to be enabled first, so use the nvmem-cells binding instead.
+
+Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+(cherry picked from commit 92f0eb08c66a73594cf200e65689e767f7f0da5e)
+---
+ arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
+index 47a3453a4211..9670f15bcb31 100644
+--- a/arch/arm/boot/dts/imx6ul.dtsi
++++ b/arch/arm/boot/dts/imx6ul.dtsi
+@@ -88,6 +88,8 @@
+ 				      "pll1_sys";
+ 			arm-supply = <&reg_arm>;
+ 			soc-supply = <&reg_soc>;
++			nvmem-cells = <&cpu_speed_grade>;
++			nvmem-cell-names = "speed_grade";
+ 		};
+ 	};
+ 
+@@ -926,6 +928,10 @@
+ 				tempmon_temp_grade: temp-grade@20 {
+ 					reg = <0x20 4>;
+ 				};
++
++				cpu_speed_grade: speed-grade@10 {
++					reg = <0x10 4>;
++				};
+ 			};
+ 
+ 			lcdif: lcdif@21c8000 {
diff --git a/recipes-kernel/linux/linux-fslc/ccimx6ul/0004-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch b/recipes-kernel/linux/linux-fslc/ccimx6ul/0004-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch
new file mode 100644
index 000000000000..6658df5895af
--- /dev/null
+++ b/recipes-kernel/linux/linux-fslc/ccimx6ul/0004-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch
@@ -0,0 +1,236 @@ 
+From f41c981a8a997b50077943ce21659ad7e73e8365 Mon Sep 17 00:00:00 2001
+From: Alex Gonzalez <alex.gonzalez@digi.com>
+Date: Thu, 12 Jul 2018 10:20:35 +0200
+Subject: [PATCH 4/5] ARM: dts: imx6ul: Add DTS for ConnectCore 6UL
+ System-On-Module (SOM)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The ConnectCore 6UL System-On-Module has the following hardware
+specification:
+
+* Based on a NXP i.MX6UL SoC
+* Industrial temperature ranges (-40ºC to +85ºC)
+* Up to 1GB DDR3 memory
+* Up to 2GB NAND flash
+* Dual Ethernet
+* On module 802.11 WiFi and Bluetooth 4.2 (QCA6564)
+* On module NXP Kinetis KL03
+* On module Microchip ATECC508A crypto element
+
+Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+(cherry picked from commit 0b9c89e213d227d3649a1cb77bb6b912fbd532f9)
+---
+ arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi | 201 ++++++++++++++++++++++++++++++
+ 1 file changed, 201 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi
+
+diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi
+new file mode 100644
+index 000000000000..c71a84da1af0
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi
+@@ -0,0 +1,201 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Digi International's ConnectCore 6UL System-On-Module device tree source
++ *
++ * Copyright 2018 Digi International, Inc.
++ *
++ */
++
++/ {
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges;
++
++		linux,cma {
++			compatible = "shared-dma-pool";
++			reusable;
++			size = <0x4000000>;
++			linux,cma-default;
++		};
++	};
++};
++
++&adc1 {
++	vref-supply = <&vdda_adc_3v3>;
++};
++
++&gpmi {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_gpmi_nand>;
++	status = "okay";
++};
++
++&i2c1 {
++	clock-frequency = <100000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_i2c1>;
++	status = "okay";
++
++	pfuze3000: pmic@8 {
++		compatible = "fsl,pfuze3000";
++		reg = <0x08>;
++
++		regulators {
++			int_3v3: sw1a {
++				regulator-min-microvolt = <700000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <6250>;
++				regulator-boot-on;
++				regulator-always-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_arm_soc_in: sw1b {
++				regulator-min-microvolt = <700000>;
++				regulator-max-microvolt = <1475000>;
++				regulator-ramp-delay = <6250>;
++				regulator-boot-on;
++				regulator-always-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <925000>;
++				};
++			};
++
++			ext_3v3: sw2 {
++				regulator-min-microvolt = <2500000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <6250>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr3: sw3 {
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <1650000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1300000>;
++				};
++			};
++
++			swbst_reg: swbst {
++				regulator-min-microvolt = <5000000>;
++				regulator-max-microvolt = <5150000>;
++			};
++
++			vdd_snvs_3v3: vsnvs {
++				regulator-min-microvolt = <1000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			vrefddr: vrefddr {
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			vdda_adc_3v3: vldo1 {
++				compatible = "regulator-fixed";
++				regulator-name = "vref-adc-3v3";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			ldo2_ext: vldo2 {
++				regulator-min-microvolt = <800000>;
++				regulator-max-microvolt = <1550000>;
++			};
++
++			vdda_wlan: vccsd {
++				regulator-min-microvolt = <2850000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_high_in: v33 {
++				regulator-min-microvolt = <2850000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			ldo3_int: vldo3 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			ldo4_ext: vldo4 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			vcoin_chg: vcoin {
++				regulator-min-microvolt = <2500000>;
++				regulator-max-microvolt = <3300000>;
++			};
++		};
++	};
++};
++
++&iomuxc {
++	pinctrl_gpmi_nand: gpmigrp {
++		fsl,pins = <
++			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0xb0b1
++			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0xb0b1
++			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0xb0b1
++			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0xb0b1
++			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0xb0b1
++			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0xb0b1
++			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0xb0b1
++			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0xb0b1
++			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0xb0b1
++			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0xb0b1
++			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0xb0b1
++			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0xb0b1
++			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0xb0b1
++			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0xb0b1
++			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0xb0b1
++			>;
++		};
++
++	pinctrl_i2c1: i2c1grp {
++		fsl,pins = <
++			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
++			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
++			>;
++		};
++};
++
++&reg_arm {
++	vin-supply = <&vdd_arm_soc_in>;
++	regulator-allow-bypass;
++};
++
++&reg_soc {
++	vin-supply = <&vdd_arm_soc_in>;
++	regulator-allow-bypass;
++};
diff --git a/recipes-kernel/linux/linux-fslc/ccimx6ul/0005-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch b/recipes-kernel/linux/linux-fslc/ccimx6ul/0005-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch
new file mode 100644
index 000000000000..2cdc4d8af26d
--- /dev/null
+++ b/recipes-kernel/linux/linux-fslc/ccimx6ul/0005-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch
@@ -0,0 +1,244 @@ 
+From 9ca4211642dc7d6521594b58600ecab8088039e2 Mon Sep 17 00:00:00 2001
+From: Alex Gonzalez <alex.gonzalez@digi.com>
+Date: Thu, 12 Jul 2018 10:20:36 +0200
+Subject: [PATCH 5/5] ARM: dts: imx6ul: Add DTS for ConnectCore 6UL SBC Express
+
+The ConnectCore 6UL Single Board Computer (SBC) Express contains the
+ConnectCore 6UL System-On-Module.
+
+Its hardware specifications are:
+
+* 256MB DDR3 memory
+* 256MB NAND flash
+* Single Ethernet
+* USB Host and USB-OTG
+* MicroSD external storage
+* Groove connectors and Raspberry Pi Hat compatible expansion header
+
+Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+(cherry picked from commit 8c7725829989d2711875f60356d22bc5af981ac0)
+---
+ arch/arm/boot/dts/Makefile                      |   1 +
+ arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts | 200 ++++++++++++++++++++++++
+ 2 files changed, 201 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 37a3de760d40..6135d3dc381c 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -533,6 +533,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
+ 	imx6sx-udoo-neo-full.dtb
+ dtb-$(CONFIG_SOC_IMX6UL) += \
+ 	imx6ul-14x14-evk.dtb \
++	imx6ul-ccimx6ulsbcexpress.dtb \
+ 	imx6ul-geam.dtb \
+ 	imx6ul-isiot-emmc.dtb \
+ 	imx6ul-isiot-nand.dtb \
+diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts
+new file mode 100644
+index 000000000000..3792679c0c90
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts
+@@ -0,0 +1,200 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Digi International's ConnectCore6UL SBC Express board device tree source
++ *
++ * Copyright 2018 Digi International, Inc.
++ *
++ */
++
++/dts-v1/;
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include "imx6ul.dtsi"
++#include "imx6ul-ccimx6ulsom.dtsi"
++
++/ {
++	model = "Digi International ConnectCore 6UL SBC Express.";
++	compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom",
++		     "fsl,imx6ul";
++};
++
++&adc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_adc1>;
++	status = "okay";
++};
++
++&can1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_flexcan1>;
++	xceiver-supply = <&ext_3v3>;
++	status = "okay";
++};
++
++&ecspi3 {
++	cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_ecspi3_master>;
++	status = "okay";
++};
++
++&fec1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_enet1>;
++	phy-mode = "rmii";
++	phy-handle = <&ethphy0>;
++	status = "okay";
++
++	mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		ethphy0: ethernet-phy@0 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			smsc,disable-energy-detect;
++			reg = <0>;
++		};
++	};
++};
++
++&i2c2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_i2c2>;
++	status = "okay";
++};
++
++&pwm1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm1>;
++	status = "okay";
++};
++
++&uart4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_uart4>;
++	status = "okay";
++};
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_uart5>;
++	status = "okay";
++};
++
++&usbotg1 {
++	dr_mode = "host";
++	disable-over-current;
++	status = "okay";
++};
++
++&usbotg2 {
++	dr_mode = "host";
++	disable-over-current;
++	status = "okay";
++};
++
++&usdhc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_usdhc2>;
++	broken-cd;      /* no carrier detect line (use polling) */
++	no-1-8-v;
++	status = "okay";
++};
++
++&iomuxc {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_hog>;
++
++	pinctrl_adc1: adc1grp {
++		fsl,pins = <
++			/* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */
++			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0xb0
++		>;
++	};
++
++	pinctrl_ecspi3_master: ecspi3grp1 {
++		fsl,pins = <
++			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
++			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
++			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
++			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0 /* Chip Select */
++		>;
++	};
++
++	pinctrl_ecspi3_slave: ecspi3grp2 {
++		fsl,pins = <
++			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
++			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
++			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
++			MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0	0x10b0 /* Chip Select */
++		>;
++	};
++
++	pinctrl_enet1: enet1grp {
++		fsl,pins = <
++			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
++			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
++			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
++			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
++			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
++			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
++			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
++			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
++			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
++			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x40017051
++		>;
++	};
++
++	pinctrl_flexcan1: flexcan1grp{
++		fsl,pins = <
++			MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX	0x1b020
++			MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX	0x1b020
++		>;
++	};
++
++	pinctrl_i2c2: i2c2grp {
++		fsl,pins = <
++			MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
++			MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
++		>;
++	};
++
++	pinctrl_pwm1: pwm1grp {
++		fsl,pins = <
++			MX6UL_PAD_LCD_DATA00__PWM1_OUT		0x10b0
++		>;
++	};
++
++	pinctrl_uart4: uart4grp {
++		fsl,pins = <
++			MX6UL_PAD_LCD_CLK__UART4_DCE_TX		0x1b0b1
++			MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX	0x1b0b1
++		>;
++	};
++
++	pinctrl_uart5: uart5grp {
++		fsl,pins = <
++			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
++			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
++		>;
++	};
++
++	pinctrl_usdhc2: usdhc2grp {
++		fsl,pins = <
++			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
++			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x10071
++			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
++			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
++			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
++			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
++		>;
++	};
++
++	/* General purpose pinctrl */
++	pinctrl_hog: hoggrp {
++		fsl,pins = <
++			/* GPIOs BANK 3 */
++			MX6UL_PAD_LCD_RESET__GPIO3_IO04		0xf030
++		>;
++	};
++};
diff --git a/recipes-kernel/linux/linux-fslc_%.bbappend b/recipes-kernel/linux/linux-fslc_%.bbappend
index 5b675d68630b..15af9917f6a2 100644
--- a/recipes-kernel/linux/linux-fslc_%.bbappend
+++ b/recipes-kernel/linux/linux-fslc_%.bbappend
@@ -8,6 +8,14 @@  SRC_URI_append_imx6qdl-variscite-som_use-mainline-bsp = " \
     file://imx6q-var-som-vsc.dts \
 "
 
+SRC_URI_append_ccimx6ul = " \
+    file://0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch \
+    file://0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch \
+    file://0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch \
+    file://0004-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-System-On.patch \
+    file://0005-ARM-dts-imx6ul-Add-DTS-for-ConnectCore-6UL-SBC-Expre.patch \
+"
+
 do_configure_prepend_imx6qdl-variscite-som() {
     cp ${WORKDIR}/imx6*-var*.dts* ${S}/arch/arm/boot/dts
 }