[1/2] rust-target-config: match riscv target names with what rust expects

Official rust risc-v targets are prefixed with riscv32gc- and riscv64gc-:
https://doc.rust-lang.org/nightly/rustc/platform-support.html

Particularly crossbeam-utils make important build time decisions
for atomics based on those names, and so we need to match ours
with official targets.

On the other hand, the actual definitions for those targets do not
use the 'gc' suffix in 'arch' and 'llvm-target' fields, and so we
need to follow that too, to avoid cryptic mismatch errors from rust-llvm:
https://github.com/rust-lang/rust/blob/master/compiler/rustc_target/src/spec/riscv32gc_unknown_linux_gnu.rs

Signed-off-by: Alexander Kanavin <alex@linutronix.de>
---
 .../classes-recipe/rust-target-config.bbclass | 40 ++++++++++++-------
 meta/lib/oe/rust.py                           |  2 +
 2 files changed, 28 insertions(+), 14 deletions(-)

On Tue, Oct 25, 2022 at 11:44 AM Alexander Kanavin
<alex.kanavin@gmail.com> wrote:
>
> Official rust risc-v targets are prefixed with riscv32gc- and riscv64gc-:
> https://doc.rust-lang.org/nightly/rustc/platform-support.html
>
> Particularly crossbeam-utils make important build time decisions
> for atomics based on those names, and so we need to match ours
> with official targets.
>
> On the other hand, the actual definitions for those targets do not
> use the 'gc' suffix in 'arch' and 'llvm-target' fields, and so we
> need to follow that too, to avoid cryptic mismatch errors from rust-llvm:
> https://github.com/rust-lang/rust/blob/master/compiler/rustc_target/src/spec/riscv32gc_unknown_linux_gnu.rs
>

This approach seems good to me. I wonder if rust_sys_to_llvm_target
would be problematic
for vardep calculations on native targets.

> Signed-off-by: Alexander Kanavin <alex@linutronix.de>
> ---
>  .../classes-recipe/rust-target-config.bbclass | 40 ++++++++++++-------
>  meta/lib/oe/rust.py                           |  2 +
>  2 files changed, 28 insertions(+), 14 deletions(-)
>
> diff --git a/meta/classes-recipe/rust-target-config.bbclass b/meta/classes-recipe/rust-target-config.bbclass
> index 9e1d81bf5c..2710b4325d 100644
> --- a/meta/classes-recipe/rust-target-config.bbclass
> +++ b/meta/classes-recipe/rust-target-config.bbclass
> @@ -231,19 +231,19 @@ TARGET_POINTER_WIDTH[powerpc64le] = "64"
>  TARGET_C_INT_WIDTH[powerpc64le] = "64"
>  MAX_ATOMIC_WIDTH[powerpc64le] = "64"
>
> -## riscv32-unknown-linux-{gnu, musl}
> -DATA_LAYOUT[riscv32] = "e-m:e-p:32:32-i64:64-n32-S128"
> -TARGET_ENDIAN[riscv32] = "little"
> -TARGET_POINTER_WIDTH[riscv32] = "32"
> -TARGET_C_INT_WIDTH[riscv32] = "32"
> -MAX_ATOMIC_WIDTH[riscv32] = "32"
> -
> -## riscv64-unknown-linux-{gnu, musl}
> -DATA_LAYOUT[riscv64] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
> -TARGET_ENDIAN[riscv64] = "little"
> -TARGET_POINTER_WIDTH[riscv64] = "64"
> -TARGET_C_INT_WIDTH[riscv64] = "64"
> -MAX_ATOMIC_WIDTH[riscv64] = "64"
> +## riscv32gc-unknown-linux-{gnu, musl}
> +DATA_LAYOUT[riscv32gc] = "e-m:e-p:32:32-i64:64-n32-S128"
> +TARGET_ENDIAN[riscv32gc] = "little"
> +TARGET_POINTER_WIDTH[riscv32gc] = "32"
> +TARGET_C_INT_WIDTH[riscv32gc] = "32"
> +MAX_ATOMIC_WIDTH[riscv32gc] = "32"
> +
> +## riscv64gc-unknown-linux-{gnu, musl}
> +DATA_LAYOUT[riscv64gc] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
> +TARGET_ENDIAN[riscv64gc] = "little"
> +TARGET_POINTER_WIDTH[riscv64gc] = "64"
> +TARGET_C_INT_WIDTH[riscv64gc] = "64"
> +MAX_ATOMIC_WIDTH[riscv64gc] = "64"
>
>  # Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something
>  # rust's internals won't choke on.
> @@ -258,9 +258,21 @@ def arch_to_rust_target_arch(arch):
>          return "arm"
>      elif arch == "powerpc64le":
>          return "powerpc64"
> +    elif arch == "riscv32gc":
> +        return "riscv32"
> +    elif arch == "riscv64gc":
> +        return "riscv64"
>      else:
>          return arch
>
> +# Convert a rust target string to a llvm-compatible triplet
> +def rust_sys_to_llvm_target(sys):
> +    if sys.startswith('riscv32gc-'):
> +        return sys.replace('riscv32gc-', 'riscv32-', 1)
> +    if sys.startswith('riscv64gc-'):
> +        return sys.replace('riscv64gc-', 'riscv64-', 1)
> +    return sys
> +
>  # generates our target CPU value
>  def llvm_cpu(d):
>      cpu = d.getVar('PACKAGE_ARCH')
> @@ -334,7 +346,7 @@ def rust_gen_target(d, thing, wd, arch):
>
>      # build tspec
>      tspec = {}
> -    tspec['llvm-target'] = rustsys
> +    tspec['llvm-target'] = rust_sys_to_llvm_target(rustsys)
>      tspec['data-layout'] = d.getVarFlag('DATA_LAYOUT', arch_abi)
>      if tspec['data-layout'] is None:
>          bb.fatal("No rust target defined for %s" % arch_abi)
> diff --git a/meta/lib/oe/rust.py b/meta/lib/oe/rust.py
> index 1dc9cf150d..185553eeeb 100644
> --- a/meta/lib/oe/rust.py
> +++ b/meta/lib/oe/rust.py
> @@ -8,4 +8,6 @@
>  def arch_to_rust_arch(arch):
>      if arch == "ppc64le":
>          return "powerpc64le"
> +    if arch in ('riscv32', 'riscv64'):
> +        return arch + 'gc'
>      return arch
> --
> 2.30.2
>
>
> -=-=-=-=-=-=-=-=-=-=-=-
> Links: You receive all messages sent to this group.
> View/Reply Online (#172141): https://lists.openembedded.org/g/openembedded-core/message/172141
> Mute This Topic: https://lists.openembedded.org/mt/94565465/1997914
> Group Owner: openembedded-core+owner@lists.openembedded.org
> Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub [raj.khem@gmail.com]
> -=-=-=-=-=-=-=-=-=-=-=-
>