mesa: upgrade 21.3.6 -> 21.3.7

Message ID 1646135949-39195-1-git-send-email-wangmy@fujitsu.com
State Accepted, archived
Commit 31daf916d218d5e6e95bac857cbeb0d44901e4b3
Headers show
Series mesa: upgrade 21.3.6 -> 21.3.7 | expand

Commit Message

Mingyu Wang (Fujitsu) March 1, 2022, 11:59 a.m. UTC
Changelog:
=========
Bug fixes
---------
lavapipe: dEQP-VK.spirv_assembly.instruction.compute.float16.arithmetic_3.step fails
ANV: Bad output from TransformFeedback . Regression from Mesa 21. Something to do with VB+XFB -> VB+XFB dependency?

Changes
-------
pan/bi: Avoid *FADD.v2f16 hazard in optimizer
pan/bi: Avoid *FADD.v2f16 hazard in scheduler
pan/bi: Lower swizzles on CSEL.i32/MUX.i32
panvk: Use more reliable assert for UBO pushing
radv: Fix preamble argument order.
ir3/spill: Fix simplify_phi_nodes with multiple loop nesting
lavapipe: fix sampler + sampler view leaks.
lavapipe: reference gallium fences correctly.
crocus: fix leak on gen4/5 stencil fallback blit path.
i915g: Initialize the rest of the "from_nir" temporary VS struct.
pick_status.json: Update to dabba7d7263be6ffb6f3676465e92c65952fa824
pick_status.json: Mark b07372312d7053f2ef5c858ceb1fbf9ade5e7c52 as denominated
gallivm/nir: Call nir_lower_bool_to_int32 after nir_opt_algebraic_late
nir: All set-on-comparison opcodes can take all float types
intel/fs: Don't optimize out 1.0*x and -1.0*x
spriv: Produce correct result for GLSLstd450Step with NaN
spirv: Produce correct result for GLSLstd450Modf with Inf
spirv: Produce correct result for GLSLstd450Tanh with NaN
nir: Properly handle various exceptional values in frexp
nir: Produce correct results for atan with NaN
nir: Add missing dependency on nir_opcodes.py
anv: Call vk_command_buffer_finish if create fails
dri: avoid NULL deref of DrawBuffer on flush
nir: fix lower_memcpy
anv/genxml/intel/fs: fix binding shader record entry
anv: don't set color state when input state was requested
ac/surface: add more elements to meta equations because HTILE can use them
lavapipe: use util_pack_color_union() for generating clear colors
aux/draw: fix llvm tcs lane vec generation
zink: always set VkPipelineMultisampleStateCreateInfo::pSampleMask
zink: always invalidate streamout counter buffer if not resuming
iris: Don't fast clear with the view format
r300: fix transformation of abs modifiers with negate
radeonsi: workaround Specviewperf13 Catia hang on GFX9
radeonsi: fix depth stencil multi sample texture blit
glx: fix pbuffer refcount init
radv/winsys: fix initializing debug/perftest options if multiple instances
intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
anv: invalidate L3 read only cache when VF cache is invalidated
iris: invalidate L3 read only cache when VF cache is invalidated
iris: fix a leak on surface states
mesa/st: always use DXT5 when transcoding ASTC format
tegra: Use private reference count for sampler views
tegra: Use private reference count for resources
radv: Disable IB2 on compute queues.
venus: properly destroy deferred ahb image before real image creation

Signed-off-by: Wang Mingyu <wangmy@fujitsu.com>
---
 .../mesa/{mesa-gl_21.3.6.bb => mesa-gl_21.3.7.bb}               | 0
 meta/recipes-graphics/mesa/mesa.inc                             | 2 +-
 meta/recipes-graphics/mesa/{mesa_21.3.6.bb => mesa_21.3.7.bb}   | 0
 3 files changed, 1 insertion(+), 1 deletion(-)
 rename meta/recipes-graphics/mesa/{mesa-gl_21.3.6.bb => mesa-gl_21.3.7.bb} (100%)
 rename meta/recipes-graphics/mesa/{mesa_21.3.6.bb => mesa_21.3.7.bb} (100%)

Patch

diff --git a/meta/recipes-graphics/mesa/mesa-gl_21.3.6.bb b/meta/recipes-graphics/mesa/mesa-gl_21.3.7.bb
similarity index 100%
rename from meta/recipes-graphics/mesa/mesa-gl_21.3.6.bb
rename to meta/recipes-graphics/mesa/mesa-gl_21.3.7.bb
diff --git a/meta/recipes-graphics/mesa/mesa.inc b/meta/recipes-graphics/mesa/mesa.inc
index cfd325add1..2f79e8b34d 100644
--- a/meta/recipes-graphics/mesa/mesa.inc
+++ b/meta/recipes-graphics/mesa/mesa.inc
@@ -23,7 +23,7 @@  SRC_URI = "https://mesa.freedesktop.org/archive/mesa-${PV}.tar.xz \
            file://0001-v3dv-account-for-64bit-time_t-on-32bit-arches.patch \
            "
 
-SRC_URI[sha256sum] = "96bb761fd546e9aa41d025fcc025225c5668443839dae21e3731959beb096736"
+SRC_URI[sha256sum] = "b4fa9db7aa61bf209ef0b40bef83080999d86ad98df8b8b4fada7c128a1efc3d"
 
 UPSTREAM_CHECK_GITTAGREGEX = "mesa-(?P<pver>\d+(\.\d+)+)"
 
diff --git a/meta/recipes-graphics/mesa/mesa_21.3.6.bb b/meta/recipes-graphics/mesa/mesa_21.3.7.bb
similarity index 100%
rename from meta/recipes-graphics/mesa/mesa_21.3.6.bb
rename to meta/recipes-graphics/mesa/mesa_21.3.7.bb