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Wed, 13 Apr 2022 19:52:34 -0700 (PDT) Received: from apollo.hsd1.ca.comcast.net ([2601:646:9200:a0f0::4307]) by smtp.gmail.com with ESMTPSA id 81-20020a621754000000b005082073f62dsm453735pfx.12.2022.04.13.19.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Apr 2022 19:52:33 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Cc: Khem Raj Subject: [PATCH 1/6] riscv: Add tunes for rv64 without compressed instructions Date: Wed, 13 Apr 2022 19:52:25 -0700 Message-Id: <20220414025230.1166825-1-raj.khem@gmail.com> X-Mailer: git-send-email 2.35.2 MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 14 Apr 2022 16:03:54 -0000 X-Groupsio-URL: https://lists.openembedded.org/g/openembedded-core/message/164378 Signed-off-by: Khem Raj --- meta/conf/machine/include/riscv/arch-riscv.inc | 2 ++ meta/conf/machine/include/riscv/tune-riscv.inc | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc index e5611a12a66..230a266563a 100644 --- a/meta/conf/machine/include/riscv/arch-riscv.inc +++ b/meta/conf/machine/include/riscv/arch-riscv.inc @@ -7,6 +7,8 @@ TUNE_PKGARCH = "${TUNE_PKGARCH:tune-${DEFAULTTUNE}}" TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nf', ' -mabi=lp64', ' ', d)}" TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32nf', ' -mabi=ilp32', ' ', d)}" +TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nc', ' -march=rv64imafd', ' ', d)}" + # Fix: ld: unrecognized option '--hash-style=sysv' LINKER_HASH_STYLE:libc-newlib = "" # Fix: ld: unrecognized option '--hash-style=gnu' diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index cc2896f277b..659801496c9 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -6,6 +6,8 @@ TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations" TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point" TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point" +TUNEVALID[riscv64nc] = "Enable 64-bit RISC-V optimizations without compressed instructions" + TUNEVALID[bigendian] = "Big endian mode" AVAILTUNES += "riscv64 riscv32 riscv64nf riscv32nf" @@ -31,3 +33,9 @@ TUNE_FEATURES:tune-riscv32nf = "${TUNE_FEATURES:tune-riscv32} riscv32nf" TUNE_ARCH:tune-riscv32nf = "riscv32" TUNE_PKGARCH:tune-riscv32nf = "riscv32nf" PACKAGE_EXTRA_ARCHS:tune-riscv32nf = "riscv32nf" + +# no compressed +TUNE_FEATURES:tune-riscv64nc = "${TUNE_FEATURES:tune-riscv64} riscv64nc" +TUNE_ARCH:tune-riscv64nc = "riscv64" +TUNE_PKGARCH:tune-riscv64nc = "riscv64nc" +PACKAGE_EXTRA_ARCHS:tune-riscv64nc = "riscv64nc"