From patchwork Fri Mar 25 13:48:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ross Burton X-Patchwork-Id: 5841 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E64DC43217 for ; Fri, 25 Mar 2022 13:48:59 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.5509.1648216138814782623 for ; Fri, 25 Mar 2022 06:48:59 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: ross.burton@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7914F12FC for ; Fri, 25 Mar 2022 06:48:58 -0700 (PDT) Received: from oss-tx204.lab.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EB5173F73B for ; Fri, 25 Mar 2022 06:48:57 -0700 (PDT) From: Ross Burton To: meta-arm@lists.yoctoproject.org Subject: [PATCH 5/7] arm-bsp/fvp-base-arm32: use correct DeviceTree Date: Fri, 25 Mar 2022 13:48:51 +0000 Message-Id: <20220325134853.3068169-5-ross.burton@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220325134853.3068169-1-ross.burton@arm.com> References: <20220325134853.3068169-1-ross.burton@arm.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 25 Mar 2022 13:48:59 -0000 X-Groupsio-URL: https://lists.yoctoproject.org/g/meta-arm/message/3209 The 64-bit fvp-base machine uses the upstream fvp-base-recv devicetree, but fvp-base-arm32 was accidentally using the old fvp-base-gicv3-psci-custom that we patch into the kernel. As the only difference between these platforms at a "hardware" level is whether the cores boot in 32- or 64-bit mode, they should both use fvp-base-revc. This isn't trivial as devicetree files need to be under the correct arch/ directory, so we need to symlink into arch/arm the right files from arch/arm64. This has several improvements, but primarily virtio networking works so we can now use testimage with fvp-base-arm32. Signed-off-by: Ross Burton --- meta-arm-bsp/conf/machine/fvp-base-arm32.conf | 4 - meta-arm-bsp/conf/machine/fvp-base.conf | 5 - meta-arm-bsp/conf/machine/fvp-common.inc | 4 + .../fvp-base-arm32/fvp-base-arm32-dts.patch | 580 ------------------ .../linux/linux-arm-platforms.inc | 10 +- 5 files changed, 12 insertions(+), 591 deletions(-) delete mode 100644 meta-arm-bsp/recipes-kernel/linux/files/fvp-base-arm32/fvp-base-arm32-dts.patch diff --git a/meta-arm-bsp/conf/machine/fvp-base-arm32.conf b/meta-arm-bsp/conf/machine/fvp-base-arm32.conf index b6fe6f77..2c0fa406 100644 --- a/meta-arm-bsp/conf/machine/fvp-base-arm32.conf +++ b/meta-arm-bsp/conf/machine/fvp-base-arm32.conf @@ -13,10 +13,6 @@ UBOOT_MACHINE = "vexpress_aemv8a_aarch32_defconfig" KERNEL_IMAGETYPE = "zImage" -KERNEL_DEVICETREE = "arm/fvp-base-gicv3-psci-custom.dtb" - -FVP_DATA ?= "cluster0.cpu0=${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}@0x80080000 \ - cluster0.cpu0=${DEPLOY_DIR_IMAGE}/fvp-base-gicv3-psci-custom.dtb@0x83000000" FVP_CONFIG[cluster0.cpu0.CONFIG64] = "0" FVP_CONFIG[cluster0.cpu1.CONFIG64] = "0" FVP_CONFIG[cluster0.cpu2.CONFIG64] = "0" diff --git a/meta-arm-bsp/conf/machine/fvp-base.conf b/meta-arm-bsp/conf/machine/fvp-base.conf index 00ef2116..d0152024 100644 --- a/meta-arm-bsp/conf/machine/fvp-base.conf +++ b/meta-arm-bsp/conf/machine/fvp-base.conf @@ -13,8 +13,3 @@ TUNE_FEATURES = "aarch64" UBOOT_MACHINE = "vexpress_aemv8a_semi_defconfig" KERNEL_IMAGETYPE = "Image" - -KERNEL_DEVICETREE = "arm/fvp-base-revc.dtb" - -FVP_DATA ?= "cluster0.cpu0=${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}@0x80080000 \ - cluster0.cpu0=${DEPLOY_DIR_IMAGE}/fvp-base-revc.dtb@0x83000000" diff --git a/meta-arm-bsp/conf/machine/fvp-common.inc b/meta-arm-bsp/conf/machine/fvp-common.inc index b0aeb81f..f8328cf4 100644 --- a/meta-arm-bsp/conf/machine/fvp-common.inc +++ b/meta-arm-bsp/conf/machine/fvp-common.inc @@ -14,6 +14,8 @@ SERIAL_CONSOLES = "115200;ttyAMA0" PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto" +KERNEL_DEVICETREE = "arm/fvp-base-revc.dtb" + EXTRA_IMAGEDEPENDS += "trusted-firmware-a u-boot" # As this is a virtual target that will not be used in the real world there is @@ -37,6 +39,8 @@ FVP_CONFIG[bp.virtioblockdevice.image_path] ?= "${DEPLOY_DIR_IMAGE}/${IMAGE_NAME FVP_CONFIG[cluster0.has_arm_v8-4] = "1" FVP_CONFIG[cluster1.has_arm_v8-4] = "1" FVP_CONSOLE ?= "terminal_0" +FVP_DATA ?= "cluster0.cpu0=${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}@0x80080000 \ + cluster0.cpu0=${DEPLOY_DIR_IMAGE}/fvp-base-revc.dtb@0x83000000" FVP_TERMINALS[bp.terminal_0] ?= "Console" FVP_TERMINALS[bp.terminal_1] ?= "" FVP_TERMINALS[bp.terminal_2] ?= "" diff --git a/meta-arm-bsp/recipes-kernel/linux/files/fvp-base-arm32/fvp-base-arm32-dts.patch b/meta-arm-bsp/recipes-kernel/linux/files/fvp-base-arm32/fvp-base-arm32-dts.patch deleted file mode 100644 index b21b4c0e..00000000 --- a/meta-arm-bsp/recipes-kernel/linux/files/fvp-base-arm32/fvp-base-arm32-dts.patch +++ /dev/null @@ -1,580 +0,0 @@ -These DTS files are the same as the ones provided for fvp-base. -They will be temporarily provided here until we can use the DTS files from TF-A. -So, no need to upstream. - -Upstream-Status: Inappropriate -Signed-off-by: Anders Dellien - -diff --git a/arch/arm/boot/dts/arm/fvp-base-gicv3-psci-common-custom.dtsi b/arch/arm/boot/dts/arm/fvp-base-gicv3-psci-common-custom.dtsi -new file mode 100644 -index 000000000000..f4601c7f99f8 ---- /dev/null -+++ b/arch/arm/boot/dts/arm/fvp-base-gicv3-psci-common-custom.dtsi -@@ -0,0 +1,264 @@ -+/* -+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. -+ * -+ * SPDX-License-Identifier: BSD-3-Clause -+ */ -+ -+/memreserve/ 0x80000000 0x00010000; -+ -+/include/ "rtsm_ve-motherboard-nomap.dtsi" -+ -+/ { -+ model = "FVP Base"; -+ compatible = "arm,vfp-base", "arm,vexpress"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ serial0 = &v2m_serial0; -+ serial1 = &v2m_serial1; -+ serial2 = &v2m_serial2; -+ serial3 = &v2m_serial3; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; -+ method = "smc"; -+ cpu_suspend = <0xc4000001>; -+ cpu_off = <0x84000002>; -+ cpu_on = <0xc4000003>; -+ sys_poweroff = <0x84000008>; -+ sys_reset = <0x84000009>; -+ }; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ cpu-map { -+ cluster0 { -+ core0 { -+ cpu = <&CPU0>; -+ }; -+ core1 { -+ cpu = <&CPU1>; -+ }; -+ core2 { -+ cpu = <&CPU2>; -+ }; -+ core3 { -+ cpu = <&CPU3>; -+ }; -+ }; -+ -+ cluster1 { -+ core0 { -+ cpu = <&CPU4>; -+ }; -+ core1 { -+ cpu = <&CPU5>; -+ }; -+ core2 { -+ cpu = <&CPU6>; -+ }; -+ core3 { -+ cpu = <&CPU7>; -+ }; -+ }; -+ }; -+ -+ idle-states { -+ entry-method = "arm,psci"; -+ -+ CPU_SLEEP_0: cpu-sleep-0 { -+ compatible = "arm,idle-state"; -+ local-timer-stop; -+ arm,psci-suspend-param = <0x0010000>; -+ entry-latency-us = <40>; -+ exit-latency-us = <100>; -+ min-residency-us = <150>; -+ }; -+ -+ CLUSTER_SLEEP_0: cluster-sleep-0 { -+ compatible = "arm,idle-state"; -+ local-timer-stop; -+ arm,psci-suspend-param = <0x1010000>; -+ entry-latency-us = <500>; -+ exit-latency-us = <1000>; -+ min-residency-us = <2500>; -+ }; -+ }; -+ -+ CPU0:cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ reg = <0x0 0x0>; -+ enable-method = "psci"; -+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ CPU1:cpu@100 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ reg = <0x0 0x100>; -+ enable-method = "psci"; -+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ CPU2:cpu@200 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ reg = <0x0 0x200>; -+ enable-method = "psci"; -+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ CPU3:cpu@300 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ reg = <0x0 0x300>; -+ enable-method = "psci"; -+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ CPU4:cpu@10000 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ reg = <0x0 0x10000>; -+ enable-method = "psci"; -+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ CPU5:cpu@10100 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ reg = <0x0 0x10100>; -+ enable-method = "psci"; -+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ CPU6:cpu@10200 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ reg = <0x0 0x10200>; -+ enable-method = "psci"; -+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ CPU7:cpu@10300 { -+ device_type = "cpu"; -+ compatible = "arm,armv8"; -+ reg = <0x0 0x10300>; -+ enable-method = "psci"; -+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; -+ next-level-cache = <&L2_0>; -+ }; -+ -+ L2_0: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0 0x7F000000>, -+ <0x00000008 0x80000000 0 0x80000000>; -+ }; -+ -+ gic: interrupt-controller@2f000000 { -+ compatible = "arm,gic-v3"; -+ #interrupt-cells = <3>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ interrupt-controller; -+ reg = <0x0 0x2f000000 0 0x10000>, // GICD -+ <0x0 0x2f100000 0 0x200000>, // GICR -+ <0x0 0x2c000000 0 0x2000>, // GICC -+ <0x0 0x2c010000 0 0x2000>, // GICH -+ <0x0 0x2c02f000 0 0x2000>; // GICV -+ interrupts = <1 9 4>; -+ -+ its: its@2f020000 { -+ compatible = "arm,gic-v3-its"; -+ msi-controller; -+ reg = <0x0 0x2f020000 0x0 0x20000>; // GITS -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = <1 13 0xff01>, -+ <1 14 0xff01>, -+ <1 11 0xff01>, -+ <1 10 0xff01>; -+ clock-frequency = <100000000>; -+ }; -+ -+ timer@2a810000 { -+ compatible = "arm,armv7-timer-mem"; -+ reg = <0x0 0x2a810000 0x0 0x10000>; -+ clock-frequency = <100000000>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ frame@2a830000 { -+ frame-number = <1>; -+ interrupts = <0 26 4>; -+ reg = <0x0 0x2a830000 0x0 0x10000>; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = <0 60 4>, -+ <0 61 4>, -+ <0 62 4>, -+ <0 63 4>; -+ }; -+ -+ smb@8000000 { -+ compatible = "simple-bus"; -+ -+ #address-cells = <2>; -+ #size-cells = <1>; -+ ranges = <0 0 0 0x08000000 0x04000000>, -+ <1 0 0 0x14000000 0x04000000>, -+ <2 0 0 0x18000000 0x04000000>, -+ <3 0 0 0x1c000000 0x04000000>, -+ <4 0 0 0x0c000000 0x04000000>, -+ <5 0 0 0x10000000 0x04000000>; -+ }; -+ -+ panels { -+ panel { -+ compatible = "panel"; -+ mode = "XVGA"; -+ refresh = <60>; -+ xres = <1024>; -+ yres = <768>; -+ pixclock = <15748>; -+ left_margin = <152>; -+ right_margin = <48>; -+ upper_margin = <23>; -+ lower_margin = <3>; -+ hsync_len = <104>; -+ vsync_len = <4>; -+ sync = <0>; -+ vmode = "FB_VMODE_NONINTERLACED"; -+ tim2 = "TIM2_BCD", "TIM2_IPC"; -+ cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; -+ caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; -+ bpp = <16>; -+ }; -+ }; -+ -+}; -diff --git a/arch/arm/boot/dts/arm/fvp-base-gicv3-psci-custom.dts b/arch/arm/boot/dts/arm/fvp-base-gicv3-psci-custom.dts -new file mode 100644 -index 000000000000..984dbca90126 ---- /dev/null -+++ b/arch/arm/boot/dts/arm/fvp-base-gicv3-psci-custom.dts -@@ -0,0 +1,9 @@ -+/* -+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. -+ * -+ * SPDX-License-Identifier: BSD-3-Clause -+ */ -+ -+/dts-v1/; -+ -+/include/ "fvp-base-gicv3-psci-common-custom.dtsi" -diff --git a/arch/arm/boot/dts/arm/rtsm_ve-motherboard-nomap.dtsi b/arch/arm/boot/dts/arm/rtsm_ve-motherboard-nomap.dtsi -new file mode 100644 -index 000000000000..a94f7cb863a2 ---- /dev/null -+++ b/arch/arm/boot/dts/arm/rtsm_ve-motherboard-nomap.dtsi -@@ -0,0 +1,282 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * ARM Ltd. Fast Models -+ * -+ * Versatile Express (VE) system model -+ * Motherboard component -+ * -+ * VEMotherBoard.lisa -+ * -+ * This is a duplicate of rtsm_ve-motherboard.dtsi but not -+ * using interrupt-map as this is not properly supported in -+ * xen right now -+ */ -+/ { -+ smb@8000000 { -+ motherboard { -+ arm,v2m-memory-map = "rs1"; -+ compatible = "arm,vexpress,v2m-p1", "simple-bus"; -+ #address-cells = <2>; /* SMB chipselect number and offset */ -+ #size-cells = <1>; -+ ranges; -+ -+ flash@0,00000000 { -+ compatible = "arm,vexpress-flash", "cfi-flash"; -+ reg = <0 0x00000000 0x04000000>, -+ <4 0x00000000 0x04000000>; -+ bank-width = <4>; -+ }; -+ -+ v2m_video_ram: vram@2,00000000 { -+ compatible = "arm,vexpress-vram"; -+ reg = <2 0x00000000 0x00800000>; -+ }; -+ -+ ethernet@2,02000000 { -+ compatible = "smsc,lan91c111"; -+ reg = <2 0x02000000 0x10000>; -+ interrupts = <0 15 4>; -+ }; -+ -+ v2m_clk24mhz: clk24mhz { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ clock-output-names = "v2m:clk24mhz"; -+ }; -+ -+ v2m_refclk1mhz: refclk1mhz { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <1000000>; -+ clock-output-names = "v2m:refclk1mhz"; -+ }; -+ -+ v2m_refclk32khz: refclk32khz { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "v2m:refclk32khz"; -+ }; -+ -+ iofpga@3,00000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 3 0 0x200000>; -+ -+ v2m_sysreg: sysreg@10000 { -+ compatible = "arm,vexpress-sysreg"; -+ reg = <0x010000 0x1000>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ v2m_sysctl: sysctl@20000 { -+ compatible = "arm,sp810", "arm,primecell"; -+ reg = <0x020000 0x1000>; -+ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; -+ clock-names = "refclk", "timclk", "apb_pclk"; -+ #clock-cells = <1>; -+ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; -+ assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; -+ assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; -+ }; -+ -+ aaci@40000 { -+ compatible = "arm,pl041", "arm,primecell"; -+ reg = <0x040000 0x1000>; -+ interrupts = <0 11 4>; -+ clocks = <&v2m_clk24mhz>; -+ clock-names = "apb_pclk"; -+ }; -+ -+ mmci@50000 { -+ compatible = "arm,pl180", "arm,primecell"; -+ reg = <0x050000 0x1000>; -+ interrupts = <0 9 4 0 10 4>; -+ cd-gpios = <&v2m_sysreg 0 0>; -+ wp-gpios = <&v2m_sysreg 1 0>; -+ max-frequency = <12000000>; -+ vmmc-supply = <&v2m_fixed_3v3>; -+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; -+ clock-names = "mclk", "apb_pclk"; -+ }; -+ -+ kmi@60000 { -+ compatible = "arm,pl050", "arm,primecell"; -+ reg = <0x060000 0x1000>; -+ interrupts = <0 12 4>; -+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; -+ clock-names = "KMIREFCLK", "apb_pclk"; -+ }; -+ -+ kmi@70000 { -+ compatible = "arm,pl050", "arm,primecell"; -+ reg = <0x070000 0x1000>; -+ interrupts = <0 13 4>; -+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; -+ clock-names = "KMIREFCLK", "apb_pclk"; -+ }; -+ -+ v2m_serial0: uart@90000 { -+ compatible = "arm,pl011", "arm,primecell"; -+ reg = <0x090000 0x1000>; -+ interrupts = <0 5 4>; -+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; -+ clock-names = "uartclk", "apb_pclk"; -+ }; -+ -+ v2m_serial1: uart@a0000 { -+ compatible = "arm,pl011", "arm,primecell"; -+ reg = <0x0a0000 0x1000>; -+ interrupts = <0 6 4>; -+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; -+ clock-names = "uartclk", "apb_pclk"; -+ }; -+ -+ v2m_serial2: uart@b0000 { -+ compatible = "arm,pl011", "arm,primecell"; -+ reg = <0x0b0000 0x1000>; -+ interrupts = <0 7 4>; -+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; -+ clock-names = "uartclk", "apb_pclk"; -+ }; -+ -+ v2m_serial3: uart@c0000 { -+ compatible = "arm,pl011", "arm,primecell"; -+ reg = <0x0c0000 0x1000>; -+ interrupts = <0 8 4>; -+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; -+ clock-names = "uartclk", "apb_pclk"; -+ }; -+ -+ wdt@f0000 { -+ compatible = "arm,sp805", "arm,primecell"; -+ reg = <0x0f0000 0x1000>; -+ interrupts = <0 0 4>; -+ clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; -+ clock-names = "wdogclk", "apb_pclk"; -+ }; -+ -+ v2m_timer01: timer@110000 { -+ compatible = "arm,sp804", "arm,primecell"; -+ reg = <0x110000 0x1000>; -+ interrupts = <0 2 4>; -+ clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; -+ clock-names = "timclken1", "timclken2", "apb_pclk"; -+ }; -+ -+ v2m_timer23: timer@120000 { -+ compatible = "arm,sp804", "arm,primecell"; -+ reg = <0x120000 0x1000>; -+ interrupts = <0 3 4>; -+ clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; -+ clock-names = "timclken1", "timclken2", "apb_pclk"; -+ }; -+ -+ rtc@170000 { -+ compatible = "arm,pl031", "arm,primecell"; -+ reg = <0x170000 0x1000>; -+ interrupts = <0 4 4>; -+ clocks = <&v2m_clk24mhz>; -+ clock-names = "apb_pclk"; -+ }; -+ -+ clcd@1f0000 { -+ compatible = "arm,pl111", "arm,primecell"; -+ reg = <0x1f0000 0x1000>; -+ interrupt-names = "combined"; -+ interrupts = <0 14 4>; -+ clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; -+ clock-names = "clcdclk", "apb_pclk"; -+ arm,pl11x,framebuffer = <0x18000000 0x00180000>; -+ memory-region = <&v2m_video_ram>; -+ max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ -+ -+ port { -+ v2m_clcd_pads: endpoint { -+ remote-endpoint = <&v2m_clcd_panel>; -+ arm,pl11x,tft-r0g0b0-pads = <0 8 16>; -+ }; -+ }; -+ -+ panel { -+ compatible = "panel-dpi"; -+ -+ port { -+ v2m_clcd_panel: endpoint { -+ remote-endpoint = <&v2m_clcd_pads>; -+ }; -+ }; -+ -+ panel-timing { -+ clock-frequency = <63500127>; -+ hactive = <1024>; -+ hback-porch = <152>; -+ hfront-porch = <48>; -+ hsync-len = <104>; -+ vactive = <768>; -+ vback-porch = <23>; -+ vfront-porch = <3>; -+ vsync-len = <4>; -+ }; -+ }; -+ }; -+ -+ virtio-block@130000 { -+ compatible = "virtio,mmio"; -+ reg = <0x130000 0x200>; -+ interrupts = <0 42 4>; -+ }; -+ }; -+ -+ v2m_fixed_3v3: v2m-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ mcc { -+ compatible = "arm,vexpress,config-bus"; -+ arm,vexpress,config-bridge = <&v2m_sysreg>; -+ -+ v2m_oscclk1: oscclk1 { -+ /* CLCD clock */ -+ compatible = "arm,vexpress-osc"; -+ arm,vexpress-sysreg,func = <1 1>; -+ freq-range = <23750000 63500000>; -+ #clock-cells = <0>; -+ clock-output-names = "v2m:oscclk1"; -+ }; -+ -+ reset { -+ compatible = "arm,vexpress-reset"; -+ arm,vexpress-sysreg,func = <5 0>; -+ }; -+ -+ muxfpga { -+ compatible = "arm,vexpress-muxfpga"; -+ arm,vexpress-sysreg,func = <7 0>; -+ }; -+ -+ shutdown { -+ compatible = "arm,vexpress-shutdown"; -+ arm,vexpress-sysreg,func = <8 0>; -+ }; -+ -+ reboot { -+ compatible = "arm,vexpress-reboot"; -+ arm,vexpress-sysreg,func = <9 0>; -+ }; -+ -+ dvimode { -+ compatible = "arm,vexpress-dvimode"; -+ arm,vexpress-sysreg,func = <11 0>; -+ }; -+ }; -+ }; -+ }; -+}; diff --git a/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc b/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc index a9f3b887..2d232bbc 100644 --- a/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc +++ b/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc @@ -67,8 +67,14 @@ FILESEXTRAPATHS:prepend:fvp-base := "${ARMBSPFILESPATHS}" COMPATIBLE_MACHINE:fvp-base-arm32 = "fvp-base-arm32" KMACHINE:fvp-base-arm32 = "fvp-arm32" FILESEXTRAPATHS:prepend:fvp-base-arm32 := "${ARMBSPFILESPATHS}" -SRC_URI:append:fvp-base-arm32 = " file://fvp-base-arm32-dts.patch \ - file://0001-ARM-vexpress-enable-GICv3.patch" +SRC_URI:append:fvp-base-arm32 = " file://0001-ARM-vexpress-enable-GICv3.patch" +# We want to use the DT in the arm64 tree but the kernel build doesn't like that, so symlink it +do_compile:prepend:fvp-base-arm32() { + mkdir --parents ${S}/arch/arm/boot/dts/arm + for file in fvp-base-revc.dts rtsm_ve-motherboard.dtsi rtsm_ve-motherboard-rs2.dtsi; do + ln -fsr ${S}/arch/arm64/boot/dts/arm/$file ${S}/arch/arm/boot/dts/arm + done +} # # FVP BaseR AEMv8r64 Machine