Patchwork [mpc5125-twr,2/2] Linux kernel for mpc5125-twr

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Submitter Jan Kobler
Date April 8, 2011, 7:33 p.m.
Message ID <1302291183-17622-2-git-send-email-eng1@koblersystems.de>
Download mbox | patch
Permalink /patch/2093/
State New, archived
Headers show

Comments

Jan Kobler - April 8, 2011, 7:33 p.m.
Freescale is shipping a Linux kernel 2.6.29-v2010041601 for the TWR-MPC5125-KIT in
http://www.freescale.com/files/soft_dev_tools/software/board_support_packages/TWRMPC5125LinuxBSP.rar

The patch mpc5125-twr.patch has been created by comparing
the Freescale Linux kernel with Linux kernel version 2.6.29.1

The defconfig file is the file linux-2.6.29-v2010041601/arch/powerpc/configs/mpc5125_twr_defconfig.

Signed-off-by: Jan Kobler <eng1@koblersystems.de>
---
 recipes/linux/linux-2.6.29/mpc5125-twr/defconfig   | 2274 +
 .../linux-2.6.29/mpc5125-twr/mpc5125-twr.patch     |48475 ++++++++++++++++++++
 2 files changed, 50749 insertions(+), 0 deletions(-)
 create mode 100644 recipes/linux/linux-2.6.29/mpc5125-twr/defconfig
 create mode 100644 recipes/linux/linux-2.6.29/mpc5125-twr/mpc5125-twr.patch

Patch

diff --git a/recipes/linux/linux-2.6.29/mpc5125-twr/defconfig b/recipes/linux/linux-2.6.29/mpc5125-twr/defconfig
new file mode 100644
index 0000000..9601c6a
--- /dev/null
+++ b/recipes/linux/linux-2.6.29/mpc5125-twr/defconfig
@@ -0,0 +1,2274 @@ 
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29.1
+# Thu Mar 18 13:38:38 2010
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_6xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+# CONFIG_ALTIVEC is not set
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+# CONFIG_SMP is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_TREE=y
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_USER_SCHED is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+CONFIG_MARKERS=y
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_CLK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_FREEZER=y
+
+#
+# Platform support
+#
+CONFIG_PPC_MULTIPLATFORM=y
+CONFIG_CLASSIC32=y
+CONFIG_PPC_CHRP=y
+CONFIG_PPC_MPC512x=y
+CONFIG_PPC_MPC5125=y
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_MPC5121_ADS is not set
+CONFIG_PPC_MERGE=y
+CONFIG_MPC5125_TWR=y
+# CONFIG_MPC5121_GENERIC is not set
+# CONFIG_MPC5121_ADS_HIB is not set
+CONFIG_MPC5121_PM_TEST=y
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_86xx is not set
+# CONFIG_EMBEDDED6xx is not set
+CONFIG_PPC_NATIVE=y
+# CONFIG_UDBG_RTAS_CONSOLE is not set
+CONFIG_IPIC=y
+CONFIG_MPIC=y
+# CONFIG_MPIC_WEIRD is not set
+CONFIG_PPC_I8259=y
+CONFIG_PPC_RTAS=y
+# CONFIG_RTAS_ERROR_LOGGING is not set
+# CONFIG_RTAS_PROC is not set
+# CONFIG_MMIO_NVRAM is not set
+CONFIG_PPC_MPC106=y
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_ULI1575 is not set
+# CONFIG_SIMPLE_GPIO is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_BINFMT_ELF=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_PPC_NEED_DMA_SYNC_OPS=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_KEXEC=y
+# CONFIG_CRASH_DUMP is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_MIGRATION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_UNEVICTABLE_LRU is not set
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_64K_PAGES is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+# CONFIG_ISA is not set
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_FSL_PCI=y
+CONFIG_PPC_PCI_CHOICE=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+CONFIG_ADVANCED_OPTIONS=y
+# CONFIG_LOWMEM_SIZE_BOOL is not set
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_AXEMBX_RESERVE_BOOL=y
+CONFIG_AXEMBX_RESERVE_START=0x00400000
+CONFIG_AXE_RESERVE_SIZE=0x00100000
+CONFIG_MBX_RESERVE_SIZE=0x0
+# CONFIG_PAGE_OFFSET_BOOL is not set
+CONFIG_PAGE_OFFSET=0xc0000000
+# CONFIG_KERNEL_START_BOOL is not set
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+# CONFIG_TASK_SIZE_BOOL is not set
+CONFIG_TASK_SIZE=0xc0000000
+# CONFIG_CONSISTENT_START_BOOL is not set
+CONFIG_CONSISTENT_START=0xff100000
+# CONFIG_CONSISTENT_SIZE_BOOL is not set
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_IPV6 is not set
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_RAW=m
+
+#
+# DECnet: Netfilter Configuration
+#
+CONFIG_DECNET_NF_GRABULATOR=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+
+#
+# DCCP CCIDs Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=y
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+CONFIG_TIPC=m
+CONFIG_TIPC_ADVANCED=y
+CONFIG_TIPC_ZONES=3
+CONFIG_TIPC_CLUSTERS=1
+CONFIG_TIPC_NODES=255
+CONFIG_TIPC_SLAVE_NODES=0
+CONFIG_TIPC_PORTS=8191
+CONFIG_TIPC_LOG=0
+# CONFIG_TIPC_DEBUG is not set
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+CONFIG_ATM_CLIP_NO_ICMP=y
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_DECNET=m
+CONFIG_DECNET_ROUTER=y
+CONFIG_LLC=m
+CONFIG_LLC2=m
+CONFIG_IPX=m
+CONFIG_IPX_INTERN=y
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_IPDDP_DECAP=y
+CONFIG_X25=m
+CONFIG_LAPB=m
+CONFIG_ECONET=m
+CONFIG_ECONET_AUNUDP=y
+CONFIG_ECONET_NATIVE=y
+CONFIG_WAN_ROUTER=m
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_CGROUP=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_NET_CLS_IND=y
+CONFIG_NET_SCH_FIFO=y
+CONFIG_DCB=y
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+# CONFIG_CAN_BCM is not set
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=y
+# CONFIG_CAN_DEBUG_DEVICES is not set
+CONFIG_CAN_MSCAN=y
+CONFIG_CAN_MPC52XX=y
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_FIB_RULES=y
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=m
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_MPC5125_NFC=y
+CONFIG_MTD_NAND_FSL=y
+CONFIG_MTD_NAND_MPC5125_HARDWARE_ECC_CORRECTION=y
+# CONFIG_NFC_DMA_ENABLE is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=m
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+CONFIG_BLK_DEV_FD=m
+CONFIG_BLK_CPQ_DA=m
+CONFIG_BLK_CPQ_CISS_DA=m
+CONFIG_CISS_SCSI_TAPE=y
+CONFIG_BLK_DEV_DAC960=m
+CONFIG_BLK_DEV_UMEM=m
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_SX8=m
+CONFIG_BLK_DEV_UB=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_TIFM_CORE=m
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+CONFIG_SCSI_NETLINK=y
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+# CONFIG_SCSI_SAS_HOST_SMP is not set
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+CONFIG_SCSI_SRP_ATTRS=m
+# CONFIG_SCSI_SRP_TGT_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+CONFIG_BLK_DEV_3W_XXXX_RAID=m
+CONFIG_SCSI_3W_9XXX=m
+CONFIG_SCSI_ACARD=m
+CONFIG_SCSI_AACRAID=m
+CONFIG_SCSI_AIC7XXX=m
+CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
+CONFIG_AIC7XXX_RESET_DELAY_MS=15000
+CONFIG_AIC7XXX_DEBUG_ENABLE=y
+CONFIG_AIC7XXX_DEBUG_MASK=0
+CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
+CONFIG_SCSI_AIC7XXX_OLD=m
+CONFIG_SCSI_AIC79XX=m
+CONFIG_AIC79XX_CMDS_PER_DEVICE=32
+CONFIG_AIC79XX_RESET_DELAY_MS=15000
+CONFIG_AIC79XX_DEBUG_ENABLE=y
+CONFIG_AIC79XX_DEBUG_MASK=0
+CONFIG_AIC79XX_REG_PRETTY_PRINT=y
+CONFIG_SCSI_AIC94XX=m
+# CONFIG_AIC94XX_DEBUG is not set
+CONFIG_SCSI_DPT_I2O=m
+CONFIG_SCSI_ADVANSYS=m
+CONFIG_SCSI_ARCMSR=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_MM=m
+CONFIG_MEGARAID_MAILBOX=m
+# CONFIG_MEGARAID_LEGACY is not set
+CONFIG_MEGARAID_SAS=m
+CONFIG_SCSI_HPTIOP=m
+CONFIG_SCSI_BUSLOGIC=m
+CONFIG_LIBFC=m
+CONFIG_FCOE=m
+CONFIG_SCSI_DMX3191D=m
+CONFIG_SCSI_EATA=m
+# CONFIG_SCSI_EATA_TAGGED_QUEUE is not set
+# CONFIG_SCSI_EATA_LINKED_COMMANDS is not set
+CONFIG_SCSI_EATA_MAX_TAGS=16
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+CONFIG_SCSI_IPS=m
+# CONFIG_SCSI_INITIO is not set
+CONFIG_SCSI_INIA100=m
+CONFIG_SCSI_MVSAS=m
+CONFIG_SCSI_STEX=m
+CONFIG_SCSI_SYM53C8XX_2=m
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+CONFIG_SCSI_SYM53C8XX_MMIO=y
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_QLA_FC=m
+CONFIG_SCSI_QLA_ISCSI=m
+CONFIG_SCSI_LPFC=m
+# CONFIG_SCSI_LPFC_DEBUG_FS is not set
+CONFIG_SCSI_DC395x=m
+CONFIG_SCSI_DC390T=m
+CONFIG_SCSI_NSP32=m
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_SCSI_SRP=m
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+CONFIG_FIREWIRE=m
+CONFIG_FIREWIRE_OHCI=m
+CONFIG_FIREWIRE_OHCI_DEBUG=y
+CONFIG_FIREWIRE_SBP2=m
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+CONFIG_IFB=m
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+CONFIG_TUN=m
+CONFIG_VETH=m
+CONFIG_ARCNET=m
+CONFIG_ARCNET_1201=m
+CONFIG_ARCNET_1051=m
+CONFIG_ARCNET_RAW=m
+CONFIG_ARCNET_CAP=m
+# CONFIG_ARCNET_COM90xx is not set
+CONFIG_ARCNET_COM90xxIO=m
+# CONFIG_ARCNET_RIM_I is not set
+CONFIG_ARCNET_COM20020=m
+CONFIG_ARCNET_COM20020_PCI=m
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_ATL2 is not set
+CONFIG_FS_ENET=y
+CONFIG_FS_ENET_MPC5121_FEC=y
+# CONFIG_FS_ENET_MPC5125_FEC2 is not set
+CONFIG_FS_ENET_HAS_FEC=y
+CONFIG_FS_ENET_MDIO_FEC=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_MLX4_CORE=m
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_HSO=m
+# CONFIG_WAN is not set
+# CONFIG_ATM_DRIVERS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+CONFIG_SLIP=m
+# CONFIG_SLIP_COMPRESSED is not set
+# CONFIG_SLIP_SMART is not set
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_POLLDEV=m
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=m
+CONFIG_SERIO_I8042=m
+CONFIG_SERIO_SERPORT=m
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_RAW=m
+# CONFIG_SERIO_XILINX_XPS_PS2 is not set
+CONFIG_GAMEPORT=m
+CONFIG_GAMEPORT_NS558=m
+CONFIG_GAMEPORT_L4=m
+CONFIG_GAMEPORT_EMU10K1=m
+CONFIG_GAMEPORT_FM801=m
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_NOZOMI=m
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_MPC52xx=y
+CONFIG_SERIAL_MPC52xx_CONSOLE=y
+CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD=115200
+CONFIG_SERIAL_JSM=m
+CONFIG_UNIX98_PTYS=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_BRIQ_PANEL is not set
+# CONFIG_HVC_RTAS is not set
+# CONFIG_HVC_UDBG is not set
+CONFIG_IPMI_HANDLER=m
+# CONFIG_IPMI_PANIC_EVENT is not set
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPMI_POWEROFF=m
+CONFIG_HW_RANDOM=m
+CONFIG_NVRAM=y
+# CONFIG_R3964 is not set
+CONFIG_APPLICOM=m
+# CONFIG_RAW_DRIVER is not set
+CONFIG_TCG_TPM=m
+CONFIG_TCG_NSC=m
+CONFIG_TCG_ATMEL=m
+CONFIG_DEVPORT=y
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_ALGOPCA=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+CONFIG_I2C_ISCH=m
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+CONFIG_I2C_SIS5595=m
+CONFIG_I2C_SIS630=m
+CONFIG_I2C_SIS96X=m
+CONFIG_I2C_VIA=m
+CONFIG_I2C_VIAPRO=m
+
+#
+# Mac SMBus host controller drivers
+#
+CONFIG_I2C_HYDRA=m
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_MPC=m
+CONFIG_I2C_OCORES=m
+CONFIG_I2C_SIMTEC=m
+
+#
+# External I2C/SMBus adapter drivers
+#
+CONFIG_I2C_PARPORT_LIGHT=m
+CONFIG_I2C_TAOS_EVM=m
+CONFIG_I2C_TINY_USB=m
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+CONFIG_I2C_VOODOO3=m
+
+#
+# Other I2C/SMBus bus drivers
+#
+CONFIG_I2C_PCA_PLATFORM=m
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_DS1682=m
+CONFIG_SENSORS_PCF8574=m
+CONFIG_PCF8575=m
+CONFIG_SENSORS_PCA9539=m
+CONFIG_SENSORS_PCF8591=m
+CONFIG_SENSORS_MAX6875=m
+CONFIG_SENSORS_TSL2550=m
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_DEBUG=y
+# CONFIG_PDA_POWER is not set
+# CONFIG_WM8350_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_CHARGER_PCF50633 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=m
+CONFIG_MFD_SM501=m
+CONFIG_HTC_PASIC3=m
+# CONFIG_MFD_TMIO is not set
+CONFIG_MFD_WM8400=m
+CONFIG_MFD_WM8350=m
+CONFIG_MFD_WM8350_I2C=m
+CONFIG_MFD_PCF50633=m
+CONFIG_PCF50633_ADC=m
+CONFIG_PCF50633_GPIO=m
+# CONFIG_REGULATOR is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_VIDEO_V4L2=m
+# CONFIG_VIDEO_CAPTURE_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DVB_DYNAMIC_MINORS is not set
+# CONFIG_DVB_CAPTURE_DRIVERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+CONFIG_AGP=m
+CONFIG_DRM=m
+CONFIG_DRM_TDFX=m
+CONFIG_DRM_R128=m
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_MGA=m
+# CONFIG_DRM_SIS is not set
+CONFIG_DRM_VIA=m
+CONFIG_DRM_SAVAGE=m
+CONFIG_VGASTATE=m
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_SVGALIB=m
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+CONFIG_FB_CIRRUS=m
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_OF is not set
+# CONFIG_FB_CT65550 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_UVESA is not set
+CONFIG_FB_S1D13XXX=m
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+CONFIG_FB_S3=m
+CONFIG_FB_SAVAGE=m
+# CONFIG_FB_SAVAGE_I2C is not set
+# CONFIG_FB_SAVAGE_ACCEL is not set
+# CONFIG_FB_SIS is not set
+CONFIG_FB_VIA=m
+CONFIG_FB_NEOMAGIC=m
+CONFIG_FB_KYRO=m
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+CONFIG_FB_VT8623=m
+CONFIG_FB_TRIDENT=m
+# CONFIG_FB_TRIDENT_ACCEL is not set
+CONFIG_FB_ARK=m
+CONFIG_FB_PM3=m
+# CONFIG_FB_CARMINE is not set
+CONFIG_FB_FSL_DIU=y
+CONFIG_FSL_DIU_FLIP_ON_VSYNC=y
+# CONFIG_FB_TMIO is not set
+CONFIG_FB_SM501=m
+CONFIG_FB_IBM_GXT4500=m
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FB_METRONOME=m
+CONFIG_FB_MB862XX=m
+# CONFIG_FB_MB862XX_PCI_GDC is not set
+# CONFIG_FB_MB862XX_LIME is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=m
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_DEBUG_VERBOSE=y
+CONFIG_SND_PCM_XRUN_DEBUG=y
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_AC97_POWER_SAVE is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_PPC is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+
+#
+# ALSA SoC audio for Freescale SOCs
+#
+CONFIG_SND_SOC_MPC5121=y
+CONFIG_SND_SOC_MPC5121_ADS=y
+# CONFIG_SND_SOC_MPC5121_I2S is not set
+CONFIG_SND_SOC_I2C_AND_SPI=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_AC97_CODEC=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_GREENASIA_FF=m
+CONFIG_HID_TOPSEED=y
+CONFIG_THRUSTMASTER_FF=m
+CONFIG_ZEROPLUS_FF=m
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+CONFIG_USB_WUSB=m
+CONFIG_USB_WUSB_CBAF=m
+# CONFIG_USB_WUSB_CBAF_DEBUG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_EHCI_HCD_PPC_OF=y
+# CONFIG_USB_OXU210HP_HCD is not set
+CONFIG_USB_ISP116X_HCD=m
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_HCD_PPC_OF is not set
+# CONFIG_USB_OHCI_HCD_SSB is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=m
+CONFIG_USB_U132_HCD=m
+CONFIG_USB_SL811_HCD=m
+CONFIG_USB_R8A66597_HCD=m
+CONFIG_USB_WHCI_HCD=m
+CONFIG_USB_HWA_HCD=m
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+CONFIG_USB_TMC=m
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+CONFIG_USB_MDC800=m
+CONFIG_USB_MICROTEK=m
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+# CONFIG_USB_SERIAL_CP2101 is not set
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+# CONFIG_USB_SERIAL_TI is not set
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_ADUTUX=m
+CONFIG_USB_SEVSEG=m
+CONFIG_USB_RIO500=m
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LCD=m
+CONFIG_USB_BERRY_CHARGE=m
+CONFIG_USB_LED=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+# CONFIG_USB_PHIDGET is not set
+CONFIG_USB_IDMOUSE=m
+CONFIG_USB_FTDI_ELAN=m
+CONFIG_USB_APPLEDISPLAY=m
+# CONFIG_USB_SISUSBVGA is not set
+CONFIG_USB_LD=m
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_IOWARRIOR=m
+CONFIG_USB_TEST=m
+CONFIG_USB_ISIGHTFW=m
+CONFIG_USB_VST=m
+CONFIG_USB_ATM=m
+CONFIG_USB_SPEEDTOUCH=m
+CONFIG_USB_CXACRU=m
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_XUSBATM=m
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_UWB=m
+CONFIG_UWB_HWA=m
+CONFIG_UWB_WHCI=m
+CONFIG_UWB_WLP=m
+CONFIG_UWB_I1480U=m
+CONFIG_UWB_I1480U_WLP=m
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=m
+CONFIG_MMC_SDHCI_PCI=m
+CONFIG_MMC_RICOH_MMC=m
+CONFIG_MMC_MPC5121=y
+# CONFIG_MMC_MPC5121_USE_DMA is not set
+# CONFIG_MMC_MPC5121_USE_CARD_INSERTION_INT is not set
+CONFIG_MMC_WBSD=m
+CONFIG_MMC_TIFM_SD=m
+CONFIG_MEMSTICK=m
+# CONFIG_MEMSTICK_DEBUG is not set
+
+#
+# MemoryStick drivers
+#
+# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
+CONFIG_MSPRO_BLOCK=m
+
+#
+# MemoryStick Host Controller Drivers
+#
+CONFIG_MEMSTICK_TIFM_MS=m
+CONFIG_MEMSTICK_JMICRON_38X=m
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_USER_MAD=m
+CONFIG_INFINIBAND_USER_ACCESS=m
+CONFIG_INFINIBAND_USER_MEM=y
+CONFIG_INFINIBAND_ADDR_TRANS=y
+CONFIG_INFINIBAND_MTHCA=m
+CONFIG_INFINIBAND_MTHCA_DEBUG=y
+CONFIG_INFINIBAND_AMSO1100=m
+# CONFIG_INFINIBAND_AMSO1100_DEBUG is not set
+CONFIG_MLX4_INFINIBAND=m
+CONFIG_INFINIBAND_NES=m
+# CONFIG_INFINIBAND_NES_DEBUG is not set
+CONFIG_INFINIBAND_IPOIB=m
+# CONFIG_INFINIBAND_IPOIB_CM is not set
+CONFIG_INFINIBAND_IPOIB_DEBUG=y
+# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
+CONFIG_INFINIBAND_SRP=m
+CONFIG_INFINIBAND_ISER=m
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS2068A is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_WM8350 is not set
+# CONFIG_RTC_DRV_PCF50633 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PPC is not set
+CONFIG_RTC_DRV_MPC5121=y
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_FSL_DMA=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_DMATEST is not set
+CONFIG_UIO=m
+CONFIG_UIO_CIF=m
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_SMX=m
+CONFIG_UIO_SERCOS3=m
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4DEV_COMPAT=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+CONFIG_YAFFS_DISABLE_TAGS_ECC=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_XPRT_RDMA=m
+CONFIG_SUNRPC_REGISTER_V4=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+CONFIG_AMIGA_PARTITION=y
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+CONFIG_KARMA_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8895-i"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_STACKTRACE=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+
+#
+# Tracers
+#
+# CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_PRINT_STACK_DEPTH=64
+# CONFIG_IRQSTACKS is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_FIPS=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_LZO=m
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+# CONFIG_CRYPTO_HW is not set
+CONFIG_PPC_CLOCK=y
+CONFIG_PPC_LIB_RHEAP=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/recipes/linux/linux-2.6.29/mpc5125-twr/mpc5125-twr.patch b/recipes/linux/linux-2.6.29/mpc5125-twr/mpc5125-twr.patch
new file mode 100644
index 0000000..f68f98d
--- /dev/null
+++ b/recipes/linux/linux-2.6.29/mpc5125-twr/mpc5125-twr.patch
@@ -0,0 +1,48475 @@ 
+diff -Naur linux-2.6.29/arch/powerpc/boot/dts/mpc5125-twr.dts linux-2.6.29-v2010041601/arch/powerpc/boot/dts/mpc5125-twr.dts
+--- linux-2.6.29/arch/powerpc/boot/dts/mpc5125-twr.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/boot/dts/mpc5125-twr.dts	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,426 @@
++/*
++ * STx/Freescale ADS5125 MPC5125 silicon
++ *
++ * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++/dts-v1/;
++
++/ {
++	model = "mpc5125ads";
++	compatible = "fsl,mpc5125ads";
++	#address-cells = <1>;
++	#size-cells = <1>;
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		PowerPC,5125@0 {
++			device_type = "cpu";
++			reg = <0>;
++			d-cache-line-size = <0x20>;	// 32 bytes
++			i-cache-line-size = <0x20>;	// 32 bytes
++			d-cache-size = <0x8000>;	// L1, 32K
++			i-cache-size = <0x8000>;	// L1, 32K
++			timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
++			bus-frequency = <198000000>;	// 198 MHz csb bus
++			clock-frequency = <396000000>;	// 396 MHz ppc core
++		};
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x00000000 0x10000000>;	// 256MB at 0
++	};
++
++	sram@30000000 {
++		compatible = "fsl,mpc5121-sram";
++		reg = <0x30000000 0x08000>;		// 32K at 0x30000000
++	};
++
++	nfc@40000000 {
++		compatible = "fsl,mpc5125-nfc";
++		reg = <0x40000000 0x100000>;	// 1M at 0x40000000
++		interrupts = <6 0x8>;
++		interrupt-parent = < &ipic >;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		bank-width = <1>;
++		write-size = <4096>;
++		spare-size = <218>;
++		chips = <1>;
++		nand-loader@0 {
++			label = "loader";
++			reg = <0x000000000 0x00100000>;
++		};
++		nand-uboot@100000 {
++			label = "uboot";
++			reg = <0x00100000 0x00100000>;
++		};
++		nand-envirement@200000 {
++			label = "envirment";
++			reg = <0x00200000 0x00100000>;
++			read-only;
++		};
++		nand-kernel@300000 {
++			label = "kernel";
++			reg = <0x00300000 0x00800000>;
++		};
++		devicetree@b00000 {
++			label = "device-tree";
++			reg = <0x00b00000 0x00100000>;
++		};
++		rootfs@c00000 {
++			label = "rootfs";
++			reg = <0x00c00000 0x800000>;
++		};
++		filesystem@1400000 {
++			label = "filesystem";
++			reg = <0x01400000 0x7ec00000>;
++		};
++		mqx@80000000 {
++			label = "mqx";
++			reg = <0x80000000 0x06400000>;
++		};
++		data@86400000 {
++			label = "data";
++			reg = <0x86400000 0x79C00000>;
++		};
++
++	};
++
++/*
++	localbus@80000020 {
++		compatible = "fsl,mpc5121ads-localbus";
++		#address-cells = <2>;
++		#size-cells = <1>;
++		reg = <0x80000020 0x40>;
++
++		ranges = <0x0 0x0 0xfe000000 0x02000000
++			  0x2 0x0 0x82000000 0x00008000>;
++
++		flash@0,0 {
++			compatible = "cfi-flash";
++			reg = <0 0x0 0x2000000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			bank-width = <2>;
++			device-width = <2>;
++			protected@0 {
++				label = "protected";
++				reg = <0x00000000 0x00040000>;  // first sector is protected
++				read-only;
++			};
++			filesystem@40000 {
++				label = "filesystem";
++				reg = <0x00040000 0x01a80000>;  // 26.25M for filesystem
++			};
++			kernel@1c40000 {
++				label = "kernel";
++				reg = <0x01ac0000 0x00400000>;  // 4M for kernel
++			};
++			device-tree@1ec0000 {
++				label = "device-tree";
++				reg = <0x01ec0000 0x00040000>;  // one sector for device tree
++			};
++			u-boot@1f00000 {
++				label = "u-boot";
++				reg = <0x01f00000 0x00100000>;  // 1M for u-boot
++				read-only;
++			};
++		};
++	};
++*/
++	soc@80000000 {
++		compatible = "fsl,mpc5121-immr";
++		device_type = "soc";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		#interrupt-cells = <2>;
++		ranges = <0x0 0x80000000 0x400000>;
++		reg = <0x80000000 0x400000>;
++		bus-frequency = <66000000>;	// 66 MHz ips bus
++
++
++		// IPIC
++		// interrupts cell = <intr #, sense>
++		// sense values match linux IORESOURCE_IRQ_* defines:
++		// sense == 8: Level, low assertion
++		// sense == 2: Edge, high-to-low change
++		//
++		ipic: interrupt-controller@c00 {
++			compatible = "fsl,mpc5121-ipic", "fsl,ipic";
++			interrupt-controller;
++			#address-cells = <0>;
++			#interrupt-cells = <2>;
++			reg = <0xc00 0x100>;
++		};
++
++		rtc@a00 {	// Real time clock
++			compatible = "fsl,mpc5121-rtc";
++			reg = <0xa00 0x100>;
++			interrupts = <79 0x8 80 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++		reset@e00 {	// Reset module
++			compatible = "fsl,mpc5121-reset";
++			reg = <0xe00 0x100>;
++		};
++
++		clock@f00 {	// Clock control
++			compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
++			reg = <0xf00 0x100>;
++		};
++
++		pmc@1000{  //Power Management Controller
++			compatible = "fsl,mpc5121-pmc";
++			reg = <0x1000 0x100>;
++			interrupts = <83 0x2>;
++			interrupt-parent = < &ipic >;
++		};
++
++		gpio@1100 {
++			compatible = "fsl,mpc5125-gpio";
++			cell-index = <0>;
++			reg = <0x1100 0x080>;
++			interrupts = <78 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++		gpio@1180 {
++			compatible = "fsl,mpc5125-gpio1";
++			cell-index = <1>;
++			reg = <0x1180 0x080>;
++			interrupts = <78 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++		mscan@1300 {
++			compatible = "fsl,mpc5121rev2-mscan";
++			cell-index = <0>;
++			interrupts = <12 0x8>;
++			interrupt-parent = < &ipic >;
++			reg = <0x1300 0x80>;
++		};
++
++		mscan@1380 {
++			compatible = "fsl,mpc5121rev2-mscan";
++			cell-index = <1>;
++			interrupts = <13 0x8>;
++			interrupt-parent = < &ipic >;
++			reg = <0x1380 0x80>;
++		};
++
++		sdhc@1500 {
++			compatible = "fsl,mpc5125-sdhc";
++			interrupts = <8 0x8>;
++			interrupt-parent = < &ipic >;
++			reg = <0x1500 0x100>;
++		};
++
++		i2c@1700 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "fsl-i2c";
++			cell-index = <0>;
++			reg = <0x1700 0x20>;
++			interrupts = <0x9 0x8>;
++			interrupt-parent = < &ipic >;
++			fsl5200-clocking;
++		};
++
++		i2c@1720 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "fsl-i2c";
++			cell-index = <1>;
++			reg = <0x1720 0x20>;
++			interrupts = <0xa 0x8>;
++			interrupt-parent = < &ipic >;
++			fsl5200-clocking;
++		};
++
++		i2c@1740 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "fsl-i2c";
++			cell-index = <2>;
++			reg = <0x1740 0x20>;
++			interrupts = <0xb 0x8>;
++			interrupt-parent = < &ipic >;
++			fsl5200-clocking;
++		};
++
++		i2ccontrol@1760 {
++			compatible = "fsl,mpc5121-i2c-ctrl";
++			reg = <0x1760 0x8>;
++		};
++
++		diu@2100 {
++			device_type = "display";
++			compatible = "fsl-diu";
++			reg = <0x2100 0x100>;
++			interrupts = <64 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++		// MPC5125e has two more CAN ports
++		// but they are not used on ADS5125
++		//mscan@2300 {
++		//	compatible = "fsl,mpc5121rev2-mscan";
++		//	cell-index = <2>;
++		//	interrupts = <90 0x8>;
++		//	interrupt-parent = < &ipic >;
++		//	reg = <0x2300 0x80>;
++		//};
++
++		//mscan@2380 {
++		//	compatible = "fsl,mpc5121rev2-mscan";
++		//	cell-index = <3>;
++		//	interrupts = <91 0x8>;
++		//	interrupt-parent = < &ipic >;
++		//	reg = <0x2380 0x80>;
++		//};
++
++		mdio@2800 {
++			device_type = "mdio";
++			compatible = "fsl,mpc5121-fec-mdio";
++			reg = <0x2800 0x800>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			phy0: ethernet-phy@0 {
++				reg = <1>;
++				device_type = "ethernet-phy";
++			};
++		};
++
++		ethernet@2800 {
++			device_type = "network";
++			compatible = "fsl,mpc5121-fec";
++			reg = <0x2800 0x800>;
++			local-mac-address = [ 00 00 00 00 00 00 ];
++			interrupts = <4 0x8>;
++			interrupt-parent = < &ipic >;
++			phy-handle = < &phy0 >;
++		};
++
++		// USB ULPI1
++		usb@3000 {
++			device_type = "usb";
++			compatible = "fsl-usb2-dr";
++			reg = <0x3000 0x400>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			interrupt-parent = < &ipic >;
++			interrupts = <43 0x8>;
++			dr_mode = "host";
++			phy_type = "ulpi";
++			big-endian-regs;
++		};
++
++		// USB ULPI2
++		//usb@4000 {
++		//	device_type = "usb";
++		//	compatible = "fsl-usb2-dr";
++		//	reg = <0x4000 0x400>;
++		//	#address-cells = <1>;
++		//	#size-cells = <0>;
++		//	interrupt-parent = < &ipic >;
++		//	interrupts = <44 0x8>;
++		//	dr_mode = "otg";
++		//	phy_type = "ulpi";
++		//	big-endian-regs;
++		//};
++
++		// Second FEC is not yet supported
++		//mdio@4800 {
++		//	device_type = "mdio";
++		//	compatible = "fsl,mpc5121-fec-mdio";
++		//	reg = <0x4800 0x800>;
++		//	#address-cells = <1>;
++		//	#size-cells = <0>;
++		//	phy1: ethernet-phy@0 {
++		//		reg = <1>;
++		//		device_type = "ethernet-phy";
++		//	};
++		//};
++
++		//ethernet@4800 {
++		//	device_type = "network";
++		//	compatible = "fsl,mpc5121-fec";
++		//	reg = <0x4800 0x800>;
++		//	local-mac-address = [ 00 00 00 00 00 00 ];
++		//	interrupts = <5 0x8>;
++		//	interrupt-parent = < &ipic >;
++		//	phy-handle = < &phy1 >;
++		//};
++
++		// IO control
++		ioctl@a000 {
++			compatible = "fsl,mpc5125-ioctl";
++			reg = <0xA000 0x1000>;
++		};
++		// PSC0 in ac97 mode
++		ac97@11000 {
++			device_type = "sound";
++			compatible = "fsl,mpc5125-psc-ac97", "fsl,mpc5125-psc";
++			cell-index = <0>;
++			reg = <0x11000 0x100>;
++			interrupts = <40 0x8>;
++			interrupt-parent = < &ipic >;
++			fsl,mode = "ac97-slave";
++			rx-fifo-size = <384>;
++			tx-fifo-size = <384>;
++		};
++		// 5125 PSCs are not 52xx or 5121 PSC compatible
++		// PSC1 uart0 aka ttyPSC0
++		serial@11100 {
++			device_type = "serial";
++			compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
++			port-number = <0>;
++			cell-index = <1>;
++			reg = <0x11100 0x100>;
++			interrupts = <40 0x8 71 0x8>;
++			interrupt-parent = < &ipic >;
++			rx-fifo-size = <16>;
++			tx-fifo-size = <16>;
++			nodcd;
++		};
++
++		// PSC9 uart1 aka ttyPSC1
++		serial@11900 {
++			device_type = "serial";
++			compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
++			port-number = <1>;
++			cell-index = <9>;
++			reg = <0x11900 0x100>;
++			interrupts = <40 0x8 32 0x8>;
++			interrupt-parent = < &ipic >;
++			rx-fifo-size = <16>;
++			tx-fifo-size = <16>;
++			nodcd;
++		};
++
++		pscfifo@11f00 {
++			compatible = "fsl,mpc5121-psc-fifo";
++			reg = <0x11f00 0x100>;
++			interrupts = <40 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++		dma2@14000 {
++			compatible = "mpc512x-dma2";
++			reg = <0x14000 0x1800>;
++			interrupts = <65 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++	};
++};
+diff -Naur linux-2.6.29/arch/powerpc/boot/dts/mpc5125-twr-fec2.dts linux-2.6.29-v2010041601/arch/powerpc/boot/dts/mpc5125-twr-fec2.dts
+--- linux-2.6.29/arch/powerpc/boot/dts/mpc5125-twr-fec2.dts	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/boot/dts/mpc5125-twr-fec2.dts	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,423 @@
++/*
++ * STx/Freescale ADS5125 MPC5125 silicon
++ *
++ * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++/dts-v1/;
++
++/ {
++	model = "mpc5125ads";
++	compatible = "fsl,mpc5125ads";
++	#address-cells = <1>;
++	#size-cells = <1>;
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		PowerPC,5125@0 {
++			device_type = "cpu";
++			reg = <0>;
++			d-cache-line-size = <0x20>;	// 32 bytes
++			i-cache-line-size = <0x20>;	// 32 bytes
++			d-cache-size = <0x8000>;	// L1, 32K
++			i-cache-size = <0x8000>;	// L1, 32K
++			timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
++			bus-frequency = <198000000>;	// 198 MHz csb bus
++			clock-frequency = <396000000>;	// 396 MHz ppc core
++		};
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x00000000 0x10000000>;	// 256MB at 0
++	};
++
++	sram@30000000 {
++		compatible = "fsl,mpc5121-sram";
++		reg = <0x30000000 0x08000>;		// 32K at 0x30000000
++	};
++
++	nfc@40000000 {
++		compatible = "fsl,mpc5125-nfc";
++		reg = <0x40000000 0x100000>;	// 1M at 0x40000000
++		interrupts = <6 0x8>;
++		interrupt-parent = < &ipic >;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		bank-width = <1>;
++		write-size = <4096>;
++		spare-size = <218>;
++		chips = <1>;
++		nand-loader@0 {
++			label = "loader";
++			reg = <0x000000000 0x00100000>;
++		};
++		nand-uboot@100000 {
++			label = "uboot";
++			reg = <0x00100000 0x00100000>;
++		};
++		nand-envirement@200000 {
++			label = "envirment";
++			reg = <0x00200000 0x00100000>;
++			read-only;
++		};
++		nand-kernel@300000 {
++			label = "kernel";
++			reg = <0x00300000 0x00800000>;
++		};
++		devicetree@b00000 {
++			label = "device-tree";
++			reg = <0x00b00000 0x00100000>;
++		};
++		rootfs@c00000 {
++			label = "rootfs";
++			reg = <0x00c00000 0x00800000>;
++		};
++		filesystem@1000000 {
++			label = "filesystem";
++			reg = <0x01400000 0x7ec00000>;
++		};
++/*
++		data@80000000 {
++			label = "data";
++			reg = <0x80000000 0x7f000000>;
++		};
++*/
++	};
++
++/*
++	localbus@80000020 {
++		compatible = "fsl,mpc5121ads-localbus";
++		#address-cells = <2>;
++		#size-cells = <1>;
++		reg = <0x80000020 0x40>;
++
++		ranges = <0x0 0x0 0xfe000000 0x02000000
++			  0x2 0x0 0x82000000 0x00008000>;
++
++		flash@0,0 {
++			compatible = "cfi-flash";
++			reg = <0 0x0 0x2000000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			bank-width = <2>;
++			device-width = <2>;
++			protected@0 {
++				label = "protected";
++				reg = <0x00000000 0x00040000>;  // first sector is protected
++				read-only;
++			};
++			filesystem@40000 {
++				label = "filesystem";
++				reg = <0x00040000 0x01a80000>;  // 26.25M for filesystem
++			};
++			kernel@1c40000 {
++				label = "kernel";
++				reg = <0x01ac0000 0x00400000>;  // 4M for kernel
++			};
++			device-tree@1ec0000 {
++				label = "device-tree";
++				reg = <0x01ec0000 0x00040000>;  // one sector for device tree
++			};
++			u-boot@1f00000 {
++				label = "u-boot";
++				reg = <0x01f00000 0x00100000>;  // 1M for u-boot
++				read-only;
++			};
++		};
++	};
++*/
++	soc@80000000 {
++		compatible = "fsl,mpc5121-immr";
++		device_type = "soc";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		#interrupt-cells = <2>;
++		ranges = <0x0 0x80000000 0x400000>;
++		reg = <0x80000000 0x400000>;
++		bus-frequency = <66000000>;	// 66 MHz ips bus
++
++
++		// IPIC
++		// interrupts cell = <intr #, sense>
++		// sense values match linux IORESOURCE_IRQ_* defines:
++		// sense == 8: Level, low assertion
++		// sense == 2: Edge, high-to-low change
++		//
++		ipic: interrupt-controller@c00 {
++			compatible = "fsl,mpc5121-ipic", "fsl,ipic";
++			interrupt-controller;
++			#address-cells = <0>;
++			#interrupt-cells = <2>;
++			reg = <0xc00 0x100>;
++		};
++
++		rtc@a00 {	// Real time clock
++			compatible = "fsl,mpc5121-rtc";
++			reg = <0xa00 0x100>;
++			interrupts = <79 0x8 80 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++		reset@e00 {	// Reset module
++			compatible = "fsl,mpc5121-reset";
++			reg = <0xe00 0x100>;
++		};
++
++		clock@f00 {	// Clock control
++			compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
++			reg = <0xf00 0x100>;
++		};
++
++		pmc@1000{  //Power Management Controller
++			compatible = "fsl,mpc5121-pmc";
++			reg = <0x1000 0x100>;
++			interrupts = <83 0x2>;
++			interrupt-parent = < &ipic >;
++		};
++
++		gpio@1100 {
++			compatible = "fsl,mpc5125-gpio";
++			cell-index = <0>;
++			reg = <0x1100 0x080>;
++			interrupts = <78 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++		gpio@1180 {
++			compatible = "fsl,mpc5125-gpio1";
++			cell-index = <1>;
++			reg = <0x1180 0x080>;
++			interrupts = <78 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++		mscan@1300 {
++			compatible = "fsl,mpc5121rev2-mscan";
++			cell-index = <0>;
++			interrupts = <12 0x8>;
++			interrupt-parent = < &ipic >;
++			reg = <0x1300 0x80>;
++		};
++
++		mscan@1380 {
++			compatible = "fsl,mpc5121rev2-mscan";
++			cell-index = <1>;
++			interrupts = <13 0x8>;
++			interrupt-parent = < &ipic >;
++			reg = <0x1380 0x80>;
++		};
++
++		sdhc@1500 {
++			compatible = "fsl,mpc5125-sdhc";
++			interrupts = <8 0x8>;
++			interrupt-parent = < &ipic >;
++			reg = <0x1500 0x100>;
++		};
++
++		i2c@1700 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "fsl-i2c";
++			cell-index = <0>;
++			reg = <0x1700 0x20>;
++			interrupts = <0x9 0x8>;
++			interrupt-parent = < &ipic >;
++			fsl5200-clocking;
++		};
++
++		i2c@1720 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "fsl-i2c";
++			cell-index = <1>;
++			reg = <0x1720 0x20>;
++			interrupts = <0xa 0x8>;
++			interrupt-parent = < &ipic >;
++			fsl5200-clocking;
++		};
++
++		i2c@1740 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			compatible = "fsl-i2c";
++			cell-index = <2>;
++			reg = <0x1740 0x20>;
++			interrupts = <0xb 0x8>;
++			interrupt-parent = < &ipic >;
++			fsl5200-clocking;
++		};
++
++		i2ccontrol@1760 {
++			compatible = "fsl,mpc5121-i2c-ctrl";
++			reg = <0x1760 0x8>;
++		};
++
++		diu@2100 {
++			device_type = "display";
++			compatible = "fsl-diu";
++			reg = <0x2100 0x100>;
++			interrupts = <64 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++		// MPC5125e has two more CAN ports
++		// but they are not used on ADS5125
++		//mscan@2300 {
++		//	compatible = "fsl,mpc5121rev2-mscan";
++		//	cell-index = <2>;
++		//	interrupts = <90 0x8>;
++		//	interrupt-parent = < &ipic >;
++		//	reg = <0x2300 0x80>;
++		//};
++
++		//mscan@2380 {
++		//	compatible = "fsl,mpc5121rev2-mscan";
++		//	cell-index = <3>;
++		//	interrupts = <91 0x8>;
++		//	interrupt-parent = < &ipic >;
++		//	reg = <0x2380 0x80>;
++		//};
++
++		mdio@2800 {
++			device_type = "mdio";
++			compatible = "fsl,mpc5121-fec-mdio";
++			reg = <0x2800 0x800>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			phy0: ethernet-phy@0 {
++				reg = <1>;
++				device_type = "ethernet-phy";
++			};
++		};
++
++		ethernet@2800 {
++			device_type = "network";
++			compatible = "fsl,mpc5121-fec";
++			reg = <0x2800 0x800>;
++			local-mac-address = [ 00 00 00 00 00 00 ];
++			interrupts = <4 0x8>;
++			interrupt-parent = < &ipic >;
++			phy-handle = < &phy0 >;
++		};
++
++		// USB ULPI1
++		usb@3000 {
++			device_type = "usb";
++			compatible = "fsl-usb2-dr";
++			reg = <0x3000 0x400>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			interrupt-parent = < &ipic >;
++			interrupts = <43 0x8>;
++			dr_mode = "host";
++			phy_type = "ulpi";
++			big-endian-regs;
++		};
++
++		// USB ULPI2
++		//usb@4000 {
++		//	device_type = "usb";
++		//	compatible = "fsl-usb2-dr";
++		//	reg = <0x4000 0x400>;
++		//	#address-cells = <1>;
++		//	#size-cells = <0>;
++		//	interrupt-parent = < &ipic >;
++		//	interrupts = <44 0x8>;
++		//	dr_mode = "otg";
++		//	phy_type = "ulpi";
++		//	big-endian-regs;
++		//};
++
++		// Second FEC is not yet supported
++		mdio@4800 {
++			device_type = "mdio";
++			compatible = "fsl,mpc5121-fec-mdio";
++			reg = <0x4800 0x800>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			phy1: ethernet-phy@0 {
++				reg = <1>;
++				device_type = "ethernet-phy";
++			};
++		};
++
++		ethernet@4800 {
++			device_type = "network";
++			compatible = "fsl,mpc5121-fec";
++			reg = <0x4800 0x800>;
++			local-mac-address = [ 00 00 00 00 00 00 ];
++			interrupts = <5 0x8>;
++			interrupt-parent = < &ipic >;
++			phy-handle = < &phy1 >;
++		};
++
++		// IO control
++		ioctl@a000 {
++			compatible = "fsl,mpc5125-ioctl";
++			reg = <0xA000 0x1000>;
++		};
++		// PSC0 in ac97 mode
++		ac97@11000 {
++			device_type = "sound";
++			compatible = "fsl,mpc5125-psc-ac97", "fsl,mpc5125-psc";
++			cell-index = <0>;
++			reg = <0x11000 0x100>;
++			interrupts = <40 0x8>;
++			interrupt-parent = < &ipic >;
++			fsl,mode = "ac97-slave";
++			rx-fifo-size = <384>;
++			tx-fifo-size = <384>;
++		};
++		// 5125 PSCs are not 52xx or 5121 PSC compatible
++		// PSC1 uart0 aka ttyPSC0
++		serial@11100 {
++			device_type = "serial";
++			compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
++			port-number = <0>;
++			cell-index = <1>;
++			reg = <0x11100 0x100>;
++			interrupts = <40 0x8 71 0x8>;
++			interrupt-parent = < &ipic >;
++			rx-fifo-size = <16>;
++			tx-fifo-size = <16>;
++			nodcd;
++		};
++
++		// PSC9 uart1 aka ttyPSC1
++		serial@11900 {
++			device_type = "serial";
++			compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
++			port-number = <1>;
++			cell-index = <9>;
++			reg = <0x11900 0x100>;
++			interrupts = <40 0x8 32 0x8>;
++			interrupt-parent = < &ipic >;
++			rx-fifo-size = <16>;
++			tx-fifo-size = <16>;
++			nodcd;
++		};
++
++		pscfifo@11f00 {
++			compatible = "fsl,mpc5121-psc-fifo";
++			reg = <0x11f00 0x100>;
++			interrupts = <40 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++		dma2@14000 {
++			compatible = "mpc512x-dma2";
++			reg = <0x14000 0x1800>;
++			interrupts = <65 0x8>;
++			interrupt-parent = < &ipic >;
++		};
++
++	};
++};
+diff -Naur linux-2.6.29/arch/powerpc/configs/mpc5125_twr_defconfig linux-2.6.29-v2010041601/arch/powerpc/configs/mpc5125_twr_defconfig
+--- linux-2.6.29/arch/powerpc/configs/mpc5125_twr_defconfig	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/configs/mpc5125_twr_defconfig	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,2274 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.29.1
++# Thu Mar 18 13:38:38 2010
++#
++# CONFIG_PPC64 is not set
++
++#
++# Processor support
++#
++CONFIG_6xx=y
++# CONFIG_PPC_85xx is not set
++# CONFIG_PPC_8xx is not set
++# CONFIG_40x is not set
++# CONFIG_44x is not set
++# CONFIG_E200 is not set
++CONFIG_PPC_FPU=y
++# CONFIG_ALTIVEC is not set
++CONFIG_PPC_STD_MMU=y
++CONFIG_PPC_STD_MMU_32=y
++# CONFIG_PPC_MM_SLICES is not set
++# CONFIG_SMP is not set
++CONFIG_NOT_COHERENT_CACHE=y
++CONFIG_PPC32=y
++CONFIG_WORD_SIZE=32
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_MMU=y
++CONFIG_GENERIC_CMOS_UPDATE=y
++CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_GENERIC_HARDIRQS=y
++# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
++CONFIG_IRQ_PER_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_HAVE_LATENCYTOP_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_RWSEM_XCHGADD_ALGORITHM=y
++CONFIG_ARCH_HAS_ILOG2_U32=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_GENERIC_FIND_NEXT_BIT=y
++# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
++CONFIG_PPC=y
++CONFIG_EARLY_PRINTK=y
++CONFIG_GENERIC_NVRAM=y
++CONFIG_SCHED_OMIT_FRAME_POINTER=y
++CONFIG_ARCH_MAY_HAVE_PC_FDC=y
++CONFIG_PPC_OF=y
++CONFIG_OF=y
++CONFIG_PPC_UDBG_16550=y
++# CONFIG_GENERIC_TBSYNC is not set
++CONFIG_AUDIT_ARCH=y
++CONFIG_GENERIC_BUG=y
++CONFIG_DEFAULT_UIMAGE=y
++# CONFIG_PPC_DCR_NATIVE is not set
++# CONFIG_PPC_DCR_MMIO is not set
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_LOCK_KERNEL=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_AUDIT=y
++CONFIG_AUDITSYSCALL=y
++CONFIG_AUDIT_TREE=y
++
++#
++# RCU Subsystem
++#
++CONFIG_CLASSIC_RCU=y
++# CONFIG_TREE_RCU is not set
++# CONFIG_PREEMPT_RCU is not set
++# CONFIG_TREE_RCU_TRACE is not set
++# CONFIG_PREEMPT_RCU_TRACE is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_LOG_BUF_SHIFT=17
++CONFIG_GROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_RT_GROUP_SCHED is not set
++# CONFIG_USER_SCHED is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_CGROUPS=y
++# CONFIG_CGROUP_DEBUG is not set
++CONFIG_CGROUP_NS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++# CONFIG_RESOURCE_COUNTERS is not set
++# CONFIG_SYSFS_DEPRECATED_V2 is not set
++CONFIG_RELAY=y
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++CONFIG_USER_NS=y
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
++CONFIG_ANON_INODES=y
++# CONFIG_EMBEDDED is not set
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_PCSPKR_PLATFORM=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_PCI_QUIRKS=y
++# CONFIG_COMPAT_BRK is not set
++CONFIG_SLAB=y
++# CONFIG_SLUB is not set
++# CONFIG_SLOB is not set
++CONFIG_PROFILING=y
++CONFIG_TRACEPOINTS=y
++CONFIG_MARKERS=y
++CONFIG_OPROFILE=m
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_HAVE_IOREMAP_PROT=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_CLK=y
++# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
++CONFIG_SLABINFO=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_BLOCK=y
++CONFIG_LBD=y
++CONFIG_BLK_DEV_IO_TRACE=y
++CONFIG_BLK_DEV_BSG=y
++CONFIG_BLK_DEV_INTEGRITY=y
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++CONFIG_FREEZER=y
++
++#
++# Platform support
++#
++CONFIG_PPC_MULTIPLATFORM=y
++CONFIG_CLASSIC32=y
++CONFIG_PPC_CHRP=y
++CONFIG_PPC_MPC512x=y
++CONFIG_PPC_MPC5125=y
++# CONFIG_PPC_MPC5121 is not set
++# CONFIG_MPC5121_ADS is not set
++CONFIG_PPC_MERGE=y
++CONFIG_MPC5125_TWR=y
++# CONFIG_MPC5121_GENERIC is not set
++# CONFIG_MPC5121_ADS_HIB is not set
++CONFIG_MPC5121_PM_TEST=y
++# CONFIG_PPC_MPC52xx is not set
++# CONFIG_PPC_PMAC is not set
++# CONFIG_PPC_CELL is not set
++# CONFIG_PPC_CELL_NATIVE is not set
++# CONFIG_PPC_82xx is not set
++# CONFIG_PQ2ADS is not set
++# CONFIG_PPC_83xx is not set
++# CONFIG_PPC_86xx is not set
++# CONFIG_EMBEDDED6xx is not set
++CONFIG_PPC_NATIVE=y
++# CONFIG_UDBG_RTAS_CONSOLE is not set
++CONFIG_IPIC=y
++CONFIG_MPIC=y
++# CONFIG_MPIC_WEIRD is not set
++CONFIG_PPC_I8259=y
++CONFIG_PPC_RTAS=y
++# CONFIG_RTAS_ERROR_LOGGING is not set
++# CONFIG_RTAS_PROC is not set
++# CONFIG_MMIO_NVRAM is not set
++CONFIG_PPC_MPC106=y
++# CONFIG_PPC_970_NAP is not set
++# CONFIG_PPC_INDIRECT_IO is not set
++# CONFIG_GENERIC_IOMAP is not set
++# CONFIG_CPU_FREQ is not set
++# CONFIG_TAU is not set
++# CONFIG_QUICC_ENGINE is not set
++# CONFIG_FSL_ULI1575 is not set
++# CONFIG_SIMPLE_GPIO is not set
++
++#
++# Kernel options
++#
++# CONFIG_HIGHMEM is not set
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_TICK_ONESHOT=y
++# CONFIG_NO_HZ is not set
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++# CONFIG_HZ_100 is not set
++CONFIG_HZ_250=y
++# CONFIG_HZ_300 is not set
++# CONFIG_HZ_1000 is not set
++CONFIG_HZ=250
++CONFIG_SCHED_HRTICK=y
++# CONFIG_PREEMPT_NONE is not set
++# CONFIG_PREEMPT_VOLUNTARY is not set
++CONFIG_PREEMPT=y
++CONFIG_BINFMT_ELF=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++# CONFIG_HAVE_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++# CONFIG_IOMMU_HELPER is not set
++CONFIG_PPC_NEED_DMA_SYNC_OPS=y
++CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
++CONFIG_ARCH_HAS_WALK_MEMORY=y
++CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
++CONFIG_KEXEC=y
++# CONFIG_CRASH_DUMP is not set
++CONFIG_ARCH_FLATMEM_ENABLE=y
++CONFIG_ARCH_POPULATES_NODE_MAP=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_MIGRATION is not set
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=1
++CONFIG_BOUNCE=y
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_UNEVICTABLE_LRU is not set
++CONFIG_PPC_4K_PAGES=y
++# CONFIG_PPC_16K_PAGES is not set
++# CONFIG_PPC_64K_PAGES is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_PROC_DEVICETREE=y
++# CONFIG_CMDLINE_BOOL is not set
++CONFIG_EXTRA_TARGETS=""
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++# CONFIG_HIBERNATION is not set
++CONFIG_SECCOMP=y
++CONFIG_ISA_DMA_API=y
++
++#
++# Bus options
++#
++# CONFIG_ISA is not set
++CONFIG_ZONE_DMA=y
++CONFIG_GENERIC_ISA_DMA=y
++CONFIG_PPC_INDIRECT_PCI=y
++CONFIG_FSL_SOC=y
++CONFIG_FSL_PCI=y
++CONFIG_PPC_PCI_CHOICE=y
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_SYSCALL=y
++# CONFIG_PCIEPORTBUS is not set
++CONFIG_ARCH_SUPPORTS_MSI=y
++# CONFIG_PCI_MSI is not set
++CONFIG_PCI_LEGACY=y
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCCARD is not set
++# CONFIG_HOTPLUG_PCI is not set
++# CONFIG_HAS_RAPIDIO is not set
++
++#
++# Advanced setup
++#
++CONFIG_ADVANCED_OPTIONS=y
++# CONFIG_LOWMEM_SIZE_BOOL is not set
++CONFIG_LOWMEM_SIZE=0x30000000
++CONFIG_AXEMBX_RESERVE_BOOL=y
++CONFIG_AXEMBX_RESERVE_START=0x00400000
++CONFIG_AXE_RESERVE_SIZE=0x00100000
++CONFIG_MBX_RESERVE_SIZE=0x0
++# CONFIG_PAGE_OFFSET_BOOL is not set
++CONFIG_PAGE_OFFSET=0xc0000000
++# CONFIG_KERNEL_START_BOOL is not set
++CONFIG_KERNEL_START=0xc0000000
++CONFIG_PHYSICAL_START=0x00000000
++# CONFIG_TASK_SIZE_BOOL is not set
++CONFIG_TASK_SIZE=0xc0000000
++# CONFIG_CONSISTENT_START_BOOL is not set
++CONFIG_CONSISTENT_START=0xff100000
++# CONFIG_CONSISTENT_SIZE_BOOL is not set
++CONFIG_CONSISTENT_SIZE=0x00200000
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_COMPAT_NET_DEV_OPS=y
++CONFIG_PACKET=y
++# CONFIG_PACKET_MMAP is not set
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++CONFIG_XFRM_USER=m
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++CONFIG_XFRM_IPCOMP=m
++CONFIG_NET_KEY=m
++# CONFIG_NET_KEY_MIGRATE is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_IP_MROUTE is not set
++# CONFIG_ARPD is not set
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_LRO=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++CONFIG_TCP_CONG_ADVANCED=y
++CONFIG_TCP_CONG_BIC=m
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_TCP_CONG_WESTWOOD=m
++CONFIG_TCP_CONG_HTCP=m
++CONFIG_TCP_CONG_HSTCP=m
++CONFIG_TCP_CONG_HYBLA=m
++CONFIG_TCP_CONG_VEGAS=m
++CONFIG_TCP_CONG_SCALABLE=m
++CONFIG_TCP_CONG_LP=m
++CONFIG_TCP_CONG_VENO=m
++CONFIG_TCP_CONG_YEAH=m
++CONFIG_TCP_CONG_ILLINOIS=m
++# CONFIG_DEFAULT_BIC is not set
++CONFIG_DEFAULT_CUBIC=y
++# CONFIG_DEFAULT_HTCP is not set
++# CONFIG_DEFAULT_VEGAS is not set
++# CONFIG_DEFAULT_WESTWOOD is not set
++# CONFIG_DEFAULT_RENO is not set
++CONFIG_DEFAULT_TCP_CONG="cubic"
++CONFIG_TCP_MD5SIG=y
++CONFIG_IPV6=m
++CONFIG_IPV6_PRIVACY=y
++CONFIG_IPV6_ROUTER_PREF=y
++CONFIG_IPV6_ROUTE_INFO=y
++CONFIG_IPV6_OPTIMISTIC_DAD=y
++CONFIG_INET6_AH=m
++CONFIG_INET6_ESP=m
++CONFIG_INET6_IPCOMP=m
++CONFIG_IPV6_MIP6=m
++CONFIG_INET6_XFRM_TUNNEL=m
++CONFIG_INET6_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
++CONFIG_IPV6_SIT=m
++CONFIG_IPV6_NDISC_NODETYPE=y
++CONFIG_IPV6_TUNNEL=m
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_IPV6_SUBTREES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_IPV6_PIMSM_V2=y
++CONFIG_NETWORK_SECMARK=y
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++CONFIG_NETFILTER_ADVANCED=y
++CONFIG_BRIDGE_NETFILTER=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_NETLINK=m
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CT_ACCT=y
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_SECMARK=y
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NF_CT_PROTO_DCCP=m
++CONFIG_NF_CT_PROTO_GRE=m
++CONFIG_NF_CT_PROTO_SCTP=m
++CONFIG_NF_CT_PROTO_UDPLITE=m
++CONFIG_NF_CONNTRACK_AMANDA=m
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SANE=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_TPROXY=m
++CONFIG_NETFILTER_XTABLES=m
++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
++CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
++CONFIG_NETFILTER_XT_TARGET_DSCP=m
++CONFIG_NETFILTER_XT_TARGET_MARK=m
++CONFIG_NETFILTER_XT_TARGET_NFLOG=m
++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
++CONFIG_NETFILTER_XT_TARGET_RATEEST=m
++CONFIG_NETFILTER_XT_TARGET_TPROXY=m
++CONFIG_NETFILTER_XT_TARGET_TRACE=m
++CONFIG_NETFILTER_XT_TARGET_SECMARK=m
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
++CONFIG_NETFILTER_XT_MATCH_COMMENT=m
++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
++CONFIG_NETFILTER_XT_MATCH_DCCP=m
++CONFIG_NETFILTER_XT_MATCH_DSCP=m
++CONFIG_NETFILTER_XT_MATCH_ESP=m
++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_HELPER=m
++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
++CONFIG_NETFILTER_XT_MATCH_LENGTH=m
++CONFIG_NETFILTER_XT_MATCH_LIMIT=m
++CONFIG_NETFILTER_XT_MATCH_MAC=m
++CONFIG_NETFILTER_XT_MATCH_MARK=m
++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
++CONFIG_NETFILTER_XT_MATCH_OWNER=m
++CONFIG_NETFILTER_XT_MATCH_POLICY=m
++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
++CONFIG_NETFILTER_XT_MATCH_QUOTA=m
++CONFIG_NETFILTER_XT_MATCH_RATEEST=m
++CONFIG_NETFILTER_XT_MATCH_REALM=m
++CONFIG_NETFILTER_XT_MATCH_RECENT=m
++# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set
++CONFIG_NETFILTER_XT_MATCH_SCTP=m
++CONFIG_NETFILTER_XT_MATCH_SOCKET=m
++CONFIG_NETFILTER_XT_MATCH_STATE=m
++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
++CONFIG_NETFILTER_XT_MATCH_STRING=m
++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
++CONFIG_NETFILTER_XT_MATCH_TIME=m
++CONFIG_NETFILTER_XT_MATCH_U32=m
++CONFIG_IP_VS=m
++# CONFIG_IP_VS_IPV6 is not set
++# CONFIG_IP_VS_DEBUG is not set
++CONFIG_IP_VS_TAB_BITS=12
++
++#
++# IPVS transport protocol load balancing support
++#
++CONFIG_IP_VS_PROTO_TCP=y
++CONFIG_IP_VS_PROTO_UDP=y
++CONFIG_IP_VS_PROTO_AH_ESP=y
++CONFIG_IP_VS_PROTO_ESP=y
++CONFIG_IP_VS_PROTO_AH=y
++
++#
++# IPVS scheduler
++#
++CONFIG_IP_VS_RR=m
++CONFIG_IP_VS_WRR=m
++CONFIG_IP_VS_LC=m
++CONFIG_IP_VS_WLC=m
++CONFIG_IP_VS_LBLC=m
++CONFIG_IP_VS_LBLCR=m
++CONFIG_IP_VS_DH=m
++CONFIG_IP_VS_SH=m
++CONFIG_IP_VS_SED=m
++CONFIG_IP_VS_NQ=m
++
++#
++# IPVS application helper
++#
++CONFIG_IP_VS_FTP=m
++
++#
++# IP: Netfilter Configuration
++#
++CONFIG_NF_DEFRAG_IPV4=m
++CONFIG_NF_CONNTRACK_IPV4=m
++CONFIG_NF_CONNTRACK_PROC_COMPAT=y
++CONFIG_IP_NF_QUEUE=m
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_MATCH_ADDRTYPE=m
++CONFIG_IP_NF_MATCH_AH=m
++CONFIG_IP_NF_MATCH_ECN=m
++CONFIG_IP_NF_MATCH_TTL=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_TARGET_REJECT=m
++CONFIG_IP_NF_TARGET_LOG=m
++CONFIG_IP_NF_TARGET_ULOG=m
++CONFIG_NF_NAT=m
++CONFIG_NF_NAT_NEEDED=y
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_TARGET_NETMAP=m
++CONFIG_IP_NF_TARGET_REDIRECT=m
++CONFIG_NF_NAT_SNMP_BASIC=m
++CONFIG_NF_NAT_PROTO_DCCP=m
++CONFIG_NF_NAT_PROTO_GRE=m
++CONFIG_NF_NAT_PROTO_UDPLITE=m
++CONFIG_NF_NAT_PROTO_SCTP=m
++CONFIG_NF_NAT_FTP=m
++CONFIG_NF_NAT_IRC=m
++CONFIG_NF_NAT_TFTP=m
++CONFIG_NF_NAT_AMANDA=m
++CONFIG_NF_NAT_PPTP=m
++CONFIG_NF_NAT_H323=m
++CONFIG_NF_NAT_SIP=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP_NF_TARGET_CLUSTERIP=m
++CONFIG_IP_NF_TARGET_ECN=m
++CONFIG_IP_NF_TARGET_TTL=m
++CONFIG_IP_NF_RAW=m
++CONFIG_IP_NF_ARPTABLES=m
++CONFIG_IP_NF_ARPFILTER=m
++CONFIG_IP_NF_ARP_MANGLE=m
++
++#
++# IPv6: Netfilter Configuration
++#
++CONFIG_NF_CONNTRACK_IPV6=m
++CONFIG_IP6_NF_QUEUE=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_MATCH_AH=m
++CONFIG_IP6_NF_MATCH_EUI64=m
++CONFIG_IP6_NF_MATCH_FRAG=m
++CONFIG_IP6_NF_MATCH_OPTS=m
++CONFIG_IP6_NF_MATCH_HL=m
++CONFIG_IP6_NF_MATCH_IPV6HEADER=m
++CONFIG_IP6_NF_MATCH_MH=m
++CONFIG_IP6_NF_MATCH_RT=m
++CONFIG_IP6_NF_TARGET_LOG=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_TARGET_REJECT=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_IP6_NF_TARGET_HL=m
++CONFIG_IP6_NF_RAW=m
++
++#
++# DECnet: Netfilter Configuration
++#
++CONFIG_DECNET_NF_GRABULATOR=m
++CONFIG_BRIDGE_NF_EBTABLES=m
++CONFIG_BRIDGE_EBT_BROUTE=m
++CONFIG_BRIDGE_EBT_T_FILTER=m
++CONFIG_BRIDGE_EBT_T_NAT=m
++CONFIG_BRIDGE_EBT_802_3=m
++CONFIG_BRIDGE_EBT_AMONG=m
++CONFIG_BRIDGE_EBT_ARP=m
++CONFIG_BRIDGE_EBT_IP=m
++CONFIG_BRIDGE_EBT_IP6=m
++CONFIG_BRIDGE_EBT_LIMIT=m
++CONFIG_BRIDGE_EBT_MARK=m
++CONFIG_BRIDGE_EBT_PKTTYPE=m
++CONFIG_BRIDGE_EBT_STP=m
++CONFIG_BRIDGE_EBT_VLAN=m
++CONFIG_BRIDGE_EBT_ARPREPLY=m
++CONFIG_BRIDGE_EBT_DNAT=m
++CONFIG_BRIDGE_EBT_MARK_T=m
++CONFIG_BRIDGE_EBT_REDIRECT=m
++CONFIG_BRIDGE_EBT_SNAT=m
++CONFIG_BRIDGE_EBT_LOG=m
++CONFIG_BRIDGE_EBT_ULOG=m
++CONFIG_BRIDGE_EBT_NFLOG=m
++CONFIG_IP_DCCP=m
++CONFIG_INET_DCCP_DIAG=m
++
++#
++# DCCP CCIDs Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_DCCP_CCID2_DEBUG is not set
++CONFIG_IP_DCCP_CCID3=y
++# CONFIG_IP_DCCP_CCID3_DEBUG is not set
++CONFIG_IP_DCCP_CCID3_RTO=100
++CONFIG_IP_DCCP_TFRC_LIB=y
++CONFIG_IP_SCTP=m
++# CONFIG_SCTP_DBG_MSG is not set
++# CONFIG_SCTP_DBG_OBJCNT is not set
++# CONFIG_SCTP_HMAC_NONE is not set
++# CONFIG_SCTP_HMAC_SHA1 is not set
++CONFIG_SCTP_HMAC_MD5=y
++CONFIG_TIPC=m
++CONFIG_TIPC_ADVANCED=y
++CONFIG_TIPC_ZONES=3
++CONFIG_TIPC_CLUSTERS=1
++CONFIG_TIPC_NODES=255
++CONFIG_TIPC_SLAVE_NODES=0
++CONFIG_TIPC_PORTS=8191
++CONFIG_TIPC_LOG=0
++# CONFIG_TIPC_DEBUG is not set
++CONFIG_ATM=m
++CONFIG_ATM_CLIP=m
++CONFIG_ATM_CLIP_NO_ICMP=y
++CONFIG_ATM_LANE=m
++CONFIG_ATM_MPOA=m
++CONFIG_ATM_BR2684=m
++# CONFIG_ATM_BR2684_IPFILTER is not set
++CONFIG_STP=m
++CONFIG_GARP=m
++CONFIG_BRIDGE=m
++# CONFIG_NET_DSA is not set
++CONFIG_VLAN_8021Q=m
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_DECNET=m
++CONFIG_DECNET_ROUTER=y
++CONFIG_LLC=m
++CONFIG_LLC2=m
++CONFIG_IPX=m
++CONFIG_IPX_INTERN=y
++CONFIG_ATALK=m
++CONFIG_DEV_APPLETALK=m
++CONFIG_IPDDP=m
++CONFIG_IPDDP_ENCAP=y
++CONFIG_IPDDP_DECAP=y
++CONFIG_X25=m
++CONFIG_LAPB=m
++CONFIG_ECONET=m
++CONFIG_ECONET_AUNUDP=y
++CONFIG_ECONET_NATIVE=y
++CONFIG_WAN_ROUTER=m
++CONFIG_NET_SCHED=y
++
++#
++# Queueing/Scheduling
++#
++CONFIG_NET_SCH_CBQ=m
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_SCH_HFSC=m
++CONFIG_NET_SCH_ATM=m
++CONFIG_NET_SCH_PRIO=m
++CONFIG_NET_SCH_MULTIQ=m
++CONFIG_NET_SCH_RED=m
++CONFIG_NET_SCH_SFQ=m
++CONFIG_NET_SCH_TEQL=m
++CONFIG_NET_SCH_TBF=m
++CONFIG_NET_SCH_GRED=m
++CONFIG_NET_SCH_DSMARK=m
++CONFIG_NET_SCH_NETEM=m
++CONFIG_NET_SCH_DRR=m
++CONFIG_NET_SCH_INGRESS=m
++
++#
++# Classification
++#
++CONFIG_NET_CLS=y
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_TCINDEX=m
++CONFIG_NET_CLS_ROUTE4=m
++CONFIG_NET_CLS_ROUTE=y
++CONFIG_NET_CLS_FW=m
++CONFIG_NET_CLS_U32=m
++CONFIG_CLS_U32_PERF=y
++CONFIG_CLS_U32_MARK=y
++CONFIG_NET_CLS_RSVP=m
++CONFIG_NET_CLS_RSVP6=m
++CONFIG_NET_CLS_FLOW=m
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_EMATCH=y
++CONFIG_NET_EMATCH_STACK=32
++CONFIG_NET_EMATCH_CMP=m
++CONFIG_NET_EMATCH_NBYTE=m
++CONFIG_NET_EMATCH_U32=m
++CONFIG_NET_EMATCH_META=m
++CONFIG_NET_EMATCH_TEXT=m
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=m
++CONFIG_NET_ACT_GACT=m
++CONFIG_GACT_PROB=y
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NET_ACT_IPT=m
++CONFIG_NET_ACT_NAT=m
++CONFIG_NET_ACT_PEDIT=m
++CONFIG_NET_ACT_SIMP=m
++CONFIG_NET_ACT_SKBEDIT=m
++CONFIG_NET_CLS_IND=y
++CONFIG_NET_SCH_FIFO=y
++CONFIG_DCB=y
++
++#
++# Network testing
++#
++CONFIG_NET_PKTGEN=m
++# CONFIG_HAMRADIO is not set
++CONFIG_CAN=y
++CONFIG_CAN_RAW=y
++# CONFIG_CAN_BCM is not set
++
++#
++# CAN Device Drivers
++#
++CONFIG_CAN_VCAN=y
++# CONFIG_CAN_DEBUG_DEVICES is not set
++CONFIG_CAN_MSCAN=y
++CONFIG_CAN_MPC52XX=y
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++# CONFIG_PHONET is not set
++CONFIG_FIB_RULES=y
++# CONFIG_WIRELESS is not set
++# CONFIG_WIMAX is not set
++CONFIG_RFKILL=m
++CONFIG_RFKILL_INPUT=m
++# CONFIG_NET_9P is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_SYS_HYPERVISOR is not set
++CONFIG_CONNECTOR=m
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_OF_PARTS=y
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_GEN_PROBE=y
++CONFIG_MTD_CFI_ADV_OPTIONS=y
++CONFIG_MTD_CFI_NOSWAP=y
++# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
++# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
++# CONFIG_MTD_CFI_GEOMETRY is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_OTP is not set
++# CONFIG_MTD_CFI_INTELEXT is not set
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++CONFIG_MTD_COMPLEX_MAPPINGS=y
++# CONFIG_MTD_PHYSMAP is not set
++CONFIG_MTD_PHYSMAP_OF=y
++# CONFIG_MTD_PCI is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++CONFIG_MTD_NAND_MPC5125_NFC=y
++CONFIG_MTD_NAND_FSL=y
++CONFIG_MTD_NAND_MPC5125_HARDWARE_ECC_CORRECTION=y
++# CONFIG_NFC_DMA_ENABLE is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_NAND_FSL_ELBC is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR flash memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++
++#
++# UBI - Unsorted block images
++#
++# CONFIG_MTD_UBI is not set
++CONFIG_OF_DEVICE=y
++CONFIG_OF_I2C=m
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++CONFIG_BLK_DEV_FD=m
++CONFIG_BLK_CPQ_DA=m
++CONFIG_BLK_CPQ_CISS_DA=m
++CONFIG_CISS_SCSI_TAPE=y
++CONFIG_BLK_DEV_DAC960=m
++CONFIG_BLK_DEV_UMEM=m
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=m
++CONFIG_BLK_DEV_CRYPTOLOOP=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_BLK_DEV_SX8=m
++CONFIG_BLK_DEV_UB=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=4
++CONFIG_BLK_DEV_RAM_SIZE=32768
++# CONFIG_BLK_DEV_XIP is not set
++CONFIG_CDROM_PKTCDVD=m
++CONFIG_CDROM_PKTCDVD_BUFFERS=8
++# CONFIG_CDROM_PKTCDVD_WCACHE is not set
++CONFIG_ATA_OVER_ETH=m
++# CONFIG_BLK_DEV_HD is not set
++# CONFIG_MISC_DEVICES is not set
++CONFIG_TIFM_CORE=m
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++CONFIG_SCSI_TGT=m
++CONFIG_SCSI_NETLINK=y
++# CONFIG_SCSI_PROC_FS is not set
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++CONFIG_BLK_DEV_SR=y
++CONFIG_BLK_DEV_SR_VENDOR=y
++CONFIG_CHR_DEV_SG=y
++CONFIG_CHR_DEV_SCH=y
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++CONFIG_SCSI_SCAN_ASYNC=y
++CONFIG_SCSI_WAIT_SCAN=m
++
++#
++# SCSI Transports
++#
++CONFIG_SCSI_SPI_ATTRS=m
++CONFIG_SCSI_FC_ATTRS=m
++# CONFIG_SCSI_FC_TGT_ATTRS is not set
++CONFIG_SCSI_ISCSI_ATTRS=m
++CONFIG_SCSI_SAS_ATTRS=m
++CONFIG_SCSI_SAS_LIBSAS=m
++# CONFIG_SCSI_SAS_HOST_SMP is not set
++# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
++CONFIG_SCSI_SRP_ATTRS=m
++# CONFIG_SCSI_SRP_TGT_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++CONFIG_ISCSI_TCP=m
++CONFIG_BLK_DEV_3W_XXXX_RAID=m
++CONFIG_SCSI_3W_9XXX=m
++CONFIG_SCSI_ACARD=m
++CONFIG_SCSI_AACRAID=m
++CONFIG_SCSI_AIC7XXX=m
++CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
++CONFIG_AIC7XXX_RESET_DELAY_MS=15000
++CONFIG_AIC7XXX_DEBUG_ENABLE=y
++CONFIG_AIC7XXX_DEBUG_MASK=0
++CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
++CONFIG_SCSI_AIC7XXX_OLD=m
++CONFIG_SCSI_AIC79XX=m
++CONFIG_AIC79XX_CMDS_PER_DEVICE=32
++CONFIG_AIC79XX_RESET_DELAY_MS=15000
++CONFIG_AIC79XX_DEBUG_ENABLE=y
++CONFIG_AIC79XX_DEBUG_MASK=0
++CONFIG_AIC79XX_REG_PRETTY_PRINT=y
++CONFIG_SCSI_AIC94XX=m
++# CONFIG_AIC94XX_DEBUG is not set
++CONFIG_SCSI_DPT_I2O=m
++CONFIG_SCSI_ADVANSYS=m
++CONFIG_SCSI_ARCMSR=m
++CONFIG_MEGARAID_NEWGEN=y
++CONFIG_MEGARAID_MM=m
++CONFIG_MEGARAID_MAILBOX=m
++# CONFIG_MEGARAID_LEGACY is not set
++CONFIG_MEGARAID_SAS=m
++CONFIG_SCSI_HPTIOP=m
++CONFIG_SCSI_BUSLOGIC=m
++CONFIG_LIBFC=m
++CONFIG_FCOE=m
++CONFIG_SCSI_DMX3191D=m
++CONFIG_SCSI_EATA=m
++# CONFIG_SCSI_EATA_TAGGED_QUEUE is not set
++# CONFIG_SCSI_EATA_LINKED_COMMANDS is not set
++CONFIG_SCSI_EATA_MAX_TAGS=16
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_GDTH is not set
++CONFIG_SCSI_IPS=m
++# CONFIG_SCSI_INITIO is not set
++CONFIG_SCSI_INIA100=m
++CONFIG_SCSI_MVSAS=m
++CONFIG_SCSI_STEX=m
++CONFIG_SCSI_SYM53C8XX_2=m
++CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
++CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
++CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
++CONFIG_SCSI_SYM53C8XX_MMIO=y
++# CONFIG_SCSI_QLOGIC_1280 is not set
++CONFIG_SCSI_QLA_FC=m
++CONFIG_SCSI_QLA_ISCSI=m
++CONFIG_SCSI_LPFC=m
++# CONFIG_SCSI_LPFC_DEBUG_FS is not set
++CONFIG_SCSI_DC395x=m
++CONFIG_SCSI_DC390T=m
++CONFIG_SCSI_NSP32=m
++# CONFIG_SCSI_DEBUG is not set
++CONFIG_SCSI_SRP=m
++# CONFIG_SCSI_DH is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++
++#
++# Enable only one of the two stacks, unless you know what you are doing
++#
++CONFIG_FIREWIRE=m
++CONFIG_FIREWIRE_OHCI=m
++CONFIG_FIREWIRE_OHCI_DEBUG=y
++CONFIG_FIREWIRE_SBP2=m
++# CONFIG_IEEE1394 is not set
++# CONFIG_I2O is not set
++# CONFIG_MACINTOSH_DRIVERS is not set
++CONFIG_NETDEVICES=y
++CONFIG_IFB=m
++CONFIG_DUMMY=m
++CONFIG_BONDING=m
++CONFIG_MACVLAN=m
++CONFIG_EQUALIZER=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++CONFIG_ARCNET=m
++CONFIG_ARCNET_1201=m
++CONFIG_ARCNET_1051=m
++CONFIG_ARCNET_RAW=m
++CONFIG_ARCNET_CAP=m
++# CONFIG_ARCNET_COM90xx is not set
++CONFIG_ARCNET_COM90xxIO=m
++# CONFIG_ARCNET_RIM_I is not set
++CONFIG_ARCNET_COM20020=m
++CONFIG_ARCNET_COM20020_PCI=m
++CONFIG_PHYLIB=y
++
++#
++# MII PHY device drivers
++#
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_FIXED_PHY is not set
++# CONFIG_MDIO_BITBANG is not set
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_TULIP is not set
++# CONFIG_HP100 is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
++# CONFIG_NET_PCI is not set
++# CONFIG_B44 is not set
++# CONFIG_ATL2 is not set
++CONFIG_FS_ENET=y
++CONFIG_FS_ENET_MPC5121_FEC=y
++# CONFIG_FS_ENET_MPC5125_FEC2 is not set
++CONFIG_FS_ENET_HAS_FEC=y
++CONFIG_FS_ENET_MDIO_FEC=y
++# CONFIG_NETDEV_1000 is not set
++# CONFIG_NETDEV_10000 is not set
++CONFIG_MLX4_CORE=m
++# CONFIG_TR is not set
++
++#
++# Wireless LAN
++#
++# CONFIG_WLAN_PRE80211 is not set
++# CONFIG_WLAN_80211 is not set
++# CONFIG_IWLWIFI_LEDS is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++
++#
++# USB Network Adapters
++#
++CONFIG_USB_CATC=m
++CONFIG_USB_KAWETH=m
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_USBNET=m
++CONFIG_USB_NET_AX8817X=m
++CONFIG_USB_NET_CDCETHER=m
++CONFIG_USB_NET_DM9601=m
++CONFIG_USB_NET_SMSC95XX=m
++CONFIG_USB_NET_GL620A=m
++CONFIG_USB_NET_NET1080=m
++CONFIG_USB_NET_PLUSB=m
++CONFIG_USB_NET_MCS7830=m
++CONFIG_USB_NET_RNDIS_HOST=m
++CONFIG_USB_NET_CDC_SUBSET=m
++# CONFIG_USB_ALI_M5632 is not set
++# CONFIG_USB_AN2720 is not set
++# CONFIG_USB_BELKIN is not set
++# CONFIG_USB_ARMLINUX is not set
++# CONFIG_USB_EPSON2888 is not set
++# CONFIG_USB_KC2190 is not set
++CONFIG_USB_NET_ZAURUS=m
++CONFIG_USB_HSO=m
++# CONFIG_WAN is not set
++# CONFIG_ATM_DRIVERS is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++# CONFIG_PPP is not set
++CONFIG_SLIP=m
++# CONFIG_SLIP_COMPRESSED is not set
++# CONFIG_SLIP_SMART is not set
++# CONFIG_SLIP_MODE_SLIP6 is not set
++# CONFIG_NET_FC is not set
++CONFIG_NETCONSOLE=m
++# CONFIG_NETCONSOLE_DYNAMIC is not set
++CONFIG_NETPOLL=y
++# CONFIG_NETPOLL_TRAP is not set
++CONFIG_NET_POLL_CONTROLLER=y
++# CONFIG_ISDN is not set
++# CONFIG_PHONE is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=y
++CONFIG_INPUT_POLLDEV=m
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=m
++CONFIG_SERIO_I8042=m
++CONFIG_SERIO_SERPORT=m
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_RAW=m
++# CONFIG_SERIO_XILINX_XPS_PS2 is not set
++CONFIG_GAMEPORT=m
++CONFIG_GAMEPORT_NS558=m
++CONFIG_GAMEPORT_L4=m
++CONFIG_GAMEPORT_EMU10K1=m
++CONFIG_GAMEPORT_FM801=m
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
++CONFIG_DEVKMEM=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++CONFIG_NOZOMI=m
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_SERIAL_MPC52xx=y
++CONFIG_SERIAL_MPC52xx_CONSOLE=y
++CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD=115200
++CONFIG_SERIAL_JSM=m
++CONFIG_UNIX98_PTYS=y
++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++# CONFIG_BRIQ_PANEL is not set
++# CONFIG_HVC_RTAS is not set
++# CONFIG_HVC_UDBG is not set
++CONFIG_IPMI_HANDLER=m
++# CONFIG_IPMI_PANIC_EVENT is not set
++CONFIG_IPMI_DEVICE_INTERFACE=m
++CONFIG_IPMI_SI=m
++CONFIG_IPMI_WATCHDOG=m
++CONFIG_IPMI_POWEROFF=m
++CONFIG_HW_RANDOM=m
++CONFIG_NVRAM=y
++# CONFIG_R3964 is not set
++CONFIG_APPLICOM=m
++# CONFIG_RAW_DRIVER is not set
++CONFIG_TCG_TPM=m
++CONFIG_TCG_NSC=m
++CONFIG_TCG_ATMEL=m
++CONFIG_DEVPORT=y
++CONFIG_I2C=m
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_CHARDEV=m
++CONFIG_I2C_HELPER_AUTO=y
++CONFIG_I2C_ALGOBIT=m
++CONFIG_I2C_ALGOPCA=m
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_I801 is not set
++CONFIG_I2C_ISCH=m
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++CONFIG_I2C_SIS5595=m
++CONFIG_I2C_SIS630=m
++CONFIG_I2C_SIS96X=m
++CONFIG_I2C_VIA=m
++CONFIG_I2C_VIAPRO=m
++
++#
++# Mac SMBus host controller drivers
++#
++CONFIG_I2C_HYDRA=m
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++CONFIG_I2C_MPC=m
++CONFIG_I2C_OCORES=m
++CONFIG_I2C_SIMTEC=m
++
++#
++# External I2C/SMBus adapter drivers
++#
++CONFIG_I2C_PARPORT_LIGHT=m
++CONFIG_I2C_TAOS_EVM=m
++CONFIG_I2C_TINY_USB=m
++
++#
++# Graphics adapter I2C/DDC channel drivers
++#
++CONFIG_I2C_VOODOO3=m
++
++#
++# Other I2C/SMBus bus drivers
++#
++CONFIG_I2C_PCA_PLATFORM=m
++# CONFIG_I2C_STUB is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++CONFIG_DS1682=m
++CONFIG_SENSORS_PCF8574=m
++CONFIG_PCF8575=m
++CONFIG_SENSORS_PCA9539=m
++CONFIG_SENSORS_PCF8591=m
++CONFIG_SENSORS_MAX6875=m
++CONFIG_SENSORS_TSL2550=m
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_DEBUG_CHIP is not set
++# CONFIG_SPI is not set
++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
++# CONFIG_GPIOLIB is not set
++# CONFIG_W1 is not set
++CONFIG_POWER_SUPPLY=y
++CONFIG_POWER_SUPPLY_DEBUG=y
++# CONFIG_PDA_POWER is not set
++# CONFIG_WM8350_POWER is not set
++# CONFIG_BATTERY_DS2760 is not set
++# CONFIG_BATTERY_BQ27x00 is not set
++# CONFIG_CHARGER_PCF50633 is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++# CONFIG_THERMAL_HWMON is not set
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB=m
++CONFIG_SSB_SPROM=y
++CONFIG_SSB_PCIHOST_POSSIBLE=y
++CONFIG_SSB_PCIHOST=y
++# CONFIG_SSB_B43_PCI_BRIDGE is not set
++# CONFIG_SSB_DEBUG is not set
++CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
++CONFIG_SSB_DRIVER_PCICORE=y
++
++#
++# Multifunction device drivers
++#
++CONFIG_MFD_CORE=m
++CONFIG_MFD_SM501=m
++CONFIG_HTC_PASIC3=m
++# CONFIG_MFD_TMIO is not set
++CONFIG_MFD_WM8400=m
++CONFIG_MFD_WM8350=m
++CONFIG_MFD_WM8350_I2C=m
++CONFIG_MFD_PCF50633=m
++CONFIG_PCF50633_ADC=m
++CONFIG_PCF50633_GPIO=m
++# CONFIG_REGULATOR is not set
++
++#
++# Multimedia devices
++#
++
++#
++# Multimedia core support
++#
++CONFIG_VIDEO_DEV=m
++CONFIG_VIDEO_V4L2_COMMON=m
++# CONFIG_VIDEO_ALLOW_V4L1 is not set
++# CONFIG_VIDEO_V4L1_COMPAT is not set
++CONFIG_DVB_CORE=m
++CONFIG_VIDEO_MEDIA=m
++
++#
++# Multimedia drivers
++#
++# CONFIG_MEDIA_ATTACH is not set
++CONFIG_MEDIA_TUNER=m
++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
++CONFIG_MEDIA_TUNER_SIMPLE=m
++CONFIG_MEDIA_TUNER_TDA8290=m
++CONFIG_MEDIA_TUNER_TDA9887=m
++CONFIG_MEDIA_TUNER_TEA5761=m
++CONFIG_MEDIA_TUNER_TEA5767=m
++CONFIG_MEDIA_TUNER_MT20XX=m
++CONFIG_MEDIA_TUNER_XC2028=m
++CONFIG_MEDIA_TUNER_XC5000=m
++CONFIG_VIDEO_V4L2=m
++# CONFIG_VIDEO_CAPTURE_DRIVERS is not set
++# CONFIG_RADIO_ADAPTERS is not set
++# CONFIG_DVB_DYNAMIC_MINORS is not set
++# CONFIG_DVB_CAPTURE_DRIVERS is not set
++# CONFIG_DAB is not set
++
++#
++# Graphics support
++#
++CONFIG_AGP=m
++CONFIG_DRM=m
++CONFIG_DRM_TDFX=m
++CONFIG_DRM_R128=m
++CONFIG_DRM_RADEON=m
++CONFIG_DRM_MGA=m
++# CONFIG_DRM_SIS is not set
++CONFIG_DRM_VIA=m
++CONFIG_DRM_SAVAGE=m
++CONFIG_VGASTATE=m
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++# CONFIG_FB_BOOT_VESA_SUPPORT is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++CONFIG_FB_SYS_FILLRECT=m
++CONFIG_FB_SYS_COPYAREA=m
++CONFIG_FB_SYS_IMAGEBLIT=m
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++CONFIG_FB_SYS_FOPS=m
++CONFIG_FB_DEFERRED_IO=y
++CONFIG_FB_SVGALIB=m
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++CONFIG_FB_MODE_HELPERS=y
++CONFIG_FB_TILEBLITTING=y
++
++#
++# Frame buffer hardware drivers
++#
++CONFIG_FB_CIRRUS=m
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_OF is not set
++# CONFIG_FB_CT65550 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_VGA16 is not set
++# CONFIG_FB_UVESA is not set
++CONFIG_FB_S1D13XXX=m
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++CONFIG_FB_S3=m
++CONFIG_FB_SAVAGE=m
++# CONFIG_FB_SAVAGE_I2C is not set
++# CONFIG_FB_SAVAGE_ACCEL is not set
++# CONFIG_FB_SIS is not set
++CONFIG_FB_VIA=m
++CONFIG_FB_NEOMAGIC=m
++CONFIG_FB_KYRO=m
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++CONFIG_FB_VT8623=m
++CONFIG_FB_TRIDENT=m
++# CONFIG_FB_TRIDENT_ACCEL is not set
++CONFIG_FB_ARK=m
++CONFIG_FB_PM3=m
++# CONFIG_FB_CARMINE is not set
++CONFIG_FB_FSL_DIU=y
++CONFIG_FSL_DIU_FLIP_ON_VSYNC=y
++# CONFIG_FB_TMIO is not set
++CONFIG_FB_SM501=m
++CONFIG_FB_IBM_GXT4500=m
++# CONFIG_FB_VIRTUAL is not set
++CONFIG_FB_METRONOME=m
++CONFIG_FB_MB862XX=m
++# CONFIG_FB_MB862XX_PCI_GDC is not set
++# CONFIG_FB_MB862XX_LIME is not set
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++# CONFIG_LCD_CLASS_DEVICE is not set
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++# CONFIG_BACKLIGHT_GENERIC is not set
++
++#
++# Display device support
++#
++CONFIG_DISPLAY_SUPPORT=m
++
++#
++# Display hardware drivers
++#
++
++#
++# Console display driver support
++#
++CONFIG_VGA_CONSOLE=y
++# CONFIG_VGACON_SOFT_SCROLLBACK is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_LOGO_LINUX_CLUT224=y
++CONFIG_SOUND=y
++CONFIG_SOUND_OSS_CORE=y
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=m
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_SEQUENCER_OSS=y
++# CONFIG_SND_HRTIMER is not set
++# CONFIG_SND_DYNAMIC_MINORS is not set
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_VERBOSE_PROCFS=y
++CONFIG_SND_VERBOSE_PRINTK=y
++CONFIG_SND_DEBUG=y
++CONFIG_SND_DEBUG_VERBOSE=y
++CONFIG_SND_PCM_XRUN_DEBUG=y
++CONFIG_SND_VMASTER=y
++CONFIG_SND_AC97_CODEC=y
++CONFIG_SND_DRIVERS=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++# CONFIG_SND_AC97_POWER_SAVE is not set
++# CONFIG_SND_PCI is not set
++# CONFIG_SND_PPC is not set
++# CONFIG_SND_USB is not set
++CONFIG_SND_SOC=y
++
++#
++# ALSA SoC audio for Freescale SOCs
++#
++CONFIG_SND_SOC_MPC5121=y
++CONFIG_SND_SOC_MPC5121_ADS=y
++# CONFIG_SND_SOC_MPC5121_I2S is not set
++CONFIG_SND_SOC_I2C_AND_SPI=m
++# CONFIG_SND_SOC_ALL_CODECS is not set
++CONFIG_SND_SOC_AC97_CODEC=y
++# CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=y
++CONFIG_HID_SUPPORT=y
++CONFIG_HID=y
++# CONFIG_HID_DEBUG is not set
++CONFIG_HIDRAW=y
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=y
++CONFIG_HID_PID=y
++CONFIG_USB_HIDDEV=y
++
++#
++# Special HID drivers
++#
++CONFIG_HID_COMPAT=y
++CONFIG_HID_A4TECH=y
++CONFIG_HID_APPLE=y
++CONFIG_HID_BELKIN=y
++CONFIG_HID_CHERRY=y
++CONFIG_HID_CHICONY=y
++CONFIG_HID_CYPRESS=y
++CONFIG_HID_EZKEY=y
++CONFIG_HID_GYRATION=y
++CONFIG_HID_LOGITECH=y
++CONFIG_LOGITECH_FF=y
++CONFIG_LOGIRUMBLEPAD2_FF=y
++CONFIG_HID_MICROSOFT=y
++CONFIG_HID_MONTEREY=y
++CONFIG_HID_NTRIG=y
++CONFIG_HID_PANTHERLORD=y
++CONFIG_PANTHERLORD_FF=y
++CONFIG_HID_PETALYNX=y
++CONFIG_HID_SAMSUNG=y
++CONFIG_HID_SONY=y
++CONFIG_HID_SUNPLUS=y
++CONFIG_GREENASIA_FF=m
++CONFIG_HID_TOPSEED=y
++CONFIG_THRUSTMASTER_FF=m
++CONFIG_ZEROPLUS_FF=m
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++CONFIG_USB_DEVICE_CLASS=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_SUSPEND is not set
++# CONFIG_USB_OTG is not set
++# CONFIG_USB_MON is not set
++CONFIG_USB_WUSB=m
++CONFIG_USB_WUSB_CBAF=m
++# CONFIG_USB_WUSB_CBAF_DEBUG is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_ROOT_HUB_TT=y
++CONFIG_USB_EHCI_TT_NEWSCHED=y
++CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
++CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
++CONFIG_USB_EHCI_FSL=y
++CONFIG_USB_EHCI_HCD_PPC_OF=y
++# CONFIG_USB_OXU210HP_HCD is not set
++CONFIG_USB_ISP116X_HCD=m
++# CONFIG_USB_ISP1760_HCD is not set
++CONFIG_USB_OHCI_HCD=m
++# CONFIG_USB_OHCI_HCD_PPC_OF is not set
++# CONFIG_USB_OHCI_HCD_SSB is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_UHCI_HCD=m
++CONFIG_USB_U132_HCD=m
++CONFIG_USB_SL811_HCD=m
++CONFIG_USB_R8A66597_HCD=m
++CONFIG_USB_WHCI_HCD=m
++CONFIG_USB_HWA_HCD=m
++# CONFIG_USB_MUSB_HDRC is not set
++
++#
++# USB Device Class drivers
++#
++CONFIG_USB_ACM=m
++CONFIG_USB_PRINTER=m
++CONFIG_USB_WDM=m
++CONFIG_USB_TMC=m
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
++#
++
++#
++# see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++CONFIG_USB_LIBUSUAL=y
++
++#
++# USB Imaging devices
++#
++CONFIG_USB_MDC800=m
++CONFIG_USB_MICROTEK=m
++
++#
++# USB port drivers
++#
++CONFIG_USB_SERIAL=m
++CONFIG_USB_EZUSB=y
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_AIRCABLE=m
++CONFIG_USB_SERIAL_ARK3116=m
++CONFIG_USB_SERIAL_BELKIN=m
++CONFIG_USB_SERIAL_CH341=m
++# CONFIG_USB_SERIAL_WHITEHEAT is not set
++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
++# CONFIG_USB_SERIAL_CP2101 is not set
++CONFIG_USB_SERIAL_CYPRESS_M8=m
++CONFIG_USB_SERIAL_EMPEG=m
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_FUNSOFT=m
++CONFIG_USB_SERIAL_VISOR=m
++CONFIG_USB_SERIAL_IPAQ=m
++CONFIG_USB_SERIAL_IR=m
++CONFIG_USB_SERIAL_EDGEPORT=m
++CONFIG_USB_SERIAL_EDGEPORT_TI=m
++CONFIG_USB_SERIAL_GARMIN=m
++CONFIG_USB_SERIAL_IPW=m
++CONFIG_USB_SERIAL_IUU=m
++CONFIG_USB_SERIAL_KEYSPAN_PDA=m
++CONFIG_USB_SERIAL_KEYSPAN=m
++# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
++# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
++CONFIG_USB_SERIAL_KLSI=m
++CONFIG_USB_SERIAL_KOBIL_SCT=m
++CONFIG_USB_SERIAL_MCT_U232=m
++CONFIG_USB_SERIAL_MOS7720=m
++CONFIG_USB_SERIAL_MOS7840=m
++CONFIG_USB_SERIAL_MOTOROLA=m
++CONFIG_USB_SERIAL_NAVMAN=m
++CONFIG_USB_SERIAL_PL2303=m
++CONFIG_USB_SERIAL_OTI6858=m
++CONFIG_USB_SERIAL_SPCP8X5=m
++CONFIG_USB_SERIAL_HP4X=m
++CONFIG_USB_SERIAL_SAFE=m
++# CONFIG_USB_SERIAL_SAFE_PADDED is not set
++CONFIG_USB_SERIAL_SIEMENS_MPI=m
++CONFIG_USB_SERIAL_SIERRAWIRELESS=m
++# CONFIG_USB_SERIAL_TI is not set
++CONFIG_USB_SERIAL_CYBERJACK=m
++CONFIG_USB_SERIAL_XIRCOM=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_USB_SERIAL_OMNINET=m
++CONFIG_USB_SERIAL_OPTICON=m
++CONFIG_USB_SERIAL_DEBUG=m
++
++#
++# USB Miscellaneous drivers
++#
++CONFIG_USB_EMI62=m
++CONFIG_USB_EMI26=m
++CONFIG_USB_ADUTUX=m
++CONFIG_USB_SEVSEG=m
++CONFIG_USB_RIO500=m
++CONFIG_USB_LEGOTOWER=m
++CONFIG_USB_LCD=m
++CONFIG_USB_BERRY_CHARGE=m
++CONFIG_USB_LED=m
++CONFIG_USB_CYPRESS_CY7C63=m
++CONFIG_USB_CYTHERM=m
++# CONFIG_USB_PHIDGET is not set
++CONFIG_USB_IDMOUSE=m
++CONFIG_USB_FTDI_ELAN=m
++CONFIG_USB_APPLEDISPLAY=m
++# CONFIG_USB_SISUSBVGA is not set
++CONFIG_USB_LD=m
++CONFIG_USB_TRANCEVIBRATOR=m
++CONFIG_USB_IOWARRIOR=m
++CONFIG_USB_TEST=m
++CONFIG_USB_ISIGHTFW=m
++CONFIG_USB_VST=m
++CONFIG_USB_ATM=m
++CONFIG_USB_SPEEDTOUCH=m
++CONFIG_USB_CXACRU=m
++CONFIG_USB_UEAGLEATM=m
++CONFIG_USB_XUSBATM=m
++# CONFIG_USB_GADGET is not set
++
++#
++# OTG and related infrastructure
++#
++CONFIG_UWB=m
++CONFIG_UWB_HWA=m
++CONFIG_UWB_WHCI=m
++CONFIG_UWB_WLP=m
++CONFIG_UWB_I1480U=m
++CONFIG_UWB_I1480U_WLP=m
++CONFIG_MMC=y
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_UNSAFE_RESUME=y
++
++#
++# MMC/SD/SDIO Card Drivers
++#
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_BOUNCE=y
++CONFIG_SDIO_UART=m
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++CONFIG_MMC_SDHCI=m
++CONFIG_MMC_SDHCI_PCI=m
++CONFIG_MMC_RICOH_MMC=m
++CONFIG_MMC_MPC5121=y
++# CONFIG_MMC_MPC5121_USE_DMA is not set
++# CONFIG_MMC_MPC5121_USE_CARD_INSERTION_INT is not set
++CONFIG_MMC_WBSD=m
++CONFIG_MMC_TIFM_SD=m
++CONFIG_MEMSTICK=m
++# CONFIG_MEMSTICK_DEBUG is not set
++
++#
++# MemoryStick drivers
++#
++# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
++CONFIG_MSPRO_BLOCK=m
++
++#
++# MemoryStick Host Controller Drivers
++#
++CONFIG_MEMSTICK_TIFM_MS=m
++CONFIG_MEMSTICK_JMICRON_38X=m
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++CONFIG_INFINIBAND=m
++CONFIG_INFINIBAND_USER_MAD=m
++CONFIG_INFINIBAND_USER_ACCESS=m
++CONFIG_INFINIBAND_USER_MEM=y
++CONFIG_INFINIBAND_ADDR_TRANS=y
++CONFIG_INFINIBAND_MTHCA=m
++CONFIG_INFINIBAND_MTHCA_DEBUG=y
++CONFIG_INFINIBAND_AMSO1100=m
++# CONFIG_INFINIBAND_AMSO1100_DEBUG is not set
++CONFIG_MLX4_INFINIBAND=m
++CONFIG_INFINIBAND_NES=m
++# CONFIG_INFINIBAND_NES_DEBUG is not set
++CONFIG_INFINIBAND_IPOIB=m
++# CONFIG_INFINIBAND_IPOIB_CM is not set
++CONFIG_INFINIBAND_IPOIB_DEBUG=y
++# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
++CONFIG_INFINIBAND_SRP=m
++CONFIG_INFINIBAND_ISER=m
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_HCTOSYS=y
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++# CONFIG_RTC_DEBUG is not set
++
++#
++# RTC interfaces
++#
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++# CONFIG_RTC_DRV_TEST is not set
++
++#
++# I2C RTC drivers
++#
++# CONFIG_RTC_DRV_DS2068A is not set
++# CONFIG_RTC_DRV_DS1307 is not set
++# CONFIG_RTC_DRV_DS1374 is not set
++# CONFIG_RTC_DRV_DS1672 is not set
++# CONFIG_RTC_DRV_MAX6900 is not set
++# CONFIG_RTC_DRV_RS5C372 is not set
++# CONFIG_RTC_DRV_ISL1208 is not set
++# CONFIG_RTC_DRV_X1205 is not set
++# CONFIG_RTC_DRV_PCF8563 is not set
++# CONFIG_RTC_DRV_PCF8583 is not set
++# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_S35390A is not set
++# CONFIG_RTC_DRV_FM3130 is not set
++# CONFIG_RTC_DRV_RX8581 is not set
++
++#
++# SPI RTC drivers
++#
++
++#
++# Platform RTC drivers
++#
++# CONFIG_RTC_DRV_CMOS is not set
++# CONFIG_RTC_DRV_DS1286 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
++# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
++# CONFIG_RTC_DRV_M48T86 is not set
++# CONFIG_RTC_DRV_M48T35 is not set
++# CONFIG_RTC_DRV_M48T59 is not set
++# CONFIG_RTC_DRV_BQ4802 is not set
++# CONFIG_RTC_DRV_V3020 is not set
++# CONFIG_RTC_DRV_WM8350 is not set
++# CONFIG_RTC_DRV_PCF50633 is not set
++
++#
++# on-CPU RTC drivers
++#
++# CONFIG_RTC_DRV_PPC is not set
++CONFIG_RTC_DRV_MPC5121=y
++CONFIG_DMADEVICES=y
++
++#
++# DMA Devices
++#
++CONFIG_FSL_DMA=y
++CONFIG_DMA_ENGINE=y
++
++#
++# DMA Clients
++#
++# CONFIG_NET_DMA is not set
++# CONFIG_DMATEST is not set
++CONFIG_UIO=m
++CONFIG_UIO_CIF=m
++CONFIG_UIO_PDRV=m
++CONFIG_UIO_PDRV_GENIRQ=m
++CONFIG_UIO_SMX=m
++CONFIG_UIO_SERCOS3=m
++# CONFIG_STAGING is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++CONFIG_EXT4_FS=y
++CONFIG_EXT4DEV_COMPAT=y
++CONFIG_EXT4_FS_XATTR=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_FILE_LOCKING=y
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++# CONFIG_QUOTA is not set
++CONFIG_AUTOFS_FS=y
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_GENERIC_ACL=y
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_UDF_NLS=y
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++CONFIG_NTFS_FS=y
++# CONFIG_NTFS_DEBUG is not set
++CONFIG_NTFS_RW=y
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_KCORE=y
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_CONFIGFS_FS=m
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_YAFFS_FS=y
++CONFIG_YAFFS_YAFFS1=y
++# CONFIG_YAFFS_9BYTE_TAGS is not set
++# CONFIG_YAFFS_DOES_ECC is not set
++CONFIG_YAFFS_YAFFS2=y
++CONFIG_YAFFS_AUTO_YAFFS2=y
++CONFIG_YAFFS_DISABLE_TAGS_ECC=y
++# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
++# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
++CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y
++CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
++# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
++# CONFIG_JFFS2_FS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++CONFIG_SUNRPC_XPRT_RDMA=m
++CONFIG_SUNRPC_REGISTER_V4=y
++CONFIG_RPCSEC_GSS_KRB5=y
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++CONFIG_AMIGA_PARTITION=y
++# CONFIG_ATARI_PARTITION is not set
++CONFIG_MAC_PARTITION=y
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++CONFIG_KARMA_PARTITION=y
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8895-i"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=m
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ASCII=m
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++CONFIG_NLS_UTF8=m
++# CONFIG_DLM is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_GENERIC_FIND_LAST_BIT=y
++CONFIG_CRC_CCITT=m
++CONFIG_CRC16=y
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC_ITU_T=m
++CONFIG_CRC32=y
++CONFIG_CRC7=m
++CONFIG_LIBCRC32C=m
++CONFIG_ZLIB_INFLATE=m
++CONFIG_ZLIB_DEFLATE=m
++CONFIG_LZO_COMPRESS=m
++CONFIG_LZO_DECOMPRESS=m
++CONFIG_TEXTSEARCH=y
++CONFIG_TEXTSEARCH_KMP=m
++CONFIG_TEXTSEARCH_BM=m
++CONFIG_TEXTSEARCH_FSM=m
++CONFIG_PLIST=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
++CONFIG_HAVE_LMB=y
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++# CONFIG_ENABLE_WARN_DEPRECATED is not set
++# CONFIG_ENABLE_MUST_CHECK is not set
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_KERNEL is not set
++CONFIG_STACKTRACE=y
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_MEMORY_INIT=y
++# CONFIG_RCU_CPU_STALL_DETECTOR is not set
++# CONFIG_LATENCYTOP is not set
++# CONFIG_SYSCTL_SYSCALL_CHECK is not set
++CONFIG_NOP_TRACER=y
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_RING_BUFFER=y
++CONFIG_TRACING=y
++
++#
++# Tracers
++#
++# CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set
++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++CONFIG_PRINT_STACK_DEPTH=64
++# CONFIG_IRQSTACKS is not set
++# CONFIG_VIRQ_DEBUG is not set
++# CONFIG_BOOTX_TEXT is not set
++# CONFIG_PPC_EARLY_DEBUG is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++CONFIG_SECURITYFS=y
++# CONFIG_SECURITY_FILE_CAPABILITIES is not set
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_FIPS=y
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++CONFIG_CRYPTO_GF128MUL=m
++CONFIG_CRYPTO_NULL=m
++# CONFIG_CRYPTO_CRYPTD is not set
++CONFIG_CRYPTO_AUTHENC=m
++CONFIG_CRYPTO_TEST=m
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=m
++CONFIG_CRYPTO_GCM=m
++CONFIG_CRYPTO_SEQIV=m
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTR=m
++CONFIG_CRYPTO_CTS=m
++CONFIG_CRYPTO_ECB=m
++CONFIG_CRYPTO_LRW=m
++CONFIG_CRYPTO_PCBC=m
++CONFIG_CRYPTO_XTS=m
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_HMAC=m
++CONFIG_CRYPTO_XCBC=m
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=m
++CONFIG_CRYPTO_MD4=m
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_MICHAEL_MIC=m
++CONFIG_CRYPTO_RMD128=m
++CONFIG_CRYPTO_RMD160=m
++CONFIG_CRYPTO_RMD256=m
++CONFIG_CRYPTO_RMD320=m
++CONFIG_CRYPTO_SHA1=m
++CONFIG_CRYPTO_SHA256=m
++CONFIG_CRYPTO_SHA512=m
++CONFIG_CRYPTO_TGR192=m
++CONFIG_CRYPTO_WP512=m
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=m
++CONFIG_CRYPTO_ANUBIS=m
++CONFIG_CRYPTO_ARC4=m
++CONFIG_CRYPTO_BLOWFISH=m
++CONFIG_CRYPTO_CAMELLIA=m
++CONFIG_CRYPTO_CAST5=m
++CONFIG_CRYPTO_CAST6=m
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_FCRYPT=m
++CONFIG_CRYPTO_KHAZAD=m
++CONFIG_CRYPTO_SALSA20=m
++CONFIG_CRYPTO_SEED=m
++CONFIG_CRYPTO_SERPENT=m
++CONFIG_CRYPTO_TEA=m
++CONFIG_CRYPTO_TWOFISH=m
++CONFIG_CRYPTO_TWOFISH_COMMON=m
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=m
++CONFIG_CRYPTO_LZO=m
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=m
++# CONFIG_CRYPTO_HW is not set
++CONFIG_PPC_CLOCK=y
++CONFIG_PPC_LIB_RHEAP=y
++# CONFIG_VIRTUALIZATION is not set
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/dma-mapping.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/dma-mapping.h
+--- linux-2.6.29/arch/powerpc/include/asm/dma-mapping.h	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/dma-mapping.h	2010-04-13 20:23:26.000000000 +0200
+@@ -242,19 +242,51 @@
+ static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+ 				       dma_addr_t *dma_handle, gfp_t flag)
+ {
++#ifdef CONFIG_PPC64
+ 	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+ 
+ 	BUG_ON(!dma_ops);
+ 	return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
++#else
++#ifdef CONFIG_NOT_COHERENT_CACHE
++	return __dma_alloc_coherent(size, dma_handle, flag);
++#else
++	void *ret;
++	/* ignore region specifiers */
++	flag &= ~(__GFP_DMA | __GFP_HIGHMEM);
++
++	if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
++		flag |= GFP_DMA;
++
++	ret = (void *)__get_free_pages(flag, get_order(size));
++
++	if (ret != NULL) {
++		memset(ret, 0, size);
++		*dma_handle = virt_to_bus(ret);
++	}
++
++	return ret;
++#endif
++
++#endif
+ }
+ 
+ static inline void dma_free_coherent(struct device *dev, size_t size,
+ 				     void *cpu_addr, dma_addr_t dma_handle)
+ {
++#ifdef CONFIG_PPC64
+ 	struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
+ 
+ 	BUG_ON(!dma_ops);
+ 	dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
++#else
++#ifdef CONFIG_NOT_COHERENT_CACHE
++	__dma_free_coherent(size, cpu_addr);
++#else
++	free_pages((unsigned long)cpu_addr, get_order(size));
++#endif
++
++#endif
+ }
+ 
+ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+@@ -438,6 +470,27 @@
+ 	BUG_ON(direction == DMA_NONE);
+ 	__dma_sync(vaddr, size, (int)direction);
+ }
++#ifdef CONFIG_PPC64
+ 
++#else
++/*
++* A helper to mmap the pages allocated via dma_alloc_coherent()
++*/
++static inline int dma_mmap_coherent(struct device *dev,
++				struct vm_area_struct *vma,
++				void *cpu_addr, dma_addr_t handle,
++				size_t size)
++{
++	struct page *pg;
++#ifdef CONFIG_NOT_COHERENT_CACHE
++	cpu_addr = bus_to_virt(handle);
++#endif
++	pg = virt_to_page(cpu_addr);
++	return remap_pfn_range(vma,
++				vma->vm_start,
++				page_to_pfn(pg) + vma->vm_pgoff,
++				size, vma->vm_page_prot);
++}
++#endif /* CONFIG_PPC64 */
+ #endif /* __KERNEL__ */
+ #endif	/* _ASM_DMA_MAPPING_H */
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/fsl_usb_gadget.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/fsl_usb_gadget.h
+--- linux-2.6.29/arch/powerpc/include/asm/fsl_usb_gadget.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/fsl_usb_gadget.h	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,25 @@
++/*
++ * Copyright (C) 2008 Freescale Semicondutor, Inc. All rights reserved.
++ *
++ * Author: Bruce Schmid <duck@freescale.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++/*
++ * These routines are needed for i2c/serial transceivers
++ * on other platforms
++ */
++static inline void
++fsl_platform_set_device_mode(struct fsl_usb2_platform_data *pdata)
++{}
++
++static inline void
++fsl_platform_pullup_enable(struct fsl_usb2_platform_data *pdata)
++{}
++
++static inline void
++fsl_platform_pullup_disable(struct fsl_usb2_platform_data *pdata)
++{}
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/fsl_usb.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/fsl_usb.h
+--- linux-2.6.29/arch/powerpc/include/asm/fsl_usb.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/fsl_usb.h	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,103 @@
++/* Copyright (c) 2008 Freescale Semiconductor Inc.
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the  GNU General Public License along
++ * with this program; if not, write  to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++#ifndef _FSL_USB_H
++#define _FSL_USB_H
++
++/* ehci_arc_hc_driver.flags value */
++#define FSL_PLATFORM_HC_FLAGS (HCD_USB2 | HCD_MEMORY)
++
++static void fsl_setup_phy(struct ehci_hcd *ehci, enum fsl_usb2_phy_modes phy_mode,
++		          int port_offset);
++
++static inline void fsl_platform_usb_setup(struct ehci_hcd *ehci)
++{
++	struct usb_hcd *hcd = ehci_to_hcd(ehci);
++	struct fsl_usb2_platform_data *pdata;
++	void __iomem *non_ehci = hcd->regs;
++	u32 tmp;
++
++	pdata = hcd->self.controller->platform_data;
++
++	/* Enable PHY interface in the control reg. */
++	if (pdata->have_sysif_regs) {
++		out_be32(non_ehci + FSL_SOC_USB_CTRL, 0x00000004);
++		out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0000001b);
++	}
++
++#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
++	/*
++	 * Turn on cache snooping hardware, since some PowerPC platforms
++	 * wholly rely on hardware to deal with cache coherent
++	 */
++
++	/* Setup Snooping for all the 4GB space */
++	/* SNOOP1 starts from 0x0, size 2G */
++	out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
++	/* SNOOP2 starts from 0x80000000, size 2G */
++	out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
++#endif
++
++	if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
++			(pdata->operating_mode == FSL_USB2_DR_OTG))
++		fsl_setup_phy(ehci, pdata->phy_mode, 0);
++
++	if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
++		unsigned int chip, rev, svr;
++
++		svr = mfspr(SPRN_SVR);
++		chip = svr >> 16;
++		rev = (svr >> 4) & 0xf;
++
++		/* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
++		if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
++			ehci->has_fsl_port_bug = 1;
++
++		if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
++			fsl_setup_phy(ehci, pdata->phy_mode, 0);
++		if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
++			fsl_setup_phy(ehci, pdata->phy_mode, 1);
++	}
++
++	/* put controller in host mode. */
++	tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
++	ehci_writel(ehci, tmp, non_ehci + FSL_SOC_USB_USBMODE);
++
++	if (pdata->have_sysif_regs) {
++		out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
++		out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
++		out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
++	}
++}
++
++static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd)
++{
++	unsigned int temp;
++	struct fsl_usb2_platform_data *pdata;
++
++	pdata = hcd->self.controller->platform_data;
++
++	temp = in_le32(hcd->regs + FSL_SOC_USB_USBMODE);
++	temp |= USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
++	out_le32(hcd->regs + FSL_SOC_USB_USBMODE, temp);
++}
++
++/* Needed for i2c/serial transceivers */
++static inline void
++fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on)
++{
++}
++#endif /* _FSL_USB_H */
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/fsl_usb_io.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/fsl_usb_io.h
+--- linux-2.6.29/arch/powerpc/include/asm/fsl_usb_io.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/fsl_usb_io.h	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,107 @@
++/* Copyright (c) 2008 Freescale Semiconductor Inc.
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the  GNU General Public License along
++ * with this program; if not, write  to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++#ifndef _FSL_USB_IO_H
++#define _FSL_USB_IO_H
++
++/*
++ * On some SoCs, the USB controller registers can be big or little endian,
++ * depending on the version of the chip.  For these SoCs, the kernel
++ * should be configured with CONFIG_USB_FSL_BIG_ENDIAN_MMIO enabled.  
++ *
++ * The "big-endian-regs" property should be specified in the USB node
++ * of the device tree for SoCs that have BE USB registers.
++ * pdata->big_endian_mmio reflects the state of that device tree property.
++ *
++ * In order to be able to run the same kernel binary on 2 different
++ * versions of an SoC, the BE/LE decision must be made at run time.
++ * _fsl_readl and fsl_writel are pointers to the BE or LE readl()
++ * and writel() functions, and fsl_readl() and fsl_writel() call through
++ * those pointers.
++ *
++ * For SoCs with the usual LE USB registers, don't enable
++ * CONFIG_USB_FSL_BIG_ENDIAN_MMIO, and then fsl_readl() and fsl_writel()
++ * are just macro wrappers for in_le32() and out_le32().
++ * 
++ * In either (LE or mixed) case, the function fsl_set_usb_accessors()
++ * should be called at probe time, to either set up the readl/writel
++ * function pointers (mixed case), or do nothing (LE case).
++ *
++ * The host USB drivers already have a mechanism to handle BE/LE
++ * registers.  The functionality here is intended to be used by the
++ * gadget and OTG transceiver drivers.
++ *
++ * This file also contains controller-to-cpu accessors for the
++ * USB descriptors, since their endianess is also SoC dependant.
++ * The kernel option CONFIG_USB_FSL_BIG_ENDIAN_DESC configures
++ * which way to go.
++ */
++
++#if 1 /*CONFIG_USB_FSL_BIG_ENDIAN_MMIO*/
++static u32 __maybe_unused _fsl_readl_be(const volatile void __iomem *p)
++{
++	return in_be32(p);
++}
++static u32 __maybe_unused _fsl_readl_le(const volatile void __iomem *p)
++{
++	return in_le32(p);
++}
++
++static void __maybe_unused _fsl_writel_be(u32 v, volatile void __iomem *p)
++{
++	out_be32(p, v);
++}
++static void __maybe_unused _fsl_writel_le(u32 v, volatile void __iomem *p)
++{
++	out_le32(p, v);
++}
++
++static u32 (*_fsl_readl)(const volatile void __iomem *p);
++static void (*_fsl_writel)(u32 v, volatile void __iomem *p);
++
++#define fsl_readl(p)		(*_fsl_readl)((p))
++#define fsl_writel(v, p)	(*_fsl_writel)((v), (p))
++
++static inline void fsl_set_usb_accessors(struct fsl_usb2_platform_data *pdata)
++{
++	if (pdata->big_endian_mmio) {
++		_fsl_readl = _fsl_readl_be;
++		_fsl_writel = _fsl_writel_be;
++	} else {
++		_fsl_readl = _fsl_readl_le;
++		_fsl_writel = _fsl_writel_le;
++	}
++}
++
++#else /* CONFIG_USB_FSL_BIG_ENDIAN_MMIO */
++
++#define fsl_readl(addr)		in_le32((addr))
++#define fsl_writel(val32, addr) out_le32((addr), (val32))
++
++static inline void fsl_set_usb_accessors(struct fsl_usb2_platform_data *pdata)
++{
++}
++#endif /* CONFIG_USB_FSL_BIG_ENDIAN_MMIO */
++
++#ifdef CONFIG_USB_FSL_BIG_ENDIAN_DESC
++#define cpu_to_hc32(x)	(x)
++#define hc32_to_cpu(x)	(x)
++#else
++#define cpu_to_hc32(x)	cpu_to_le32((x))
++#define hc32_to_cpu(x)	le32_to_cpu((x))
++#endif
++
++#endif /* _FSL_USB_IO_H */
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/mpc5121_struct.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/mpc5121_struct.h
+--- linux-2.6.29/arch/powerpc/include/asm/mpc5121_struct.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/mpc5121_struct.h	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,149 @@
++/******************
++*******************/
++#ifndef _PIEBOX_STRUCT_H_
++#define	_PIEBOX_STRUCT_H_
++
++#define	CFG_IMMR	0x80000000
++
++
++#define	SYS_CONFIGRATION_BASE	0x0000
++#define	SOFTWARE_WATCHDOG_BASE	0x0900
++#define	REAL_TIME_BASE			0x0a00
++#define	GENERAL_TIMER_BASE		0x0b00
++#define	INTERRUPT_CONTROLER_BASE	0x0c00
++#define	CSB_BASE					0x0d00
++#define	RESET_BASE					0x0e00
++#define	CLOCK_BASE					0x0f00
++#define	POWER_MANAGEMENT_BASE	0x1000
++#define	GENERAL_GPIO_BASE			0x1100
++#define	MSCAN_BASE				0x1300
++#define	BYTE_CONTROLLER_BASE		0x1400
++#define	SECURE_DIGITAL_BASE		0x1500
++#define	SONY_DIGITAL_BASE			0x1600
++#define	I2C1_BASE					0x1700
++#define	I2C2_BASE					0x1720
++#define	I2C3_BASE					0x1740
++#define	AXE_BASE					0x2000
++#define	DISPLAY_BASE				0x2100
++#define	CLOCK_FREQUENCY_BASE		0x2200
++#define	FAST_ETHERNET_BASE		0x2800
++#define	USB_ULPI_BASE				0x3000
++#define	USB_UTMI_BASE				0x4000
++#define	PCI_DMA_BASE				0x8000
++#define	PCI_CONFIG_BASE			0x8300
++#define	PCI_IOS_BASE				0x8400
++#define	PCI_CONTROLLER_BASE		0x8500
++#define	DRAM_CONTROLLER_BASE		0x9000
++#define	IO_CONTROL_BASE			0xa000
++#define	IIM_BASE					0xb000
++#define	LOCALPLUS_BASE			0x10000
++#define	PATA_BASE					0x10200
++#define	PSC_CONTROL_BASE			0x11000
++#define	PSC_N_CONTROL_BASE(n)		(n*0x100+PSC_CONTROL_BASE)
++#define	SFIFO_PSC_BASE			0x11f00
++#define	IO_CONTROL_MEM_REG		(CFG_IMMR+IO_CONTROL_BASE+0x000)
++#define	IO_CONTROL_GP_REG			(CFG_IMMR+IO_CONTROL_BASE+0x004)
++
++
++
++
++#define PIEBOX_LED_SET_REG(addr,value)	 *(volatile unsigned int *)(addr)=(value)
++
++
++#define	GPIO_BIT_OFFSET(x)		(1<<(31-x))
++#define	GPT_BIT_OFFSET(x)		(1<<(7-x))
++#define	GPIO_PIEBOX_BIT_OFFSET(x)		GPIO_BIT_OFFSET(x)
++
++#define	GPIO_RUN_LED		1
++#define	GPIO_P_LED			15
++#define	GPIO_YNET_LED		14
++#define	GPIO_PWROFF_MUTE	13
++
++#define COLOR_BIT_MASK	(GPIO_BIT_OFFSET(GPIO_RUN_LED)|GPIO_BIT_OFFSET(GPIO_P_LED)|GPIO_BIT_OFFSET(GPIO_YNET_LED))
++/*
++#define	GPIO_WIFI_P		13
++*/
++/*
++#define	GPIO_PDN			12
++*/
++#define	GPIO_LED_PWM		0
++#define	GPIO_PENABLE_LED	11
++#define	GPIO_PIEKEY_LED	10
++
++#define	GPIO_KEY_VOL		20
++#define	GPIO_KEY_MENU		22
++#define	GPIO_KEY_LCD		3
++
++
++#define	GPIO_SYSTEM_START_NORFLASH		12
++
++#define	GPIO_HDR_GPIO6_LCD_ENABLE	6
++#define	GPIO_LCD_GPT2					2
++
++#define	LCD_BRIGHT_GPT_MAX		100		
++#define	LED_BRIGHT_GPT_MAX		100	
++
++/**************
++gpio int mode
++******************/
++#define	GPIO_INTERRUPT_MODE_ANY		0
++#define	GPIO_INTERRUPT_MODE_LOW_TO_HEIGHT	1
++#define	GPIO_INTERRUPT_MODE_HIGHT_TO_LOW	2
++#define	GPIO_INTERRUPT_MODE_PLUSE	3
++
++
++enum{
++	PIEBOX_LED_GREEN=0,
++	PIEBOX_LED_RED,
++	PIEBOX_LED_YELLOW	,
++	PIEBOX_LED_PIEKEY
++};
++
++/************
++mtc systemcall defined
++**************/
++#define	MTC_SYSTEM_CALL_NUMBER		319
++
++#define	MTC_SYSTEM_CALL_SET_LCD_VALUE	0xf000
++#define	MTC_SYSTEM_CALL_GET_LCD_VALUE	0xf001
++#define	MTC_SYSTEM_CALL_SET_LED_VALUE	0xf002
++#define	MTC_SYSTEM_CALL_GET_LED_VALUE	0xf003
++
++#define	MTC_SYSTEM_CALL_GET_LED_STATUS	0xf004
++#define	MTC_SYSTEM_CALL_SET_LED_STATUS	0xf005
++
++#define	MTC_SYSTEM_CALL_GET_LCD_MAX		0xf006
++#define	MTC_SYSTEM_CALL_GET_LED_MAX		0xf007
++
++#define	MTC_SYSTEM_CALL_GET_FB0_ADDR	0xf008
++
++
++
++
++
++struct io_control_struct {
++	 unsigned int io_control;
++	unsigned int 	value;
++};
++struct mpc5121_gpio_struct{
++	volatile unsigned int 	gpdir;
++	volatile unsigned int 	gpodr;
++	volatile unsigned int 	gpdat;
++	volatile unsigned int 	gpier;	
++	volatile unsigned int 	gpimr;
++	volatile unsigned int 	gpicr1;
++	volatile unsigned int 	gpicr2;
++};
++struct mpc5121_gpt_struct{
++	volatile unsigned int 	enable_mode;
++	volatile unsigned int	counter;
++	volatile unsigned int	pwm_config;
++	volatile unsigned int	status;	
++};
++
++struct mpc5121_gpt_control_struct{
++	struct mpc5121_gpt_struct	gpt[7];
++};
++ void mpc5121_usb_ide_dma_lock(void);
++ void mpc5121_usb_ide_dma_unlock(void);
++#endif
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/mpc5125_nfc.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/mpc5125_nfc.h
+--- linux-2.6.29/arch/powerpc/include/asm/mpc5125_nfc.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/mpc5125_nfc.h	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,487 @@
++/*
++ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Author: Shaohui Xie <b21989@freescale.com>
++ *
++ * Description:
++ * MPC5125 Nand driver.
++ *
++ * This is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef MPC5125_NFC_H
++#define MPC5125_NFC_H
++
++/* I/O Control Register OFFSETS */
++#define IOCTL_MEM		0x00
++#define IOCTL_GBOBE		0x01
++#define IOCTL_LPC_CLK		0x04
++#define IOCTL_LPC_OE_B		0x05
++#define IOCTL_LPC_RWB		0x06
++#define IOCTL_LPC_CS0_B	0x07
++#define IOCTL_LPC_ACK_B	0x08
++#define IOCTL_LPC_AX03		0x09
++#define IOCTL_EMB_AX02		0x0a
++#define IOCTL_EMB_AX01		0x0b
++#define IOCTL_EMB_AX00		0x0c
++#define IOCTL_EMB_AD31		0x0d
++#define IOCTL_EMB_AD30		0x0e
++#define IOCTL_EMB_AD29		0x0f
++#define IOCTL_EMB_AD28		0x10
++#define IOCTL_EMB_AD27		0x11
++#define IOCTL_EMB_AD26		0x12
++#define IOCTL_EMB_AD25		0x13
++#define IOCTL_EMB_AD24		0x14
++#define IOCTL_EMB_AD23		0x15
++#define IOCTL_EMB_AD22		0x16
++#define IOCTL_EMB_AD21		0x17
++#define IOCTL_EMB_AD20		0x18
++#define IOCTL_EMB_AD19		0x19
++#define IOCTL_EMB_AD18		0x1a
++#define IOCTL_EMB_AD17		0x1b
++#define IOCTL_EMB_AD16		0x1c
++#define IOCTL_EMB_AD15		0x1d
++#define IOCTL_EMB_AD14		0x1e
++#define IOCTL_EMB_AD13		0x1f
++#define IOCTL_EMB_AD12		0x20
++#define IOCTL_EMB_AD11		0x21
++#define IOCTL_EMB_AD10		0x22
++#define IOCTL_EMB_AD09		0x23
++#define IOCTL_EMB_AD08		0x24
++#define IOCTL_EMB_AD07		0x25
++#define IOCTL_EMB_AD06		0x26
++#define IOCTL_EMB_AD05		0x27
++#define IOCTL_EMB_AD04		0x28
++#define IOCTL_EMB_AD03		0x29
++#define IOCTL_EMB_AD02		0x2a
++#define IOCTL_EMB_AD01		0x2b
++#define IOCTL_EMB_AD00		0x2c
++#define IOCTL_NFC_CE0_B	0x2d
++#define IOCTL_NFC_RB		0x2e
++#define IOCTL_DIU_CLK		0x2f
++#define IOCTL_DIU_DE		0x30
++#define IOCTL_DIU_HSYNC	0x31
++#define IOCTL_DIU_VSYNC	0x32
++#define IOCTL_DIU_LD00		0x33
++#define IOCTL_DIU_LD01		0x34
++#define IOCTL_DIU_LD02		0x35
++#define IOCTL_DIU_LD03		0x36
++#define IOCTL_DIU_LD04		0x37
++#define IOCTL_DIU_LD05		0x38
++#define IOCTL_DIU_LD06		0x39
++#define IOCTL_DIU_LD07		0x3a
++#define IOCTL_DIU_LD08		0x3b
++#define IOCTL_DIU_LD09		0x3c
++#define IOCTL_DIU_LD10		0x3d
++#define IOCTL_DIU_LD11		0x3e
++#define IOCTL_DIU_LD12		0x3f
++#define IOCTL_DIU_LD13		0x40
++#define IOCTL_DIU_LD14		0x41
++#define IOCTL_DIU_LD15		0x42
++#define IOCTL_DIU_LD16		0x43
++#define IOCTL_DIU_LD17		0x44
++#define IOCTL_DIU_LD18		0x45
++#define IOCTL_DIU_LD19		0x46
++#define IOCTL_DIU_LD20		0x47
++#define IOCTL_DIU_LD21		0x48
++#define IOCTL_DIU_LD22		0x49
++#define IOCTL_DIU_LD23		0x4a
++#define IOCTL_I2C2_SCL		0x4b
++#define IOCTL_I2C2_SDA		0x4c
++#define IOCTL_CAN1_TX		0x4d
++#define IOCTL_CAN2_TX		0x4e
++#define IOCTL_I2C1_SCL		0x4f
++#define IOCTL_I2C1_SDA		0x50
++#define IOCTL_FEC1_TXD_2	0x51
++#define IOCTL_FEC1_TXD_3	0x52
++#define IOCTL_FEC1_RXD_2	0x53
++#define IOCTL_FEC1_RXD_3	0x54
++#define IOCTL_FEC1_CRS		0x55
++#define IOCTL_FEC1_TX_ER	0x56
++#define IOCTL_FEC1_RXD_1	0x57
++#define IOCTL_FEC1_TXD_1	0x58
++#define IOCTL_FEC1_MDC		0x59
++#define IOCTL_FEC1_RX_ER	0x5a
++#define IOCTL_FEC1_MDIO	0x5b
++#define IOCTL_FEC1_RXD_0	0x5c
++#define IOCTL_FEC1_TXD_0	0x5d
++#define IOCTL_FEC1_TX_CLK	0x5e
++#define IOCTL_FEC1_RX_CLK	0x5f
++#define IOCTL_FEC1_RX_DV	0x60
++#define IOCTL_FEC1_TX_EN	0x61
++#define IOCTL_FEC1_COL		0x62
++#define IOCTL_USB1_DATA0	0x63
++#define IOCTL_USB1_DATA1	0x64
++#define IOCTL_USB1_DATA2	0x65
++#define IOCTL_USB1_DATA3	0x66
++#define IOCTL_USB1_DATA4	0x67
++#define IOCTL_USB1_DATA5	0x68
++#define IOCTL_USB1_DATA6	0x69
++#define IOCTL_USB1_DATA7	0x6a
++#define IOCTL_USB1_STOP	0x6b
++#define IOCTL_USB1_CLK		0x6c
++#define IOCTL_USB1_NEXT	0x6d
++#define IOCTL_USB1_DIR		0x6e
++#define IOCTL_SDHC1_CLK	0x6f
++#define IOCTL_SDHC1_CMD	0x70
++#define IOCTL_SDHC1_D0		0x71
++#define IOCTL_SDHC1_D1		0x72
++#define IOCTL_SDHC1_D2		0x73
++#define IOCTL_SDHC1_D3		0x74
++#define IOCTL_PSC_MCLK_IN	0x75
++#define IOCTL_PSC0_0		0x76
++#define IOCTL_PSC0_1		0x77
++#define IOCTL_PSC0_2		0x78
++#define IOCTL_PSC0_3		0x79
++#define IOCTL_PSC0_4		0x7a
++#define IOCTL_PSC1_0		0x7b
++#define IOCTL_PSC1_1		0x7c
++#define IOCTL_PSC1_2		0x7d
++#define IOCTL_PSC1_3		0x7e
++#define IOCTL_PSC1_4		0x7f
++#define IOCTL_J1850_TX		0x80
++#define IOCTL_J1850_RX		0x81
++
++#define NFC_CE0			1
++#define NFC_CE1			2
++#define NFC_CE2			4
++#define NFC_CE3			8
++#define NFC_SEL_RB0			1
++#define NFC_SEL_RB1			2
++#define NFC_SEL_RB2			4
++#define NFC_SEL_RB3			8
++
++/******************** IO control fields ************************/
++#define DS_MSR_1			0x00
++#define DS_MSR_2			0x01
++#define DS_MSR_3			0x02
++#define DS_MSR_4			0x03
++#define ST_Disabled			0x00
++#define ST_Enabled			0x04
++#define PAD_FUNC0			0x00
++#define PAD_FUNC1			0x20
++#define PAD_FUNC2			0x40
++#define PAD_FUNC3			0x60
++#define PUD_PUE			0x18
++/**************************************************************/
++
++/* Chip select and rb select Define */
++
++/* NFC PAD Define */
++#define PAD_NFC_IO                	PAD_FUNC0
++#define PAD_NFC_ALE               	PAD_FUNC0
++#define PAD_NFC_CLE               	PAD_FUNC0
++#define PAD_NFC_WE                	PAD_FUNC0
++#define PAD_NFC_RE                	PAD_FUNC0
++#define PAD_NFC_CE0               	PAD_FUNC0
++#define PAD_NFC_CE1               	PAD_FUNC1
++#define PAD_NFC_CE2               	PAD_FUNC2
++#define PAD_NFC_CE3               	PAD_FUNC2
++#define PAD_NFC_RB0               	PAD_FUNC0
++#define PAD_NFC_RB1               	PAD_FUNC2
++#define PAD_NFC_RB2               	PAD_FUNC2
++#define PAD_NFC_RB3               	PAD_FUNC2
++
++/* NFC Control PAD Define */
++#define BALL_NFC_CE0			IOCTL_NFC_CE0_B
++#define BALL_NFC_CE1			IOCTL_SDHC1_CLK
++#define BALL_NFC_CE2			IOCTL_PSC1_4
++#define BALL_NFC_CE3			IOCTL_J1850_TX
++#define BALL_NFC_RB0			IOCTL_NFC_RB
++#define BALL_NFC_RB1			IOCTL_FEC1_TXD_0
++#define BALL_NFC_RB2			IOCTL_PSC1_3
++#define BALL_NFC_RB3			IOCTL_J1850_RX
++#define BALL_NFC_ALE			IOCTL_EMB_AD19
++#define BALL_NFC_CLE			IOCTL_EMB_AD18
++#define BALL_NFC_WE			IOCTL_EMB_AD16
++#define BALL_NFC_RE			IOCTL_EMB_AD17
++
++/* NFC IO Pad Define */
++#define BALL_NFC_IO0			IOCTL_EMB_AD00
++#define BALL_NFC_IO1			IOCTL_EMB_AD01
++#define BALL_NFC_IO2			IOCTL_EMB_AD02
++#define BALL_NFC_IO3			IOCTL_EMB_AD03
++#define BALL_NFC_IO4			IOCTL_EMB_AD04
++#define BALL_NFC_IO5			IOCTL_EMB_AD05
++#define BALL_NFC_IO6			IOCTL_EMB_AD06
++#define BALL_NFC_IO7			IOCTL_EMB_AD07
++
++/* Addresses for NFC MAIN RAM BUFFER areas */
++#define NFC_MAIN_AREA(n)	((n) *  0x1000)
++
++/* Addresses for NFC SPARE BUFFER areas */
++#define NFC_SPARE_BUFFERS		8
++#define NFC_SPARE_LEN			0x10
++#define NFC_SPARE_AREA(n)		(0x800 + NFC_MAIN_AREA(n))
++
++#define PAGE_2K                   	0x0800
++#define PAGE_virtual_2K          0x0840
++#define PAGE_64                   	0x0040
++
++/* MPC5125 NFC registers */
++/* Typical Flash Commands */
++#define READ_PAGE_CMD_CODE		0x7EE0
++#define DMA_READ_PAGE_CMD_CODE		0x7EE0
++#define PROGRAM_PAGE_CMD_CODE		0x7FC0
++#define ERASE_CMD_CODE			0x4EC0
++#define READ_ID_CMD_CODE		0x4804
++#define RESET_CMD_CODE			0x4040
++#define DMA_PROGRAM_PAGE_CMD_CODE	0xFFC0
++#define RANDOM_IN_CMD_CODE		0x7140
++#define RANDOM_OUT_CMD_CODE		0x70E0
++#define STATUS_READ_CMD_CODE		0x4068
++
++#define PAGE_READ_CMD_BYTE1		0x00
++#define PAGE_READ_CMD_BYTE2		0x30
++#define PROGRAM_PAGE_CMD_BYTE1		0x80
++#define PROGRAM_PAGE_CMD_BYTE2		0x10
++#define READ_STATUS_CMD_BYTE		0x70
++#define ERASE_CMD_BYTE1		0x60
++#define ERASE_CMD_BYTE2		0xD0
++#define READ_ID_CMD_BYTE		0x90
++#define RESET_CMD_BYTE			0xFF
++#define RANDOM_OUT_CMD_BYTE1		0x05
++#define RANDOM_OUT_CMD_BYTE2		0xE0
++
++/* NFC ECC mode define */
++#define ECC_BYPASS			0x0
++#define ECC_8_BYTE			0x1
++#define ECC_12_BYTE			0x2
++#define ECC_15_BYTE			0x3
++#define ECC_23_BYTE			0x4
++#define ECC_30_BYTE			0x5
++#define ECC_45_BYTE			0x6
++#define ECC_60_BYTE			0x7
++#define ECC_ERROR			1
++#define ECC_RIGHT			0
++
++/***************** Module-Relative Register Offsets *************************/
++#define NFC_SRAM_BUFFER                0x0000
++#define NFC_FLASH_CMD1 		0x3F00
++#define NFC_FLASH_CMD2			0x3F04
++#define NFC_COL_ADDR			0x3F08
++#define NFC_ROW_ADDR			0x3F0c
++#define NFC_FLASH_COMMAND_REPEAT	0x3F10
++#define NFC_ROW_ADDR_INC		0x3F14
++#define NFC_FLASH_STATUS1		0x3F18
++#define NFC_FLASH_STATUS2		0x3F1c
++#define NFC_DMA1_ADDR			0x3F20
++#define NFC_DMA2_ADDR			0x3F34
++#define NFC_DMA_CONFIG			0x3F24
++#define NFC_CACHE_SWAP			0x3F28
++#define NFC_SECTOR_SIZE		0x3F2c
++#define NFC_FLASH_CONFIG		0x3F30
++#define NFC_IRQ_STATUS			0x3F38
++
++/***************** Module-Relative Register Reset Value *********************/
++#define NFC_SRAM_BUFFER_RSTVAL                	0x00000000
++#define NFC_FLASH_CMD1_RSTVAL 			0x30FF0000
++#define NFC_FLASH_CMD2_RSTVAL			0x007EE000
++#define NFC_COL_ADDR_RSTVAL			0x00000000
++#define NFC_ROW_ADDR_RSTVAL			0x11000000
++#define NFC_FLASH_COMMAND_REPEAT_RSTVAL	0x00000000
++#define NFC_ROW_ADDR_INC_RSTVAL		0x00000001
++#define NFC_FLASH_STATUS1_RSTVAL		0x00000000
++#define NFC_FLASH_STATUS2_RSTVAL		0x00000000
++#define NFC_DMA1_ADDR_RSTVAL			0x00000000
++#define NFC_DMA2_ADDR_RSTVAL			0x00000000
++#define NFC_DMA_CONFIG_RSTVAL			0x00000000
++#define NFC_CACHE_SWAP_RSTVAL			0x0FFE0FFE
++#define NFC_SECTOR_SIZE_RSTVAL			0x00000420
++#define NFC_FLASH_CONFIG_RSTVAL		0x000EA631
++#define NFC_IRQ_STATUS_RSTVAL			0x04000000
++
++/***************** Module-Relative Register Mask *************************/
++
++/* NFC_FLASH_CMD1 Field */
++#define CMD1_MASK				0xFFFF0000
++#define CMD1_SHIFT				0
++#define CMD_BYTE2_MASK    			0xFF000000
++#define CMD_BYTE2_SHIFT   			24
++#define CMD_BYTE3_MASK    			0x00FF0000
++#define CMD_BYTE3_SHIFT   			16
++
++/* NFC_FLASH_CM2 Field */
++#define CMD2_MASK				0xFFFFFF07
++#define CMD2_SHIFT				0
++#define CMD_BYTE1_MASK			    	0xFF000000
++#define CMD_BYTE1_SHIFT   			24
++#define CMD_CODE_MASK				0x00FFFF00
++#define CMD_CODE_SHIFT				8
++#define BUFNO_MASK				0x00000006
++#define BUFNO_SHIFT				1
++#define BUSY_MASK				0x00000001
++#define BUSY_SHIFT				0
++#define START_MASK				0x00000001
++#define START_SHIFT				0
++
++/* NFC_COL_ADDR Field */
++#define COL_ADDR_MASK				0x0000FFFF
++#define COL_ADDR_SHIFT				0
++#define COL_ADDR_COL_ADDR2_MASK		0x0000FF00
++#define COL_ADDR_COL_ADDR2_SHIFT		8
++#define COL_ADDR_COL_ADDR1_MASK		0x000000FF
++#define COL_ADDR_COL_ADDR1_SHIFT		0
++
++/* NFC_ROW_ADDR Field */
++#define ROW_ADDR_MASK				0x00FFFFFF
++#define ROW_ADDR_SHIFT				0
++#define ROW_ADDR_CHIP_SEL_RB_MASK		0xF0000000
++#define ROW_ADDR_CHIP_SEL_RB_SHIFT		28
++#define ROW_ADDR_CHIP_SEL_MASK			0x0F000000
++#define ROW_ADDR_CHIP_SEL_SHIFT		24
++#define ROW_ADDR_ROW_ADDR3_MASK		0x00FF0000
++#define ROW_ADDR_ROW_ADDR3_SHIFT		16
++#define ROW_ADDR_ROW_ADDR2_MASK		0x0000FF00
++#define ROW_ADDR_ROW_ADDR2_SHIFT		8
++#define ROW_ADDR_ROW_ADDR1_MASK		0x000000FF
++#define ROW_ADDR_ROW_ADDR1_SHIFT		0
++
++/* NFC_FLASH_COMMAND_REPEAT Field */
++#define COMMAND_REPEAT_MASK			0x0000FFFF
++#define COMMAND_REPEAT_SHIFT			0
++#define COMMAND_REPEAT_REPEAT_COUNT_MASK	0x0000FFFF
++#define COMMAND_REPEAT_REPEAT_COUNT_SHIFT	0
++
++/* NFC_ROW_ADDR_INC Field */
++#define ROW_ADDR_INC_MASK			0x00FFFFFF
++#define ROW_ADDR_INC_SHIFT			0
++#define ROW_ADDR_INC_ROW_ADDR3_INC_MASK	0x00FF0000
++#define ROW_ADDR_INC_ROW_ADDR3_INC_SHIFT	16
++#define ROW_ADDR_INC_ROW_ADDR2_INC_MASK	0x0000FF00
++#define ROW_ADDR_INC_ROW_ADDR2_INC_SHIFT	8
++#define ROW_ADDR_INC_ROW_ADDR1_INC_MASK	0x000000FF
++#define ROW_ADDR_INC_ROW_ADDR1_INC_SHIFT	0
++
++/* NFC_FLASH_STATUS1 Field */
++#define STATUS1_MASK				0xFFFFFFFF
++#define STATUS1_SHIFT				0
++#define STATUS1_ID_BYTE1_MASK			0xFF000000
++#define STATUS1_ID_BYTE1_SHIFT			24
++#define STATUS1_ID_BYTE2_MASK			0x00FF0000
++#define STATUS1_ID_BYTE2_SHIFT			16
++#define STATUS1_ID_BYTE3_MASK			0x0000FF00
++#define STATUS1_ID_BYTE3_SHIFT			8
++#define STATUS1_ID_BYTE4_MASK			0x000000FF
++#define STATUS1_ID_BYTE4_SHIFT			0
++
++/* NFC_FLASH_STATUS2 Field */
++#define STATUS2_MASK				0xFF0000FF
++#define STATUS2_SHIFT				0
++#define STATUS2_ID_BYTE5_MASK			0xFF000000
++#define STATUS2_ID_BYTE5_SHIFT			24
++#define STATUS_BYTE1_MASK			0x000000FF
++#define STATUS2_STATUS_BYTE1_SHIFT		0
++
++/* NFC_DMA1_ADDR Field */
++#define DMA1_ADDR_MASK				0xFFFFFFFF
++#define DMA1_ADDR_SHIFT			0
++#define DMA1_ADDR_DMA1_ADDR_MASK		0xFFFFFFFF
++#define DMA1_ADDR_DMA1_ADDR_SHIFT		0
++
++/* DMA2_ADDR Field */
++#define DMA2_ADDR_MASK				0xFFFFFFFF
++#define DMA2_ADDR_SHIFT			0
++#define DMA2_ADDR_DMA2_ADDR_MASK		0xFFFFFFFF
++#define DMA2_ADDR_DMA2_ADDR_SHIFT		0
++
++/* DMA_CONFIG Field */
++#define DMA_CONFIG_MASK			0xFFFFFFFF
++#define DMA_CONFIG_SHIFT			0
++#define DMA_CONFIG_DMA1_CNT_MASK		0xFFF00000
++#define DMA_CONFIG_DMA1_CNT_SHIFT		20
++#define DMA_CONFIG_DMA2_CNT_MASK		0x000FE000
++#define DMA_CONFIG_DMA2_CNT_SHIFT		13
++#define DMA_CONFIG_DMA2_OFFSET_MASK		0x00001FC0
++#define DMA_CONFIG_DMA2_OFFSET_SHIFT		2
++#define DMA_CONFIG_DMA1_ACT_MASK		0x00000002
++#define DMA_CONFIG_DMA1_ACT_SHIFT		1
++#define DMA_CONFIG_DMA2_ACT_MASK		0x00000001
++#define DMA_CONFIG_DMA2_ACT_SHIFT		0
++
++/* NFC_CACHE_SWAP Field */
++#define CACHE_SWAP_MASK			0x0FFE0FFE
++#define CACHE_SWAP_SHIFT			1
++#define CACHE_SWAP_CACHE_SWAP_ADDR2_MASK	0x0FFE0000
++#define CACHE_SWAP_CACHE_SWAP_ADDR2_SHIFT	17
++#define CACHE_SWAP_CACHE_SWAP_ADDR1_MASK	0x00000FFE
++#define CACHE_SWAP_CACHE_SWAP_ADDR1_SHIFT	1
++
++/* NFC_SECTOR_SIZE Field */
++#define SECTOR_SIZE_MASK			0x00001FFF
++#define SECTOR_SIZE_SHIFT			0
++#define SECTOR_SIZE_SECTOR_SIZE_MASK		0x00001FFF
++#define SECTOR_SIZE_SECTOR_SIZE_SHIFT		0
++
++/* NFC_FLASH_CONFIG Field */
++#define CONFIG_MASK				0xFFFFFFFF
++#define CONFIG_SHIFT				0
++#define CONFIG_STOP_ON_WERR_MASK		0x80000000
++#define CONFIG_STOP_ON_WERR_SHIFT		31
++#define CONFIG_ECC_SRAM_ADDR_MASK		0x7FC00000
++#define CONFIG_ECC_SRAM_ADDR_SHIFT		22
++#define CONFIG_ECC_SRAM_REQ_MASK		0x00200000
++#define CONFIG_ECC_SRAM_REQ_SHIFT		21
++#define CONFIG_DMA_REQ_MASK			0x00100000
++#define CONFIG_DMA_REQ_SHIFT			20
++#define CONFIG_ECC_MODE_MASK			0x000E0000
++#define CONFIG_ECC_MODE_SHIFT			17
++#define CONFIG_FAST_FLASH_MASK			0x00010000
++#define CONFIG_FAST_FLASH_SHIFT		16
++#define CONFIG_ID_COUNT_MASK			0x0000E000
++#define CONFIG_ID_COUNT_SHIFT			13
++#define CONFIG_CMD_TIMEOUT_MASK		0x00001F00
++#define CONFIG_CMD_TIMEOUT_SHIFT		8
++#define CONFIG_16BIT_MASK			0x00000080
++#define CONFIG_16BIT_SHIFT			7
++#define CONFIG_BOOT_MODE_MASK			0x00000040
++#define CONFIG_BOOT_MODE_SHIFT			6
++#define CONFIG_ADDR_AUTO_INCR_MASK		0x00000020
++#define CONFIG_ADDR_AUTO_INCR_SHIFT		5
++#define CONFIG_BUFNO_AUTO_INCR_MASK		0x00000010
++#define CONFIG_BUFNO_AUTO_INCR_SHIFT		4
++#define CONFIG_PAGE_CNT_MASK			0x0000000F
++#define CONFIG_PAGE_CNT_SHIFT			0
++
++/* NFC_IRQ_STATUS Field */
++#define MASK					0xEFFC003F
++#define SHIFT					0
++#define WERR_IRQ_MASK				0x80000000
++#define WERR_IRQ_SHIFT				31
++#define CMD_DONE_IRQ_MASK			0x40000000
++#define CMD_DONE_IRQ_SHIFT			30
++#define IDLE_IRQ_MASK				0x20000000
++#define IDLE_IRQ_SHIFT				29
++#define WERR_STATUS_MASK			0x08000000
++#define WERR_STATUS_SHIFT			27
++#define FLASH_CMD_BUSY_MASK			0x04000000
++#define FLASH_CMD_BUSY_SHIFT			26
++#define RESIDUE_BUSY_MASK			0x02000000
++#define RESIDUE_BUSY_SHIFT			25
++#define ECC_BUSY_MASK				0x01000000
++#define ECC_BUSY_SHIFT				24
++#define DMA_BUSY_MASK				0x00800000
++#define DMA_BUSY_SHIFT				23
++#define WERR_EN_MASK				0x00400000
++#define WERR_EN_SHIFT				22
++#define CMD_DONE_EN_MASK			0x00200000
++#define CMD_DONE_EN_SHIFT			21
++#define IDLE_EN_MASK				0x00100000
++#define IDLE_EN_SHIFT				20
++#define WERR_CLEAR_MASK			0x00080000
++#define WERR_CLEAR_SHIFT			19
++#define CMD_DONE_CLEAR_MASK			0x00040000
++#define CMD_DONE_CLEAR_SHIFT			18
++#define IDLE_CLEAR_MASK			0x00020000
++#define IDLE_CLEAR_SHIFT			17
++#define RESIDUE_BUFF_NO_MASK			0x00000030
++#define RESIDUE_BUFF_NO_SHIFT			4
++#define ECC_BUFF_NO_MASK			0x000000C0
++#define ECC_BUFF_NO_SHIFT			2
++#define DMA_BUFF_NO_MASK			0x00000003
++
++#endif /* MPC5125_NFC_H */
++
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/mpc512x.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/mpc512x.h
+--- linux-2.6.29/arch/powerpc/include/asm/mpc512x.h	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/mpc512x.h	2010-04-13 20:23:26.000000000 +0200
+@@ -16,7 +16,114 @@
+ #ifndef __ASM_POWERPC_MPC512x_H__
+ #define __ASM_POWERPC_MPC512x_H__
+ 
++/*
++ * DDR Memory Controller Memory Map
++ */
++struct ddr512x {
++	u32 ddr_sys_config;	/* System Configuration Register */
++	u32 ddr_time_config0;	/* Timing Configuration Register */
++	u32 ddr_time_config1;	/* Timing Configuration Register */
++	u32 ddr_time_config2;	/* Timing Configuration Register */
++	u32 ddr_command;	/* Command Register */
++	u32 ddr_compact_command;	/* Compact Command Register */
++	u16 pad_0;		/* Padding for Self Refresh Command Register 0 */
++	u16 self_refresh_cmd_0;	/* Enter/Exit Self Refresh Registers */
++	u16 pad_1;		/* Padding for Self Refresh Command Register 1 */
++	u16 self_refresh_cmd_1;	/* Enter/Exit Self Refresh Registers */
++	u16 pad_2;		/* Padding for Self Refresh Command Register 2 */
++	u16 self_refresh_cmd_2;	/* Enter/Exit Self Refresh Registers */
++	u16 pad_3;		/* Padding for Self Refresh Command Register 3 */
++	u16 self_refresh_cmd_3;	/* Enter/Exit Self Refresh Registers */
++	u16 pad_4;		/* Padding for Self Refresh Command Register 4 */
++	u16 self_refresh_cmd_4;	/* Enter/Exit Self Refresh Registers */
++	u16 pad_5;		/* Padding for Self Refresh Command Register 5 */
++	u16 self_refresh_cmd_5;	/* Enter/Exit Self Refresh Registers */
++	u16 pad_6;		/* Padding for Self Refresh Command Register 6 */
++	u16 self_refresh_cmd_6;	/* Enter/Exit Self Refresh Registers */
++	u16 pad_7;		/* Padding for Self Refresh Command Register 7 */
++	u16 self_refresh_cmd_7;	/* Enter/Exit Self Refresh Registers */
++	u32 DQS_config_offset_count;	/* DQS Config Offset Count */
++	u32 DQS_config_offset_time;	/* DQS Config Offset Time */
++	u32 DQS_delay_status;	/* DQS Delay Status */
++	u32 res0[0xF];
++	u32 prioman_config1;	/* Priority Manager Configuration */
++	u32 prioman_config2;	/* Priority Manager Configuration */
++	u32 hiprio_config;	/* High Priority Configuration */
++	u32 lut_table0_main_upper;	/* LUT0 Main Upper */
++	u32 lut_table1_main_upper;	/* LUT1 Main Upper */
++	u32 lut_table2_main_upper;	/* LUT2 Main Upper */
++	u32 lut_table3_main_upper;	/* LUT3 Main Upper */
++	u32 lut_table4_main_upper;	/* LUT4 Main Upper */
++	u32 lut_table0_main_lower;	/* LUT0 Main Lower */
++	u32 lut_table1_main_lower;	/* LUT1 Main Lower */
++	u32 lut_table2_main_lower;	/* LUT2 Main Lower */
++	u32 lut_table3_main_lower;	/* LUT3 Main Lower */
++	u32 lut_table4_main_lower;	/* LUT4 Main Lower */
++	u32 lut_table0_alternate_upper;	/* LUT0 Alternate Upper */
++	u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
++	u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
++	u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
++	u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
++	u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
++	u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
++	u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
++	u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
++	u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
++	u32 performance_monitor_config;
++	u32 event_time_counter;
++	u32 event_time_preset;
++	u32 performance_monitor1_address_low;
++	u32 performance_monitor2_address_low;
++	u32 performance_monitor1_address_hi;
++	u32 performance_monitor2_address_hi;
++	u32 res1[2];
++	u32 performance_monitor1_read_counter;
++	u32 performance_monitor2_read_counter;
++	u32 performance_monitor1_write_counter;
++	u32 performance_monitor2_write_counter;
++	u32 granted_ack_counter0;
++	u32 granted_ack_counter1;
++	u32 granted_ack_counter2;
++	u32 granted_ack_counter3;
++	u32 granted_ack_counter4;
++	u32 cumulative_wait_counter0;
++	u32 cumulative_wait_counter1;
++	u32 cumulative_wait_counter2;
++	u32 cumulative_wait_counter3;
++	u32 cumulative_wait_counter4;
++	u32 summed_priority_counter0;
++	u32 summed_priority_counter1;
++	u32 summed_priority_counter2;
++	u32 summed_priority_counter3;
++	u32 summed_priority_counter4;
++	u32 res2[0x3AD];
++};
++
++#define MPC512x_DDR_BASE	0x9000	/* Offset of DRAM controller */
++
++struct clk;
++
+ extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
++extern struct clk *clk_get(struct device *dev, const char *id);
++extern int clk_enable(struct clk *clk);
++
++
++/*
++ * helper routines for switching psc pins to gpios and back
++ * and driving them high or low
++ */
++extern void mpc5121_pscgpio_make_gpio(int psc, int pin);
++extern void mpc5121_pscgpio_pin_high(int psc, int pin);
++extern void mpc5121_pscgpio_pin_low(int psc, int pin);
++extern void mpc5121_pscgpio_make_psc(int psc, int pin);
++#ifdef CONFIG_PPC_MPC5125
++extern void mpc5125_psc_io_controller_set(int psc, int pin,unsigned char value);
++extern void mpc5125_io_controller_set(int offset,unsigned char value);
++extern void mpc5121_pscgpio_make_psc_pull_up(int psc, int pin);
++#endif
++#ifdef CONFIG_PM
++extern int __init mpc512x_pm_init(void);
++#endif
+ 
+ #endif /* __ASM_POWERPC_MPC512x_H__ */
+ 
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/mpc52xx_psc.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/mpc52xx_psc.h
+--- linux-2.6.29/arch/powerpc/include/asm/mpc52xx_psc.h	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/mpc52xx_psc.h	2010-04-13 20:23:26.000000000 +0200
+@@ -134,6 +134,51 @@
+ 
+ /* Structure of the hardware registers */
+ struct mpc52xx_psc {
++#ifdef CONFIG_PPC_MPC5125
++	u8		mr1;		/* PSC + 0x00 */
++	u8		reserved0[3];
++	u8		mr2;		/* PSC + 0x04 */
++	u8		reserved1[3];
++	u16		mpc52xx_psc_status; /* PSC + 0x08 */
++	u8		reserved2[2];
++	u8		mpc52xx_psc_clock_select; /* PSC + 0x0c */
++	u8		reserved3[3];
++	u8		command;	/* PSC + 0x10 */
++	u8		reserved4[3];
++	union {				/* PSC + 0x14 */
++		u8	buffer_8;
++		u16	buffer_16;
++		u32	buffer_32;
++	} buffer;
++#define mpc52xx_psc_buffer_8	buffer.buffer_8
++#define mpc52xx_psc_buffer_16	buffer.buffer_16
++#define mpc52xx_psc_buffer_32	buffer.buffer_32
++	u8		mpc52xx_psc_ipcr;	/* PSC + 0x18 */
++	u8		reserved5[3];
++	u8		mpc52xx_psc_acr;	/* PSC + 0x1c */
++	u8		reserved6[3];
++	u16		mpc52xx_psc_isr;	/* PSC + 0x20 */
++	u8		reserved7[2];
++	u16		mpc52xx_psc_imr;	/* PSC + 0x24 */
++	u8		reserved8[2];
++	u8		ctur;			/* PSC + 0x28 */
++	u8		reserved9[3];
++	u8		ctlr;			/* PSC + 0x2c */
++	u8		reserved10[3];
++	u32             ccr;            	/* PSC + 0x30 */
++	u32             ac97slots;      	/* PSC + 0x34 */
++	u32             ac97cmd;        	/* PSC + 0x38 */
++	u32             ac97data;       	/* PSC + 0x3c */
++	u8		reserved11[4];
++	u8		ip;			/* PSC + 0x44 */
++	u8		reserved12[3];
++	u8		op1;			/* PSC + 0x48 */
++	u8		reserved13[3];
++	u8		op0;			/* PSC + 0x4c */
++	u8		reserved14[3];
++	u32		sicr;			/* PSC + 0x50 */
++	u8		reserved15[4];
++#else
+ 	u8		mode;		/* PSC + 0x00 */
+ 	u8		reserved0[3];
+ 	union {				/* PSC + 0x04 */
+@@ -171,12 +216,15 @@
+ 	u8		reserved5[3];
+ 	u8		ctlr;		/* PSC + 0x1c */
+ 	u8		reserved6[3];
+-	/* BitClkDiv field of CCR is byte swapped in
+-	 * the hardware for mpc5200/b compatibility */
+-	u32		ccr;		/* PSC + 0x20 */
+-	u32		ac97_slots;	/* PSC + 0x24 */
+-	u32		ac97_cmd;	/* PSC + 0x28 */
+-	u32		ac97_data;	/* PSC + 0x2c */
++#ifdef CONFIG_PPC_MPC5121
++	u32             ccr;            /* PSC + 0x20 */
++	u32             ac97slots;      /* PSC + 0x24 */
++	u32             ac97cmd;        /* PSC + 0x28 */
++	u32             ac97data;       /* PSC + 0x2c */
++#else
++	u16		ccr;		/* PSC + 0x20 */
++	u8		reserved7[14];
++#endif
+ 	u8		ivr;		/* PSC + 0x30 */
+ 	u8		reserved8[3];
+ 	u8		ip;		/* PSC + 0x34 */
+@@ -196,6 +244,7 @@
+ 	u8		reserved16[3];
+ 	u8		irfdr;		/* PSC + 0x54 */
+ 	u8		reserved17[3];
++#endif
+ };
+ 
+ struct mpc52xx_psc_fifo {
+@@ -233,16 +282,19 @@
+ 	u16		tflwfptr;	/* PSC + 0x9e */
+ };
+ 
+-#define MPC512x_PSC_FIFO_RESET_SLICE	0x80
+-#define MPC512x_PSC_FIFO_ENABLE_SLICE	0x01
+-#define MPC512x_PSC_FIFO_ENABLE_DMA	0x04
++#define MPC512x_PSC_FIFO_EOF		0x100
++#define MPC512x_PSC_FIFO_RESET_SLICE	0x080
++#define MPC512x_PSC_FIFO_ENABLE_AXE	0x008
++#define MPC512x_PSC_FIFO_ENABLE_DMA	0x004
++#define MPC512x_PSC_FIFO_ENABLE_SLICE	0x001
+ 
+ #define MPC512x_PSC_FIFO_EMPTY		0x1
+ #define MPC512x_PSC_FIFO_FULL		0x2
+ #define MPC512x_PSC_FIFO_ALARM		0x4
+ #define MPC512x_PSC_FIFO_URERR		0x8
+-#define MPC512x_PSC_FIFO_ORERR		0x01
+-#define MPC512x_PSC_FIFO_MEMERROR	0x02
++#define MPC512x_PSC_FIFO_ORERR		0x10
++#define MPC512x_PSC_FIFO_DATARDY	0x20
++#define MPC512x_PSC_FIFO_MEMERROR	0x40
+ 
+ struct mpc512x_psc_fifo {
+ 	u32		reserved1[10];
+@@ -282,4 +334,7 @@
+ #define rxdata_32 rxdata.rxdata_32
+ };
+ 
++/* extract and scale size field in txsz or rxsz */
++#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2)
++
+ #endif  /* __ASM_MPC52xx_PSC_H__ */
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/of_platform.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/of_platform.h
+--- linux-2.6.29/arch/powerpc/include/asm/of_platform.h	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/of_platform.h	2010-04-13 20:23:26.000000000 +0200
+@@ -11,6 +11,9 @@
+  *
+  */
+ 
++/* This is just here during the transition */
++#include <linux/of_platform.h>
++
+ /* Platform drivers register/unregister */
+ static inline int of_register_platform_driver(struct of_platform_driver *drv)
+ {
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/systbl.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/systbl.h
+--- linux-2.6.29/arch/powerpc/include/asm/systbl.h	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/systbl.h	2010-04-13 20:23:26.000000000 +0200
+@@ -322,3 +322,4 @@
+ SYSCALL_SPU(dup3)
+ SYSCALL_SPU(pipe2)
+ SYSCALL(inotify_init1)
++SYSCALL(mtc_system_call)
+\ Kein Zeilenumbruch am Dateiende.
+diff -Naur linux-2.6.29/arch/powerpc/include/asm/unistd.h linux-2.6.29-v2010041601/arch/powerpc/include/asm/unistd.h
+--- linux-2.6.29/arch/powerpc/include/asm/unistd.h	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/include/asm/unistd.h	2010-04-13 20:23:26.000000000 +0200
+@@ -341,10 +341,11 @@
+ #define __NR_dup3		316
+ #define __NR_pipe2		317
+ #define __NR_inotify_init1	318
++#define __NR_mtc_system_call	319
+ 
+ #ifdef __KERNEL__
+ 
+-#define __NR_syscalls		319
++#define __NR_syscalls		320
+ 
+ #define __NR__exit __NR_exit
+ #define NR_syscalls	__NR_syscalls
+diff -Naur linux-2.6.29/arch/powerpc/Kconfig linux-2.6.29-v2010041601/arch/powerpc/Kconfig
+--- linux-2.6.29/arch/powerpc/Kconfig	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/Kconfig	2010-04-13 20:23:26.000000000 +0200
+@@ -199,14 +199,6 @@
+ 	depends on BROKEN || (PPC_PMAC64 && EXPERIMENTAL)
+ 	default y
+ 
+-config ARCH_HIBERNATION_POSSIBLE
+-	bool
+-	depends on (PPC64 && HIBERNATE_64) || (PPC32 && HIBERNATE_32)
+-	default y
+-
+-config ARCH_SUSPEND_POSSIBLE
+-	def_bool y
+-	depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx
+ 
+ config PPC_DCR_NATIVE
+ 	bool
+@@ -234,12 +226,22 @@
+ source "arch/powerpc/sysdev/Kconfig"
+ source "arch/powerpc/platforms/Kconfig"
+ 
++
++
+ menu "Kernel options"
+ 
+ config HIGHMEM
+ 	bool "High memory support"
+ 	depends on PPC32
++config ARCH_HIBERNATION_POSSIBLE
++	bool "hibernation possible"
++	depends on (PPC64 && HIBERNATE_64) || (PPC32 && HIBERNATE_32) || PPC32
++	default y
+ 
++config ARCH_SUSPEND_POSSIBLE
++	bool "arch suspend possible"
++	depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || PPC32
++	default y
+ source kernel/time/Kconfig
+ source kernel/Kconfig.hz
+ source kernel/Kconfig.preempt
+@@ -729,6 +731,28 @@
+ config LOWMEM_SIZE
+ 	hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL
+ 	default "0x30000000"
++config AXEMBX_RESERVE_BOOL
++	bool "Reserved memory for AXE and/or MBX driver"
++	depends on ADVANCED_OPTIONS
++	help
++	  This option allows you to reserve a range of memory for the AXE driver
++	  this is useful for guaranteeing that the AXE driver gets memory under 16M
++	  and for reserving a contiguous region for MBX frame buffers
++
++	  Say N here unless you know what you are doing.
++
++config AXEMBX_RESERVE_START
++	hex "Start of reserved AXE and MBX driver memory in bytes" if AXEMBX_RESERVE_BOOL
++	default "0x00400000"
++
++config AXE_RESERVE_SIZE
++	hex "Size of reserved AXE driver memory in bytes" if AXEMBX_RESERVE_BOOL
++	default "0x00100000"
++
++config MBX_RESERVE_SIZE
++	hex "Size of reserved MBX driver memory in bytes" if AXEMBX_RESERVE_BOOL
++	default "0x04000000"
++
+ 
+ config RELOCATABLE
+ 	bool "Build a relocatable kernel (EXPERIMENTAL)"
+diff -Naur linux-2.6.29/arch/powerpc/kernel/clock.c linux-2.6.29-v2010041601/arch/powerpc/kernel/clock.c
+--- linux-2.6.29/arch/powerpc/kernel/clock.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/kernel/clock.c	2010-04-13 20:23:26.000000000 +0200
+@@ -8,7 +8,7 @@
+ #include <linux/errno.h>
+ #include <linux/module.h>
+ #include <asm/clk_interface.h>
+-
++#ifndef CONFIG_MPC5125_TWR
+ struct clk_interface clk_functions;
+ 
+ struct clk *clk_get(struct device *dev, const char *id)
+@@ -80,3 +80,4 @@
+ 	return -ENOSYS;
+ }
+ EXPORT_SYMBOL(clk_set_parent);
++#endif
+diff -Naur linux-2.6.29/arch/powerpc/kernel/head_32.S linux-2.6.29-v2010041601/arch/powerpc/kernel/head_32.S
+--- linux-2.6.29/arch/powerpc/kernel/head_32.S	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/kernel/head_32.S	2010-04-13 20:23:26.000000000 +0200
+@@ -554,6 +554,11 @@
+  * r2:	ptr to linux-style pte
+  * r3:	scratch
+  */
++
++#ifdef CONFIG_PPC_MPC512x
++	b bugfix5121
++bugreturn5121:
++#endif
+ 	mfctr	r0
+ 	/* Get PTE (linux-style) and check access */
+ 	mfspr	r3,SPRN_DMISS
+@@ -629,6 +634,29 @@
+  * r2:	ptr to linux-style pte
+  * r3:	scratch
+  */
++#ifdef CONFIG_PPC_MPC512x
++/* MPC512x: workaround for errata in die M36P and earlier:
++* Implement LRW for TLB way.
++*/
++	mfspr r3,SPRN_DMISS
++	rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */
++	lis r2,lrw@ha /* Search index in lrw[] */
++	addi r2,r2,lrw@l
++	tophys(r2,r2)
++	lwzx r1,r3,r2 /* Get item from lrw[] */
++	cmpwi 0,r1,0 /* Was it way 0 last time? */ 
++	beq- 0,113f /* Then goto 113: */
++	mfspr r1,SPRN_SRR1
++	rlwinm r1,r1,0,15,13 /* Mask out SRR1[WAY] */
++	mtspr SPRN_SRR1,r1
++	li r0,0
++	stwx r0,r3,r2 /* Make lrw[] entry 0 */
++	b 114f
++113:
++	li r0,1
++	stwx r0,r3,r2 /* Make lrw[] entry 1 */
++114:
++#endif
+ 	mfctr	r0
+ 	/* Get PTE (linux-style) and check access */
+ 	mfspr	r3,SPRN_DMISS
+@@ -819,6 +847,33 @@
+ 	blr
+ #endif /* CONFIG_ALTIVEC */
+ 
++#ifdef CONFIG_PPC_MPC512x
++bugfix5121:
++/* MPC512x: workaround for errata in die M36P and earlier:
++* Implement LRW for TLB way.
++*/
++	mfspr r3,SPRN_DMISS
++	rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */
++	lis r2,lrw@ha /* Search index in lrw[] */
++	addi r2,r2,lrw@l
++	tophys(r2,r2)
++	lwzx r1,r3,r2 /* Get item from lrw[] */
++	cmpwi 0,r1,0 /* Was it way 0 last time? */ 
++	beq- 0,113f /* Then goto 113: */
++	mfspr r1,SPRN_SRR1
++	rlwinm r1,r1,0,15,13 /* Mask out SRR1[WAY] */
++	mtspr SPRN_SRR1,r1
++	li r0,0
++	stwx r0,r3,r2 /* Make lrw[] entry 0 */
++	b 114f
++113:
++	li r0,1
++	stwx r0,r3,r2 /* Make lrw[] entry 1 */
++114:
++	b bugreturn5121
++#endif
++
++
+ /*
+  * This code is jumped to from the startup code to copy
+  * the kernel image to physical address PHYSICAL_START.
+@@ -1334,6 +1389,12 @@
+ 	.long 0, 0, 0, 0, 0, 0, 0, 0
+ 	.long 0, 0, 0, 0, 0, 0, 0, 0
+ 
++lrw: 
++       .long 0, 0, 0, 0, 0, 0, 0, 0 
++       .long 0, 0, 0, 0, 0, 0, 0, 0 
++       .long 0, 0, 0, 0, 0, 0, 0, 0 
++       .long 0, 0, 0, 0, 0, 0, 0, 0 
++
+ /* Room for two PTE pointers, usually the kernel and current user pointers
+  * to their respective root page table.
+  */
+diff -Naur linux-2.6.29/arch/powerpc/kernel/prom.c linux-2.6.29-v2010041601/arch/powerpc/kernel/prom.c
+--- linux-2.6.29/arch/powerpc/kernel/prom.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/kernel/prom.c	2010-04-13 20:23:26.000000000 +0200
+@@ -1023,6 +1023,31 @@
+ 	return 0;
+ }
+ 
++#ifdef CONFIG_AXEMBX_RESERVE_BOOL
++unsigned long axemem[2] = {
++	CONFIG_AXEMBX_RESERVE_START,
++	CONFIG_AXE_RESERVE_SIZE
++};
++
++unsigned long *get_axe_mem(void)
++{
++	return axemem;
++}
++EXPORT_SYMBOL(get_axe_mem);
++
++unsigned long mbxmem[2] = {
++	CONFIG_AXEMBX_RESERVE_START+CONFIG_AXE_RESERVE_SIZE,
++	CONFIG_MBX_RESERVE_SIZE
++};
++
++unsigned long *get_mbx_mem(void)
++{
++	return mbxmem;
++}
++EXPORT_SYMBOL(get_mbx_mem);
++#endif
++
++
+ static void __init early_reserve_mem(void)
+ {
+ 	u64 base, size;
+@@ -1038,6 +1063,12 @@
+ 	self_size = initial_boot_params->totalsize;
+ 	lmb_reserve(self_base, self_size);
+ 
++#ifdef CONFIG_AXEMBX_RESERVE_BOOL
++	lmb_reserve(CONFIG_AXEMBX_RESERVE_START,
++		CONFIG_AXE_RESERVE_SIZE +
++		CONFIG_MBX_RESERVE_SIZE);
++#endif
++
+ #ifdef CONFIG_BLK_DEV_INITRD
+ 	/* then reserve the initrd, if any */
+ 	if (initrd_start && (initrd_end > initrd_start))
+diff -Naur linux-2.6.29/arch/powerpc/kernel/setup-common.c linux-2.6.29-v2010041601/arch/powerpc/kernel/setup-common.c
+--- linux-2.6.29/arch/powerpc/kernel/setup-common.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/kernel/setup-common.c	2010-04-13 20:23:26.000000000 +0200
+@@ -105,7 +105,25 @@
+ 	if (ppc_md.machine_shutdown)
+ 		ppc_md.machine_shutdown();
+ }
+-
++struct mpc5121_reset_reg{
++	unsigned int con_low;
++	unsigned int con_hight;
++	unsigned int reserved[2];
++	unsigned int reset_stat;
++	unsigned int reset_mode;
++	unsigned int reset_protect;
++	unsigned int reset_control;
++	unsigned int reset_enable;
++};
++void machine_restart_hardware(void)
++{
++	volatile struct mpc5121_reset_reg *reset=ioremap(0x80000e00,0x100);
++	
++	reset->reset_enable=0x01;
++	reset->reset_protect=0x52535445;
++	while(!(reset->reset_enable&0x01));
++	reset->reset_control=0x3;
++}
+ void machine_restart(char *cmd)
+ {
+ 	machine_shutdown();
+@@ -115,6 +133,9 @@
+ 	smp_send_stop();
+ #endif
+ 	printk(KERN_EMERG "System Halted, OK to turn off power\n");
++	
++	machine_restart_hardware();
++	printk(KERN_EMERG "%s line:%d\n",__func__,__LINE__);
+ 	local_irq_disable();
+ 	while (1) ;
+ }
+diff -Naur linux-2.6.29/arch/powerpc/mm/pgtable_32.c linux-2.6.29-v2010041601/arch/powerpc/mm/pgtable_32.c
+--- linux-2.6.29/arch/powerpc/mm/pgtable_32.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/mm/pgtable_32.c	2010-04-13 20:23:26.000000000 +0200
+@@ -147,6 +147,8 @@
+ }
+ EXPORT_SYMBOL(ioremap_flags);
+ 
++#define ALLOW_RAM_REMAP_FOR_MBX
++
+ void __iomem *
+ __ioremap(phys_addr_t addr, unsigned long size, unsigned long flags)
+ {
+@@ -178,6 +180,8 @@
+ 	if (p < 16*1024*1024)
+ 		p += _ISA_MEM_BASE;
+ 
++#ifndef ALLOW_RAM_REMAP_FOR_MBX
++
+ #ifndef CONFIG_CRASH_DUMP
+ 	/*
+ 	 * Don't allow anybody to remap normal RAM that we're using.
+@@ -189,6 +193,7 @@
+ 		return NULL;
+ 	}
+ #endif
++#endif
+ 
+ 	if (size == 0)
+ 		return NULL;
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/ads5121_pm.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/ads5121_pm.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/ads5121_pm.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/ads5121_pm.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,430 @@
++/*
++ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Description:
++ * This file implements power management for the ADS5121
++ *
++ * This file is part of the Linux kernel
++ *
++ * This is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/suspend.h>
++#include <linux/of_platform.h>
++#include <asm/time.h>
++#include <asm/mpc512x.h>
++#include <asm/ipic.h>
++#include <asm/reg.h>
++#include <sysdev/fsl_soc.h>
++#include "mpc512x_pm.h"
++
++static struct mpc512x_pm ads5121_pm_data;
++static struct ads5121_hib_regs *ads5121_save_ptr;
++
++/* Array to store the SRAM contents */
++static char saved_sram[256 * 1024];
++static u32 ads5121_targeted_state = MPC512x_PM_NONE;
++static u32 ads5121_set_rtc_alarm(void);
++#ifdef CONFIG_MPC5121_ADS_HIB
++int fsl_deep_sleep(void)
++{
++	return ads5121_targeted_state;
++}
++#endif
++/*
++ * Name       : ads5121_save_regs
++ * Desc       : This function is called to store the Peripheral registers
++ *		which dont have drivers associated with it to store it back.
++ *
++ * Parameters : sram - Pointer of a Mapped Memory Location.
++ * Return     : void
++ */
++static int ads5121_save_regs(u32 *sram)
++{
++	u32 *reg_ptr;
++	ads5121_save_ptr = kmalloc(sizeof(struct ads5121_hib_regs), GFP_KERNEL);
++
++	if (!ads5121_save_ptr)
++		return -1;
++
++	reg_ptr = (u32 *)((u32)ads5121_pm_data.mbar +
++						MPC512x_IMMRBAR_IPIC_OFFSET);
++	_memcpy_fromio(ads5121_save_ptr->ipic_regs, reg_ptr,
++					sizeof(ads5121_save_ptr->ipic_regs));
++
++	reg_ptr = (u32 *)((u32)ads5121_pm_data.mbar +
++						MPC512x_IMMRBAR_CLK_OFFSET);
++	_memcpy_fromio(ads5121_save_ptr->clk_regs, reg_ptr,
++					sizeof(ads5121_save_ptr->clk_regs));
++
++	reg_ptr = (u32 *)((u32)ads5121_pm_data.mbar +
++						MPC512x_IMMRBAR_GPT_OFFSET);
++	_memcpy_fromio(ads5121_save_ptr->gpt_regs, reg_ptr,
++					sizeof(ads5121_save_ptr->gpt_regs));
++
++	reg_ptr = (u32 *)((u32)ads5121_pm_data.mbar +
++						MPC512x_IMMRBAR_GPIO_OFFSET);
++	_memcpy_fromio(ads5121_save_ptr->gpio_regs, reg_ptr,
++					sizeof(ads5121_save_ptr->gpio_regs));
++
++	memcpy(saved_sram, sram, sizeof(saved_sram));
++	return 0;
++}
++
++/*
++ * Name       : ads5121_restore_regs
++ * Desc       : This function is called to restore the Peripheral registers
++ *		which dont have drivers associated with it to restore it back.
++ *
++ * Parameters : sram - Pointer of a Mapped Memory Location.
++ * Return     : void
++ */
++static void ads5121_restore_regs(u32 *sram)
++{
++	u32 *reg_ptr;
++
++	/* Disable here explicitly, needs not enable since the interrrups
++	 * would be enabled latter on the suspend_enter function
++	 * in the kernel/power/main.c
++	 */
++	local_irq_disable();
++
++	memcpy(sram, saved_sram, sizeof(saved_sram));
++
++	reg_ptr = (u32 *)((u32)ads5121_pm_data.mbar +
++					MPC512x_IMMRBAR_IPIC_OFFSET);
++	_memcpy_toio(reg_ptr, ads5121_save_ptr->ipic_regs,
++					sizeof(ads5121_save_ptr->ipic_regs));
++
++	reg_ptr = (u32 *)((u32)ads5121_pm_data.mbar +
++					MPC512x_IMMRBAR_CLK_OFFSET);
++	_memcpy_toio(reg_ptr, ads5121_save_ptr->clk_regs,
++					sizeof(ads5121_save_ptr->clk_regs));
++
++	reg_ptr = (u32 *)((u32)ads5121_pm_data.mbar +
++					MPC512x_IMMRBAR_GPT_OFFSET);
++	_memcpy_toio(reg_ptr, ads5121_save_ptr->gpt_regs,
++					sizeof(ads5121_save_ptr->gpt_regs));
++
++	reg_ptr = (u32 *)((u32)ads5121_pm_data.mbar +
++					MPC512x_IMMRBAR_GPIO_OFFSET);
++	_memcpy_toio(reg_ptr, ads5121_save_ptr->gpio_regs,
++					sizeof(ads5121_save_ptr->gpio_regs));
++
++	kfree(ads5121_save_ptr);
++}
++
++/*
++ * Name       : ads5121_hibernate
++ * Desc       : This function is called to hibernate.
++ *
++ * Parameters : void
++ * Return     : void
++ */
++/* Set the Target Time Register to a Future Value */
++static int ads5121_hibernate(void)
++{
++	 void ads5121_low_power(u32 *, u32 *, u32);
++	/*
++	 * 1. Save SRAM data to DDR
++	 * 2. Copy code to SRAM
++	 * 3. Configure RTC to hibernate with specified timeout.
++	 * 3. Jump to SRAM and put DDR in self refresh.
++	 */
++	u32 reg, ret;
++	u32 offset_minutes;
++
++	u32 *rtc = (u32 *)((u32)ads5121_pm_data.mbar +
++						MPC512x_IMMRBAR_RTC_OFFSET);
++	u32 *sram = (u32 *) in_be32((u32 *)((u32)ads5121_pm_data.mbar +
++						MPC512x_IMMRBAR_SRAM_OFFSET));
++
++	/* IOREMAP the SRAM address obtained from MBAR */
++	sram = ioremap((u32)sram, (256 * 1024));
++
++	if (!sram) {
++		printk(KERN_ERR "Error mapping SRAM\n");
++		return -1;
++	}
++
++	ret = ads5121_save_regs(sram);
++	if (ret < 0)
++		return -1;
++
++	/* Set the BC6 bit in the Keep Alive Register to indicate Hibernate.
++	 * The Bit Value would retained across the power cycles.
++	 */
++	reg = in_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2]);
++	reg |= (1 << 8);
++	out_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2], reg);
++
++
++	/* Set the DIS_HIB_MODE to 0 to enable the Hibernate mode
++	   out of MPC5121e.
++	 */
++	reg = in_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2]);
++	reg &= ~(1 << 7);
++	out_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2], reg);
++
++
++	/* Store the Value of the TTR Register in RTC so as to restore */
++	ads5121_pm_data.rtc_targettime = in_be32(&rtc[MPC512x_RTC_TTR >> 2]);
++
++	offset_minutes = ads5121_set_rtc_alarm();
++
++	ads5121_low_power(sram, ads5121_pm_data.mbar, offset_minutes);
++
++	/* We are out of hibernate.. Lets restart jiffies */
++	wakeup_decrementer();
++
++	out_be32(&rtc[MPC512x_RTC_TTR >> 2], ads5121_pm_data.rtc_targettime);
++
++	/* Reset the BC6 bit after coming out of Hibernate */
++	reg = in_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2]);
++	reg &= ~(1 << 8);
++	out_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2], reg);
++
++	/* Restore the Registers */
++	ads5121_restore_regs(sram);
++
++	/* IOUMAP this location only after the restore funcion. The restore
++	 * function would copy data back and then only release this memory.
++	 */
++	iounmap(sram);
++	return 0;
++}
++
++/*
++ * Name       : ads5121_set_rtc_wakeup
++ * Desc       : This function is called to enable the wakeup sources.
++ *
++ * Parameters : void
++ * Return     : void
++ */
++static void ads5121_set_rtc_wakeup(struct mpc512x_pm *p_pmdata)
++{
++	u32 rtc_reg;
++	u32 *rtc;
++
++	if (!p_pmdata->mbar)
++		return;
++
++	rtc = (u32 *)((u32)p_pmdata->mbar + MPC512x_IMMRBAR_RTC_OFFSET);
++	rtc_reg = in_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2]);
++
++	/* Set the Active LVL values for the Wake-up Sources[1-5] */
++	rtc_reg |= MPC512x_RTCKAR_WKUP_SRCLVL;
++	out_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2], rtc_reg);
++
++	rtc_reg = in_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2]);
++	/* Enable the Wake-Up sources */
++	rtc_reg |= (MPC512x_RTCKAR_WKUP_SRCEN);
++	out_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2], rtc_reg);
++}
++
++static void ads5121_prepare_hibernate(struct mpc512x_pm *p_pmdata)
++{
++	/*
++	*  Enable the wakeup sources
++	*/
++	ads5121_set_rtc_wakeup(p_pmdata);
++}
++/*
++ * Name       : ads5121_pm_valid
++ * Desc       : Checks whether the PM state is valid
++ *
++ * Parameters : void
++ * Return     : 1 - Valid , 0 - Invalid
++ */
++static int ads5121_pm_valid(suspend_state_t state)
++{
++	switch (state) {
++	case PM_SUSPEND_STANDBY:
++	case PM_SUSPEND_MEM:
++		return 1;
++	default:
++		return 0;
++	}
++}
++
++/*
++ * Name       : ads5121_pm_settarget
++ * Desc       : Set the state to which the system is to enter.
++ *
++ * Parameters : void
++ * Return     : 0 - Success
++ */
++static int ads5121_pm_settarget(suspend_state_t state)
++{
++	switch (state) {
++	case PM_SUSPEND_STANDBY:
++		ads5121_targeted_state = MPC512x_PM_STANDBY;
++		break;
++	case PM_SUSPEND_MEM:
++		ads5121_targeted_state = MPC512x_PM_SUSP_MEM;
++		break;
++	default:
++		ads5121_targeted_state = MPC512x_PM_NONE;
++	}
++	return 0;
++}
++/*
++ * Name       : ads5121_pm_prepare
++ * Desc       : This function would map the IO regions. Also sets the DDRC and
++ * 		RTC regs for Deep Sleep Mode.
++ *
++ * Parameters : void
++ * Return     : int
++ *		ENOSYS
++ *
++ */
++static int ads5121_pm_prepare(void)
++{
++	mpc512x_pm_setup(&ads5121_pm_data);
++
++	switch (ads5121_targeted_state) {
++	case MPC512x_PM_STANDBY:
++		mpc512x_prepare_deepsleep(&ads5121_pm_data);
++		break;
++	case MPC512x_PM_SUSP_MEM:
++		ads5121_prepare_hibernate(&ads5121_pm_data);
++		break;
++	}
++	return 0;
++}
++
++/*
++ * Name       : ads5121_pm_enter
++ * Desc       : This function is exported to the Power Management Core. This
++ *	`	function is called with the state which the system should enter.
++ *
++ * Parameters : state 	- PM_SUSPEND_STANDBY
++			- PM_SUSPEND_MEM
++ * Return     : int
++ * 		-1 : FAILED
++ *		0  : SUCCESS
++ */
++static int ads5121_pm_enter(suspend_state_t state)
++{
++	if (!ads5121_pm_data.mbar) {
++		printk(KERN_ERR "Failed to enter PM mode as IO not mapped.\n");
++		return -1;
++	}
++	switch (ads5121_targeted_state) {
++
++	case MPC512x_PM_STANDBY:
++		mpc512x_enter_deepsleep(&ads5121_pm_data);
++		break;
++	case MPC512x_PM_SUSP_MEM:
++		ads5121_hibernate();
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++/*
++ * Name       : ads5121_pm_finish
++ * Desc       : This routine is called by the kernel on exit from
++ * 		power down modes. Restores the DDRC and RTC regs
++ * 		suspend to memory. Also releases allocated resources.
++ *
++ * Parameters : void
++ * Return     : void
++ */
++static void ads5121_pm_finish(void)
++{
++	switch (ads5121_targeted_state) {
++
++	case MPC512x_PM_STANDBY:
++		mpc512x_finish_deepsleep(&ads5121_pm_data);
++		break;
++	case MPC512x_PM_SUSP_MEM:
++		break;
++	}
++	ads5121_targeted_state = MPC512x_PM_NONE;
++
++	mpc512x_pm_release(&ads5121_pm_data);
++}
++
++static struct platform_suspend_ops ads5121_pm_ops = {
++	.valid		= ads5121_pm_valid,
++	.begin	= ads5121_pm_settarget,
++	.prepare	= ads5121_pm_prepare,
++	.enter		= ads5121_pm_enter,
++	.finish		= ads5121_pm_finish,
++};
++
++/*
++ * Name       : ads5121_pm_init
++ * Desc       : This function registers the platform_suspend_ops
++ * 		structure with the kernel.
++ *
++ * Parameters : void
++ * Return     : int
++ */
++int __init ads5121_pm_init(void)
++{
++	suspend_set_ops(&ads5121_pm_ops);
++	return 0;
++}
++
++/*
++ * Name       : ads5121_set_rtc_alarm
++ * Desc       : This function woul dbe called from the ads5121_hibernate funct-
++ *		which return the alarm offset in case it is set. If not then
++ *		it would retun 0xFFFFFFFF, which would be the MAX value for TTR.
++ *
++ * Parameters :
++ * Return     : u32 - Offset of Alarm Value with the Current Time.
++ */
++static u32 ads5121_set_rtc_alarm()
++{
++	u32 rtc_reg;
++	u32 *rtc;
++	u32 alm_hr, alm_min, cur_hr, cur_min;
++	u32 offset_minutes;
++
++	rtc = (u32 *)((u32)ads5121_pm_data.mbar + MPC512x_IMMRBAR_RTC_OFFSET);
++
++	rtc_reg = in_be32(&rtc[MPC512x_RTC_AIER >> 2]);
++
++	if (rtc_reg & MPC512x_RTCAIER_ALMEN_MASK) {
++		/*Alarm was set.. Let us wakeup in that time..*/
++		alm_hr = (rtc_reg >> MPC512x_RTC_HR_OFFSET)
++				& MPC512x_RTC_HR_MASK;
++		alm_min = (rtc_reg >> MPC512x_RTC_MIN_OFFSET)
++				& MPC512x_RTC_MIN_MASK;
++		rtc_reg = in_be32(&rtc[MPC512x_RTC_CTR >> 2]);
++		cur_min = (rtc_reg >> MPC512x_RTC_MIN_OFFSET)
++				& MPC512x_RTC_MIN_MASK;
++
++		if (in_be32(&rtc[MPC512x_RTC_TSR >> 2])
++				& MPC512x_RTCTSR_SLCHR_MASK) {
++			/* 12 Hour Format*/
++			cur_hr = (rtc_reg >> MPC512x_RTC_HR_OFFSET) & 0xF;
++			if (rtc_reg & MPC512x_RTC_CTR_PM)
++				cur_hr += 12;
++		} else
++			cur_hr = (rtc_reg >> MPC512x_RTC_HR_OFFSET)
++					& MPC512x_RTC_HR_MASK;
++		offset_minutes = (alm_hr * MPC512x_RTC_MINS_PER_HR + alm_min) -
++					(cur_hr * MPC512x_RTC_MINS_PER_HR + cur_min);
++
++		if (offset_minutes > 0)
++			offset_minutes = offset_minutes * MPC512x_RTC_MINS_PER_HR;
++		else
++			offset_minutes = MPC512x_RTCTTR_MAXTIMEOUT;
++	} else
++		offset_minutes = MPC512x_RTCTTR_MAXTIMEOUT;
++
++	return(offset_minutes);
++}
++
++
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/ads5121_sleep.S linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/ads5121_sleep.S
+--- linux-2.6.29/arch/powerpc/platforms/512x/ads5121_sleep.S	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/ads5121_sleep.S	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,378 @@
++/*
++ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Author: Harith George <harith.george@wipro.com>
++ *
++ * Implements the Power management code to enter Suspend to RAM.
++ *
++ *    Original based on arch/powerpc/platforms/52xx/mpc52xx_sleep.S
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <asm/reg.h>
++#include <asm/ppc_asm.h>
++#include <asm/processor.h>
++#include <asm/cache.h>
++
++/* Helpers... beware: r10 and r4 are overwritten */
++#define SAVE_SPRN(reg, addr)		\
++	mfspr	r10, SPRN_##reg;	\
++	stw	r10, ((addr)*4)(r4);	\
++	sync;
++
++#define LOAD_SPRN(reg, addr)		\
++	lwz	r10, ((addr)*4)(r4);	\
++	mtspr	SPRN_##reg, r10;	\
++	sync;				\
++	isync;
++
++/* Helpers for saving registers */
++#define SAVE_BAT(n, addr)		\
++	SAVE_SPRN(DBAT##n##L, addr);	\
++	SAVE_SPRN(DBAT##n##U, addr+1);	\
++	SAVE_SPRN(IBAT##n##L, addr+2);	\
++	SAVE_SPRN(IBAT##n##U, addr+3);
++
++#define SAVE_SR(n, addr)		\
++	mfsr	r10, n;			\
++	stw	r10, ((addr)*4)(r4);
++
++#define SAVE_4SR(n, addr)	\
++	SAVE_SR(n, addr);	\
++	SAVE_SR(n+1, addr+1);	\
++	SAVE_SR(n+2, addr+2);	\
++	SAVE_SR(n+3, addr+3);
++
++/* Helpers for restoring registers */
++#define LOAD_BAT(n, addr)		\
++	LOAD_SPRN(DBAT##n##L, addr);	\
++	LOAD_SPRN(DBAT##n##U, addr+1);	\
++	LOAD_SPRN(IBAT##n##L, addr+2);	\
++	LOAD_SPRN(IBAT##n##U, addr+3);
++
++#define LOAD_SR(n, addr)		\
++	lwz	r10, ((addr)*4)(r4);	\
++	mtsr	n, r10;
++
++#define LOAD_4SR(n, addr)	\
++	LOAD_SR(n, addr);	\
++	LOAD_SR(n+1, addr+1);	\
++	LOAD_SR(n+2, addr+2);	\
++	LOAD_SR(n+3, addr+3);
++
++#define MPC5121_DDRC_OFFSET		0x9000
++#define MPC512x_IMMRBAR_RTC_OFFSET 	0xA00
++#define MPC512x_DDRC_CMD0		0x3C00
++#define MPC512x_DDRC_CMD1		0x4420
++#define MPC512x_DDRC_CMD2		0x4210
++#define MPC512x_DDRC_CMD3		0x1410
++#define DDRC_SYSCONFIG_CMD		(1 << 28)
++
++	.data
++registers:
++	.space 0x5d*4
++
++	.text
++	.globl ads5121_low_power
++ads5121_low_power:
++	/* Low-power mode with help of Power CPLD */
++	mr	r7, r3	/* save SRAM va */
++	mr 	r8, r4	/* MBAR*/
++	mr	r9, r5	/* Offset_minutes for setting the alarm */
++	mflr    r0      /* store lr into r0 */
++
++	/* setup wakeup address for u-boot at physical location 0x0 */
++	lis	r3, CONFIG_KERNEL_START@h
++	/* saving the contents of 0x00000000 at
++	 * location 0x5c offset in registers
++	 */
++	lis	r4, registers@h
++	ori	r4, r4, registers@l
++	lwz	r5, 0x0(r3)
++	stw     r5, (4*0x5c)(r4)
++
++	lis	r4, ads5121_wakeup@h
++	ori	r4, r4, ads5121_wakeup@l
++	sub	r4, r4, r3
++	stw	r4, 0(r3)
++	sync
++
++	lis	r4, registers@h
++	ori	r4, r4, registers@l
++
++	/* save registers to r4 [destroys r10] */
++	SAVE_SPRN(LR, 0x1c)
++	bl	save_regs
++
++	/* copy code to sram */
++	mr	r4, r7
++	li	r3, (sram_code_end - sram_code)/4
++	/* Added to fix the crash issue while executing from SRAM */
++	addi	r3, r3,0x3
++	mtctr	r3
++	lis	r3, sram_code@h
++	ori	r3, r3, sram_code@l
++1:
++	lwz	r5, 0(r3)
++	stw	r5, 0(r4)
++	addi	r3, r3, 4
++	addi	r4, r4, 4
++	bdnz	1b
++
++	/* flush caches [destroys r3, r4] */
++	bl	flush_data_cache
++
++	/* disable I and D caches */
++	mfspr	r3, SPRN_HID0
++	ori	r3, r3, HID0_ICE | HID0_DCE
++	xori	r3, r3, HID0_ICE | HID0_DCE
++	sync; isync;
++	mtspr	SPRN_HID0, r3
++	isync; isync;
++
++	/*
++	 * We will load the RTC ATR value here so that
++	 * we get the address in a TLB. We cannot get any
++	 * ea->pa conversions after DDR is turned off.
++	 */
++	ori	r6, r8, MPC512x_IMMRBAR_RTC_OFFSET@l
++	lwz	r5, 0x24(r6)
++
++	/* setting the alarm value */
++	lis	r4, 0xFFFF
++	ori	r4, r4,0xFFFF
++
++	/* check whether the TTR should be set
++	 * to 0xFFFFFFFF or not */
++
++	xor	r4, r4, r9
++	/* compare r4 with 0 and set the bit
++	 * in the condition register 0 */
++	cmpi	0, r4,0
++	/* branch to "alarm" until the CR0 second bit is
++	 * set i.e,equal to condition for the
++	 * above comparison */
++	bc	0xC, 2, alarm
++
++	add	r9, r5, r9
++alarm:
++	mr	r5, r9
++
++	/* jump to sram */
++	mtlr    r7
++	blrl
++	/* doesn't return */
++
++sram_code:
++	/* Put DDR in Self Refresh */
++	mr 	r3, r8
++	ori	r3, r3, MPC5121_DDRC_OFFSET@l
++	lwz	r4, 0(r3)
++	oris	r4, r4, DDRC_SYSCONFIG_CMD@h
++	stw	r4, 0(r3)
++	sync
++	li	r4, MPC512x_DDRC_CMD0@l
++	stw	r4, 0x14(r3)
++	sync
++	li	r4, MPC512x_DDRC_CMD1@l
++	stw	r4, 0x14(r3)
++	sync
++	li	r4, MPC512x_DDRC_CMD2@l
++	stw	r4, 0x14(r3)
++	sync
++	li	r4, MPC512x_DDRC_CMD3@l
++	stw	r4, 0x14(r3)
++	sync
++
++	/* Set TTR = ATR + 60 (0x3C)*/
++	stw	r5, 0x20(r6)
++	sync
++
++sram_code_end:
++	b	sram_code_end
++	sync
++	isync
++
++	/* Uboot jumps here on resume */
++ads5121_wakeup:
++	bl	restore_regs
++
++	/* HIDs, MSR */
++	LOAD_SPRN(HID1, 0x19)
++	LOAD_SPRN(HID2, 0x1a)
++
++	/* address translation is tricky (see turn_on_mmu) */
++	mfmsr	r10
++	ori	r10, r10, MSR_DR | MSR_IR
++
++	mtspr	SPRN_SRR1, r10
++	lis	r10, mmu_on@h
++	ori	r10, r10, mmu_on@l
++	mtspr	SPRN_SRR0, r10
++	sync
++	rfi
++
++mmu_on:
++	/* kernel offset (r4 is still set from restore_registers) */
++	/* Though r4, will contain, just restoring incase if its
++	 * corrupted
++	 */
++	addis	r4, r4, CONFIG_KERNEL_START@h
++
++	/* restore MSR */
++	lwz	r10, (4*0x1b)(r4)
++	mtmsr	r10
++	sync; isync;
++
++	/* invalidate caches */
++	mfspr	r10, SPRN_HID0
++	ori	r5, r10, HID0_ICFI | HID0_DCI
++	mtspr	SPRN_HID0, r5	/* invalidate caches */
++	sync; isync;
++	mtspr	SPRN_HID0, r10
++	sync; isync;
++
++	/* enable caches */
++	lwz	r10, (4*0x18)(r4)
++	mtspr	SPRN_HID0, r10	/* restore (enable caches, DPM) */
++	/* ^ this has to be after address translation set in MSR */
++	sync
++	isync
++
++	LOAD_SPRN(LR, 0x1c)
++	blr
++
++save_regs:
++	stw	r0, 0(r4)
++	stw	r1, 0x4(r4)
++	stw	r2, 0x8(r4)
++	stmw	r11, 0xc(r4) /* 0xc -> 0x5f, (0x18*4-1) */
++
++	SAVE_SPRN(HID0, 0x18)
++	SAVE_SPRN(HID1, 0x19)
++	SAVE_SPRN(HID2, 0x1a)
++	mfmsr	r10
++	stw	r10, (4*0x1b)(r4)
++	/*SAVE_SPRN(LR, 0x1c) have to save it before the call */
++	SAVE_SPRN(RPA,   0x1e)
++	SAVE_SPRN(SDR1,  0x1f)
++
++	/* save MMU regs */
++	SAVE_BAT(0, 0x20)
++	SAVE_BAT(1, 0x24)
++	SAVE_BAT(2, 0x28)
++	SAVE_BAT(3, 0x2c)
++	SAVE_BAT(4, 0x30)
++	SAVE_BAT(5, 0x34)
++	SAVE_BAT(6, 0x38)
++	SAVE_BAT(7, 0x3c)
++
++	SAVE_4SR(0, 0x40)
++	SAVE_4SR(4, 0x44)
++	SAVE_4SR(8, 0x48)
++	SAVE_4SR(12, 0x4c)
++
++	SAVE_SPRN(SPRG0, 0x50)
++	SAVE_SPRN(SPRG1, 0x51)
++	SAVE_SPRN(SPRG2, 0x52)
++	SAVE_SPRN(SPRG3, 0x53)
++	SAVE_SPRN(SPRG4, 0x54)
++	SAVE_SPRN(SPRG5, 0x55)
++	SAVE_SPRN(SPRG6, 0x56)
++	SAVE_SPRN(SPRG7, 0x57)
++
++	SAVE_SPRN(IABR,  0x58)
++	SAVE_SPRN(DABR,  0x59)
++	SAVE_SPRN(TBRL,  0x5a)
++	SAVE_SPRN(TBRU,  0x5b)
++
++	blr
++
++restore_regs:
++	lis	r4, registers@h
++	ori	r4, r4, registers@l
++
++	/* This only required in case when the register is directly accessed in Virtual Mode */
++	/* MMU is not up yet */
++	subis	r4, r4, CONFIG_KERNEL_START@h
++
++	/* restoring the contents at 0x00000000 location
++	 * from the 0x5c offset in registers
++	 */
++	lis	r5, CONFIG_KERNEL_START@h
++	subis	r5, r5, CONFIG_KERNEL_START@h
++	lwz	r3, (0x5c*4)(r4)
++	stw	r3, 0x0(r5)
++
++	lwz	r0, 0(r4)
++	lwz	r1, 0x4(r4)
++	lwz	r2, 0x8(r4)
++	lmw	r11, 0xc(r4)
++
++	/*
++	 * these are a bit tricky
++	 * 0x18 - HID0
++	 * 0x19 - HID1
++	 * 0x1a - HID2
++	 * 0x1b - MSR
++	 * 0x1c - LR
++	 */
++	LOAD_SPRN(RPA,   0x1e);
++	LOAD_SPRN(SDR1,  0x1f);
++
++	/* restore MMU regs */
++	LOAD_BAT(0, 0x20)
++	LOAD_BAT(1, 0x24)
++	LOAD_BAT(2, 0x28)
++	LOAD_BAT(3, 0x2c)
++	LOAD_BAT(4, 0x30)
++	LOAD_BAT(5, 0x34)
++	LOAD_BAT(6, 0x38)
++	LOAD_BAT(7, 0x3c)
++
++	LOAD_4SR(0, 0x40)
++	LOAD_4SR(4, 0x44)
++	LOAD_4SR(8, 0x48)
++	LOAD_4SR(12, 0x4c)
++
++	/* rest of regs */
++	LOAD_SPRN(SPRG0, 0x50);
++	LOAD_SPRN(SPRG1, 0x51);
++	LOAD_SPRN(SPRG2, 0x52);
++	LOAD_SPRN(SPRG3, 0x53);
++	LOAD_SPRN(SPRG4, 0x54);
++	LOAD_SPRN(SPRG5, 0x55);
++	LOAD_SPRN(SPRG6, 0x56);
++	LOAD_SPRN(SPRG7, 0x57);
++
++	LOAD_SPRN(IABR,  0x58);
++	LOAD_SPRN(DABR,  0x59);
++	LOAD_SPRN(TBWL,  0x5a);	/* these two have separate R/W regs */
++	LOAD_SPRN(TBWU,  0x5b);
++
++	blr
++
++
++/* cache flushing code. copied from arch/ppc/boot/util.S */
++/*
++ * Flush data cache
++ * Do this by just reading lots of stuff into the cache.
++ * We copy twice the cache lines to make sure all cache
++ * is flushed..
++ */
++#define NUM_CACHE_LINES (128*8*2)
++
++flush_data_cache:
++	lis	r3, CONFIG_KERNEL_START@h
++	ori	r3, r3, CONFIG_KERNEL_START@l
++	li	r4, NUM_CACHE_LINES
++	mtctr	r4
++1:
++	lwz	r4, 0(r3)
++	addi	r3, r3, L1_CACHE_BYTES	/* Next line, please */
++	bdnz	1b
++	blr
++
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/clock.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/clock.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/clock.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/clock.c	2010-04-13 20:23:26.000000000 +0200
+@@ -30,10 +30,11 @@
+ #undef CLK_DEBUG
+ 
+ static int clocks_initialized;
++static int rev2_silicon;
+ 
+ #define CLK_HAS_RATE	0x1	/* has rate in MHz */
+ #define CLK_HAS_CTRL	0x2	/* has control reg and bit */
+-
++#define ROUND_1MHZ	1000000	/* 1MHZ */
+ struct clk {
+ 	struct list_head node;
+ 	char name[32];
+@@ -50,18 +51,18 @@
+ static LIST_HEAD(clocks);
+ static DEFINE_MUTEX(clocks_mutex);
+ 
+-static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
++struct clk *clk_get(struct device *dev, const char *id)
+ {
+ 	struct clk *p, *clk = ERR_PTR(-ENOENT);
+ 	int dev_match = 0;
+ 	int id_match = 0;
+ 
+-	if (dev == NULL || id == NULL)
++	if (dev == NULL && id == NULL) {
+ 		return NULL;
+-
++	}
+ 	mutex_lock(&clocks_mutex);
+ 	list_for_each_entry(p, &clocks, node) {
+-		if (dev == p->dev)
++		if (dev && dev == p->dev)
+ 			dev_match++;
+ 		if (strcmp(id, p->name) == 0)
+ 			id_match++;
+@@ -74,6 +75,7 @@
+ 
+ 	return clk;
+ }
++EXPORT_SYMBOL(clk_get);
+ 
+ #ifdef CLK_DEBUG
+ static void dump_clocks(void)
+@@ -99,10 +101,11 @@
+ #endif
+ 
+ 
+-static void mpc5121_clk_put(struct clk *clk)
++void clk_put(struct clk *clk)
+ {
+ 	module_put(clk->owner);
+ }
++EXPORT_SYMBOL(clk_put);
+ 
+ #define NRPSC 12
+ 
+@@ -117,11 +120,13 @@
+ 	u32 spccr;		/* SPDIF Clk Ctrl Reg */
+ 	u32 cccr;		/* CFM Clk Ctrl Reg */
+ 	u32 dccr;		/* DIU Clk Cnfg Reg */
++	/* rev2 only regs */
++	u32 mccr[4];		/* MSCAN Clk Ctrl Reg 1-3 */
+ };
+ 
+ struct mpc512x_clockctl __iomem *clockctl;
+ 
+-static int mpc5121_clk_enable(struct clk *clk)
++int clk_enable(struct clk *clk)
+ {
+ 	unsigned int mask;
+ 
+@@ -132,8 +137,9 @@
+ 	}
+ 	return 0;
+ }
++EXPORT_SYMBOL(clk_enable);
+ 
+-static void mpc5121_clk_disable(struct clk *clk)
++void clk_disable(struct clk *clk)
+ {
+ 	unsigned int mask;
+ 
+@@ -143,32 +149,46 @@
+ 		out_be32(&clockctl->sccr[clk->reg], mask);
+ 	}
+ }
++EXPORT_SYMBOL(clk_disable);
+ 
+-static unsigned long mpc5121_clk_get_rate(struct clk *clk)
++unsigned long clk_get_rate(struct clk *clk)
+ {
+-	if (clk->flags & CLK_HAS_RATE)
++	if (clk->flags & CLK_HAS_RATE) {
+ 		return clk->rate;
+-	else
++	} else {
+ 		return 0;
++	}
+ }
++EXPORT_SYMBOL(clk_get_rate);
+ 
+-static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
++long clk_round_rate(struct clk *clk, unsigned long rate)
+ {
+ 	return rate;
+ }
++EXPORT_SYMBOL(clk_round_rate);
+ 
+-static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
++int clk_set_rate(struct clk *clk, unsigned long rate)
+ {
+ 	return 0;
+ }
++EXPORT_SYMBOL(clk_set_rate);
+ 
+-static int clk_register(struct clk *clk)
++int clk_register(struct clk *clk)
+ {
+ 	mutex_lock(&clocks_mutex);
+ 	list_add(&clk->node, &clocks);
+ 	mutex_unlock(&clocks_mutex);
+ 	return 0;
+ }
++EXPORT_SYMBOL(clk_register);
++
++void clk_unregister(struct clk *clk)
++{
++	mutex_lock(&clocks_mutex);
++	list_del(&clk->node);
++	mutex_unlock(&clocks_mutex);
++}
++EXPORT_SYMBOL(clk_unregister);
+ 
+ static unsigned long spmf_mult(void)
+ {
+@@ -236,16 +256,15 @@
+ 
+ static unsigned long devtree_getfreq(char *clockname)
+ {
+-	struct device_node *np;
+-	const unsigned int *prop;
++	struct device_node *node;
++	const unsigned int *fp;
+ 	unsigned int val = 0;
+ 
+-	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
+-	if (np) {
+-		prop = of_get_property(np, clockname, NULL);
+-		if (prop)
+-			val = *prop;
+-	    of_node_put(np);
++	node = of_find_node_by_type(NULL, "soc");
++	if (node) {
++		fp = of_get_property(node, clockname, NULL);
++		if (fp)
++			val = of_read_ulong(fp, 1);
+ 	}
+ 	return val;
+ }
+@@ -254,13 +273,21 @@
+ {
+ 	unsigned long rate;
+ 
+-	rate = devtree_getfreq("bus-frequency");
++	rate = devtree_getfreq("ref-frequency");
+ 	if (rate == 0) {
+-		printk(KERN_ERR "No bus-frequency in dev tree\n");
+-		clk->rate = 0;
+-		return;
++		/*
++		 * no reference clock in device tree
++		 * get ips clock freq and go backwards from there
++		 */
++		rate = devtree_getfreq("bus-frequency");
++		if (rate == 0) {
++			printk(KERN_WARNING
++				"No bus-frequency in dev tree using 66MHz\n");
++			clk->rate = 66000000;
++			return;
++		}
++		clk->rate = ips_to_ref(rate);
+ 	}
+-	clk->rate = ips_to_ref(rate);
+ }
+ 
+ static struct clk ref_clk = {
+@@ -661,8 +688,11 @@
+ 	struct device_node *np;
+ 	const u32 *cell_index;
+ 	struct of_device *ofdev;
+-
++#ifdef CONFIG_PPC_MPC5125
++	for_each_compatible_node(np, NULL, "fsl,mpc5125-psc") {
++#else
+ 	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
++#endif
+ 		cell_index = of_get_property(np, "cell-index", NULL);
+ 		if (cell_index) {
+ 			int pscnum = *cell_index;
+@@ -686,28 +716,97 @@
+ 	}
+ }
+ 
+-static struct clk_interface mpc5121_clk_functions = {
+-	.clk_get		= mpc5121_clk_get,
+-	.clk_enable		= mpc5121_clk_enable,
+-	.clk_disable		= mpc5121_clk_disable,
+-	.clk_get_rate		= mpc5121_clk_get_rate,
+-	.clk_put		= mpc5121_clk_put,
+-	.clk_round_rate		= mpc5121_clk_round_rate,
+-	.clk_set_rate		= mpc5121_clk_set_rate,
+-	.clk_set_parent		= NULL,
+-	.clk_get_parent		= NULL,
+-};
++unsigned long round_rate(unsigned long rate)
++{
++	unsigned long new_rate;
++	new_rate = (unsigned long)((rate + ROUND_1MHZ) / ROUND_1MHZ) *
++							ROUND_1MHZ;
++	return new_rate;
++}
++
++/*
++ * mscan clock rate calculation
++ */
++static void mscan_calc_rate(struct clk *clk, int mscannum, struct device_node *np)
++{
++	unsigned long mscanclk_src = sys_clk.rate;
++	unsigned long mscanclk_div;
++
++	/*
++	 * If the divider is the reset default of all 1's then
++	 * we know u-boot and/or board setup has not
++	 * done anything so set up a sane default
++	 */
++	if (((clockctl->mccr[mscannum] >> 17) & 0x7fff) == 0x7fff) {
++		/* disable */
++		clockctl->mccr[mscannum] = 0x0;
++		/* src is sysclk, divider is 4 */
++		clockctl->mccr[mscannum] = 0x3 << 17;
++		/* enable */
++		clockctl->mccr[mscannum] |= 0x10000;
++	}
++
++	switch ((clockctl->mccr[mscannum] >> 14) & 0x3) {
++	case 0:
++		mscanclk_src = round_rate(sys_clk.rate);
++		break;
++	case 1:
++		mscanclk_src = round_rate(ref_clk.rate);
++		break;
++	case 2:
++		mscanclk_src = round_rate(psc_mclk_in.rate);
++		break;
++	case 3:
++		mscanclk_src = round_rate(spdif_txclk.rate);
++		break;
++	}
++
++	mscanclk_div = ((clockctl->mccr[mscannum] >> 17) & 0x7fff) + 1;
++	clk->rate = mscanclk_src / mscanclk_div;
++}
++struct clk mscan_clks[4];
++
++/*
++ * Find all silicon rev2 mscan nodes in device tree and assign a clock
++ * with name "mscan%d_clk" and dev pointing at the device
++ * returned from of_find_device_by_node
++ */
++static void mscan_clks_init(void)
++{
++	struct device_node *np;
++	const u32 *cell_index;
++	struct of_device *ofdev;
++
++	for_each_compatible_node(np, NULL, "fsl,mpc5121rev2-mscan") {
++		cell_index = of_get_property(np, "cell-index", NULL);
++		if (cell_index) {
++			int mscannum = *cell_index;
++			struct clk *clk = &mscan_clks[mscannum];
++
++			clk->flags = CLK_HAS_RATE;
++			ofdev = of_find_device_by_node(np);
++			clk->dev = &ofdev->dev;
++			mscan_calc_rate(clk, mscannum, np);
++			sprintf(clk->name, "mscan%d_clk", mscannum);
++			printk("register :%s \n",clk->name);
++			clk_register(clk);
++		}
++	}
++}
+ 
+ static int
+ mpc5121_clk_init(void)
+ {
+ 	struct device_node *np;
+ 
+-	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+-	if (np) {
+-		clockctl = of_iomap(np, 0);
+-		of_node_put(np);
+-	}
++	/* look for rev2 first then rev1 */
++	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121rev2-clock");
++	if (np)
++		rev2_silicon++;
++	else
++		np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
++	clockctl = of_iomap(np, 0);
++	of_node_put(np);
+ 
+ 	if (!clockctl) {
+ 		printk(KERN_ERR "Could not map clock control registers\n");
+@@ -716,12 +815,13 @@
+ 
+ 	rate_clks_init();
+ 	psc_clks_init();
++	if (rev2_silicon)
++		mscan_clks_init();
+ 
+ 	/* leave clockctl mapped forever */
+ 	/*iounmap(clockctl); */
+ 	DEBUG_CLK_DUMP();
+ 	clocks_initialized++;
+-	clk_functions = mpc5121_clk_functions;
+ 	return 0;
+ }
+ 
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/Kconfig linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/Kconfig
+--- linux-2.6.29/arch/powerpc/platforms/512x/Kconfig	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/Kconfig	2010-04-13 20:23:26.000000000 +0200
+@@ -6,9 +6,25 @@
+ 	select PPC_PCI_CHOICE
+ 	select FSL_PCI if PCI
+ 
++config PPC_MPC5125
++	bool
++	select PPC_MPC512x
++	select USB_ARCH_HAS_EHCI
++	select USB_EHCI_BIG_ENDIAN_DESC
++	select USB_EHCI_BIG_ENDIAN_MMIO
++	select USB_FSL_BIG_ENDIAN_DESC
++	select PPC_INDIRECT_PCI
++	default n
++
+ config PPC_MPC5121
+ 	bool
+ 	select PPC_MPC512x
++	select USB_ARCH_HAS_EHCI
++	select USB_EHCI_BIG_ENDIAN_DESC
++	select USB_EHCI_BIG_ENDIAN_MMIO
++	select USB_FSL_BIG_ENDIAN_DESC
++	select PPC_INDIRECT_PCI
++	default n
+ 
+ config MPC5121_ADS
+ 	bool "Freescale MPC5121E ADS"
+@@ -18,6 +34,19 @@
+ 	select MPC5121_ADS_CPLD
+ 	help
+ 	  This option enables support for the MPC5121E ADS board.
++config PPC_MERGE
++	bool "Freescale MPC5121 PORTING TO MPC5125 tower"
++	depends on MPC5125_TWR
++	default n
++config MPC5125_TWR
++	bool "Freescale MPC5125 tower"
++	depends on PPC_MULTIPLATFORM && PPC32
++	select DEFAULT_UIMAGE
++	select PPC_MPC5125
++	select PPC_MERGE
++	help
++	  This option enables support for the MPC5121E ADS board.
++
+ 
+ config MPC5121_GENERIC
+ 	bool "Generic support for simple MPC5121 based boards"
+@@ -29,4 +58,24 @@
+ 	  which do not need custom platform specific setup.
+ 
+ 	  Compatible boards include:  Protonic LVT base boards (ZANMCU
+-	  and VICVT2).
++		and VICVT2).
++
++config MPC5121_ADS_HIB
++        bool "Hibernate Support for ADS5121"
++        depends on PM && ARCH_SUSPEND_POSSIBLE
++        ---help---
++          This option enables support for Hibernate on ADS5121 board
++	  (based on MPC5121e). The Hibernate is entered by writing
++	  "mem" to /sys/power/state, while Deep-Sleep mode is
++	  supported by writing "standby" to /sys/power/state.
++        default n
++
++
++config MPC5121_PM_TEST
++	bool "Lowlevel test for Freescale MPC5121E Power Management"
++	depends on PM
++	---help---
++	  Say yes here to enable low level powermanagement test code.
++	  It uses the MSCAN modules so the 5121 MSCAN driver must
++	  be turned off.
++
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/Makefile linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/Makefile
+--- linux-2.6.29/arch/powerpc/platforms/512x/Makefile	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/Makefile	2010-04-13 20:23:26.000000000 +0200
+@@ -1,6 +1,13 @@
+ #
+ # Makefile for the Freescale PowerPC 512x linux kernel.
+ #
+-obj-y				+= clock.o mpc512x_shared.o
++obj-y				+= clock.o mpc512x_shared.o mpc5121_usb.o mpc5121_pscgpio.o
++obj-$(CONFIG_SPI)		+= mpc5121_spi.o
+ obj-$(CONFIG_MPC5121_ADS)	+= mpc5121_ads.o mpc5121_ads_cpld.o
++obj-$(CONFIG_MPC5125_TWR)	+=mpc5125_twr.o
+ obj-$(CONFIG_MPC5121_GENERIC)	+= mpc5121_generic.o
++obj-$(CONFIG_PM)		+= mpc512x_pm.o mpc512x.o
++ifeq ($(CONFIG_MPC5121_ADS_HIB),y)
++	obj-$(CONFIG_PM)		+= ads5121_pm.o ads5121_sleep.o
++endif
++obj-$(CONFIG_MPC5121_PM_TEST)	+= mpc512x_pm_test.o
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/mpc5121_ads.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc5121_ads.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/mpc5121_ads.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc5121_ads.c	1970-01-01 01:00:00.000000000 +0100
+@@ -1,71 +0,0 @@
+-/*
+- * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc. All rights reserved.
+- *
+- * Author: John Rigby, <jrigby@freescale.com>, Thur Mar 29 2007
+- *
+- * Description:
+- * MPC5121 ADS board setup
+- *
+- * This is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/io.h>
+-#include <linux/of_platform.h>
+-
+-#include <asm/machdep.h>
+-#include <asm/ipic.h>
+-#include <asm/prom.h>
+-#include <asm/time.h>
+-
+-#include <sysdev/fsl_pci.h>
+-
+-#include "mpc512x.h"
+-#include "mpc5121_ads.h"
+-
+-static void __init mpc5121_ads_setup_arch(void)
+-{
+-#ifdef CONFIG_PCI
+-	struct device_node *np;
+-#endif
+-	printk(KERN_INFO "MPC5121 ADS board from Freescale Semiconductor\n");
+-	/*
+-	 * cpld regs are needed early
+-	 */
+-	mpc5121_ads_cpld_map();
+-
+-#ifdef CONFIG_PCI
+-	for_each_compatible_node(np, "pci", "fsl,mpc5121-pci")
+-		mpc83xx_add_bridge(np);
+-#endif
+-}
+-
+-static void __init mpc5121_ads_init_IRQ(void)
+-{
+-	mpc512x_init_IRQ();
+-	mpc5121_ads_cpld_pic_init();
+-}
+-
+-/*
+- * Called very early, MMU is off, device-tree isn't unflattened
+- */
+-static int __init mpc5121_ads_probe(void)
+-{
+-	unsigned long root = of_get_flat_dt_root();
+-
+-	return of_flat_dt_is_compatible(root, "fsl,mpc5121ads");
+-}
+-
+-define_machine(mpc5121_ads) {
+-	.name			= "MPC5121 ADS",
+-	.probe			= mpc5121_ads_probe,
+-	.setup_arch		= mpc5121_ads_setup_arch,
+-	.init			= mpc512x_declare_of_platform_devices,
+-	.init_IRQ		= mpc5121_ads_init_IRQ,
+-	.get_irq		= ipic_get_irq,
+-	.calibrate_decr		= generic_calibrate_decr,
+-};
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/mpc5121_pscgpio.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc5121_pscgpio.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/mpc5121_pscgpio.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc5121_pscgpio.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,172 @@
++/*
++ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Author: John Rigby, <jrigby@freescale.com>, April 2008
++ *
++ * Description:
++ * MPC5121 psc gpio helper routines
++ *
++ * This is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/of_platform.h>
++
++#include <asm/io.h>
++
++/*
++ * Helper routines for pscN_M pins.
++ * Allow for making the psc pins into GPIO outputs and
++ * driving them high or low.
++ * These are for use by the various psc drivers (Audio, SPI, whatever)
++ * so they don't have to be polluted with IOCTL and GPIO knowledge.
++ *
++ * TODO:  Make a full fledged GPIO driver.
++ */
++
++/*
++ * psc/pin to gpio number map
++ *   psc pin gpio
++ * ==========================
++ *   0    0   8  (psc % 5)*4 + 8 + pin
++ *   0    1   9
++ *   0    2   10
++ *   0    3   11
++ *   0    4   0  psc % 8
++ *   1    0   12
++ *   1    1   13
++ *   1    2   14
++ *   1    3   15
++ *   1    4   1
++ *   2    0   16
++ *   ....
++ *   pin 4 cycles through GPIOs 0-7
++ *   other pins cycle through GPIOs 8-27
++ *   ....
++ *   10   2   10
++ *   10   3   11
++ *   10   4   2
++ *   11   0   12
++ *   11   1   13
++ *   11   2   14
++ *   11   3   15
++ *   11   4   3
++ */
++
++#define PSC_TO_GPIO(psc, pin) ( \
++    pin == 4 ?			\
++	(psc % 8)		\
++    :				\
++	(psc % 5) * 4 + 8 + pin	\
++)
++#ifdef CONFIG_PPC_MPC5125
++#define PSC_TO_IOCTL_OFFSET(psc, pin) ( \
++	0x76				\
++	+ psc * (5*sizeof(u8))		\
++	+ pin * sizeof(u8)		\
++)
++#else
++#define PSC_IOCTL_SIZE (5 * sizeof(long))
++
++#define PSC_TO_IOCTL_OFFSET(psc, pin) ( \
++	0x20C				\
++	+ psc * PSC_IOCTL_SIZE		\
++	+ pin * sizeof(long)		\
++)
++#endif
++static void __iomem *gpioctl;
++#define GPIODIR 0
++#define GPIODAT 8
++static void  __iomem *ioctl;
++
++void mpc5121_pscgpio_make_gpio(int psc, int pin)
++{
++	out_be32(ioctl + PSC_TO_IOCTL_OFFSET(psc, pin), 0x00000183);
++	setbits32(gpioctl+GPIODIR, 0x80000000 >> PSC_TO_GPIO(psc, pin));
++}
++EXPORT_SYMBOL(mpc5121_pscgpio_make_gpio);
++
++void mpc5121_pscgpio_make_psc(int psc, int pin)
++{
++#ifdef CONFIG_PPC_MPC5125
++	out_8(ioctl + PSC_TO_IOCTL_OFFSET(psc, pin), pin == 0 ? 0x7 : 0x03);
++#else
++	out_be32(ioctl + PSC_TO_IOCTL_OFFSET(psc, pin), pin == 0 ? 0x00000007 : 0x00000003);
++#endif
++}
++EXPORT_SYMBOL(mpc5121_pscgpio_make_psc);
++
++void mpc5121_pscgpio_make_psc_pull_up(int psc, int pin)
++{
++#ifdef CONFIG_PPC_MPC5125
++	out_8(ioctl + PSC_TO_IOCTL_OFFSET(psc, pin), pin == 0 ? 0x1f : 0x1b);
++#else
++	out_be32(ioctl + PSC_TO_IOCTL_OFFSET(psc, pin), pin == 0 ? 0x00000007 : 0x00000003);
++#endif
++}
++EXPORT_SYMBOL(mpc5121_pscgpio_make_psc_pull_up);
++
++#ifdef CONFIG_PPC_MPC5125
++void mpc5125_psc_io_controller_set(int psc, int pin,unsigned char value)
++{
++	out_8(ioctl + PSC_TO_IOCTL_OFFSET(psc, pin), value);
++}
++EXPORT_SYMBOL(mpc5125_psc_io_controller_set);
++void mpc5125_io_controller_set(int offset,unsigned char value)
++{
++	out_8(ioctl + offset, value);
++}
++EXPORT_SYMBOL(mpc5125_io_controller_set);
++#endif
++void mpc5121_pscgpio_pin_high(int psc, int pin)
++{
++	setbits32(gpioctl+GPIODAT, 0x80000000 >> PSC_TO_GPIO(psc, pin));
++}
++EXPORT_SYMBOL(mpc5121_pscgpio_pin_high);
++
++void mpc5121_pscgpio_pin_low(int psc, int pin)
++{
++	clrbits32(gpioctl+GPIODAT, 0x80000000 >> PSC_TO_GPIO(psc, pin));
++}
++EXPORT_SYMBOL(mpc5121_pscgpio_pin_low);
++
++static int __init mpc5121_pscgpio_init(void)
++{
++	struct device_node *np;
++#ifdef CONFIG_PPC_MPC5125
++	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5125-ioctl");
++#else
++	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ioctl");
++#endif
++	if (np) {
++		ioctl = of_iomap(np, 0);
++		of_node_put(np);
++	}
++/*enable nand_ce1*/
++	out_8(ioctl+0x08,0x3b);
++#ifdef CONFIG_PPC_MPC5125
++	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5125-gpio");
++#else
++	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-gpio");
++#endif
++	if (np) {
++		gpioctl = of_iomap(np, 0);
++		of_node_put(np);
++	}
++
++	/* don't unmap these, they will be used later */
++	/*
++	 * iounmap(ioctl);
++	 * iounmap(gpioctl);
++	 */
++
++	printk(KERN_INFO "mapped ioctl to %p and gpioctl to %p\n",
++		(void *)ioctl, (void *)gpioctl);
++
++	return 0;
++}
++
++arch_initcall(mpc5121_pscgpio_init);
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/mpc5121_spi.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc5121_spi.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/mpc5121_spi.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc5121_spi.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,188 @@
++/*
++ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Author: John Rigby, <jrigby@freescale.com>, May 2008
++ *
++ * Description:
++ * MPC5121 spi setup 
++ *
++ * This is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/of_platform.h>
++#include <linux/spi/spi.h>
++#include <linux/fsl_devices.h>
++
++#include <asm/io.h>
++
++#include "mpc512x.h"
++
++static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
++{
++	const u32 *prop;
++	int len;
++
++	prop = of_get_property(np, name, &len);
++	if (prop && len == 4)
++		return *prop;
++	return def;
++}
++
++#define GET_INT_PROP(pd, np, propname)	\
++	(pd->propname = get_int_prop(np, #propname, pd->propname))
++
++
++#if 0/*defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)*/
++#define CFG_ADS7846
++#include <linux/spi/ads7846.h>
++#endif
++
++#if 0 /* CFG_ADS7846*/
++
++static struct ads7846_platform_data mpc5121eads_ads7846_platform_data __initdata = {
++	.model			= 7843,
++	.vref_delay_usecs	= 100,
++	.x_plate_ohms		= 500,
++	.y_plate_ohms		= 500,
++	.get_pendown_state	= mpc5121ads_get_pendown_state,
++};
++
++static void __init *ads7846_get_pdata(struct device_node *np)
++{
++	struct ads7846_platform_data *pd = &mpc5121eads_ads7846_platform_data;
++	GET_INT_PROP(pd, np, model);
++	GET_INT_PROP(pd, np, vref_delay_usecs);
++	GET_INT_PROP(pd, np, x_plate_ohms);
++	GET_INT_PROP(pd, np, y_plate_ohms);
++
++	return pd;
++}
++#endif
++
++struct spi_driver_device {
++	char *of_device;
++	char *modalias;
++	int needirq;
++	void *(*get_platform_data)(struct device_node *);
++};
++
++static struct spi_driver_device spi_devices[] __initdata = {
++#ifdef CONFIG_SPI_SPIDEV
++	{
++		.of_device = "linux,spidev",
++		.modalias = "spidev",
++	},
++#endif
++#ifdef CFG_ADS7846
++	{
++		.of_device = "ti,ads7846",
++		.modalias = "ads7846",
++		.needirq = 1,
++		.get_platform_data = ads7846_get_pdata,
++	},
++#endif
++#ifdef CONFIG_SND_SOC_AD1939
++	{
++		.of_device = "ad,ad1938",
++		.modalias = "AD1939",
++	},
++	{
++		.of_device = "ad,ad1939",
++		.modalias ="AD1939",
++	},
++#endif
++};
++
++static int __init find_spi_driver(struct device_node *node,
++				     struct spi_board_info *info)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(spi_devices); i++) {
++		if (!of_device_is_compatible(node, spi_devices[i].of_device))
++			continue;
++		if (spi_devices[i].needirq && info->irq == NO_IRQ) {
++			printk(KERN_WARNING "mpc5121_spi.c %s needs valid irq\n",
++			       spi_devices[i].modalias);	
++			return -EINVAL;
++		}
++		/*
++		if (strlcpy(info->modalias, spi_devices[i].modalias,
++			    KOBJ_NAME_LEN) >= KOBJ_NAME_LEN)
++		*/
++		if (strlcpy(info->modalias, spi_devices[i].modalias,
++			    20) >= 20)
++			return -ENOMEM;
++		if (spi_devices[i].get_platform_data)
++			info->platform_data = spi_devices[i].get_platform_data(node);
++		return 0;
++	}
++	return -ENODEV;
++}
++
++static int of_device_add_data(struct of_device *of_dev, const void *data, size_t size)
++{
++	void *d;
++
++	d = kmalloc(size, GFP_KERNEL);
++	if (d) {
++		memcpy(d, data, size);
++		of_dev->dev.platform_data = d;
++	}
++	return d ? 0 : -ENOMEM;
++}
++
++static void __init register_spi_bus(struct device_node *spi_node, int bus_num)
++{
++	struct device_node *node = NULL;
++	struct of_device *of_dev;
++	struct fsl_spi_platform_data pdata = {
++		.bus_num = bus_num,
++		.max_chipselect = 255,
++	};
++
++	of_dev = of_find_device_by_node(spi_node);
++	if (of_dev) {
++		of_device_add_data(of_dev, &pdata, sizeof(pdata));
++	}
++
++	while ((node = of_get_next_child(spi_node, node))) {
++		struct spi_board_info *bp, info = {};
++
++		bp = &info;
++			
++		bp->bus_num = bus_num;
++		GET_INT_PROP(bp, node, chip_select);
++		GET_INT_PROP(bp, node, max_speed_hz);
++		info.irq = irq_of_parse_and_map(node, 0);
++
++		if (find_spi_driver(node, &info) < 0)
++			continue;
++
++		spi_register_board_info(&info, 1);
++	}
++}
++
++static int __init mpc5121_spi_init(void)
++{
++	struct device_node *np;
++	int bus_num;
++
++	for_each_compatible_node(np, NULL, "fsl,mpc5121-psc-spi") {
++		bus_num = get_int_prop(np, "cell-index", -1);
++		if (bus_num < 0 || bus_num > 11) {
++			printk(KERN_WARNING "mpc5121_spi.c no cell-index spi node, skipping\n");
++			continue;
++		}
++		register_spi_bus(np, bus_num);
++		of_node_put(np);
++	}
++
++	return 0;
++}
++
++arch_initcall(mpc5121_spi_init);
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/mpc5121_usb.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc5121_usb.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/mpc5121_usb.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc5121_usb.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,107 @@
++/*
++ * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Author: Duck, <duck@freescale.com>, Tue Oct 2 2007
++ *
++ * Description:
++ * MPC5121 USB platform-specific routines
++ *
++ * This is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/errno.h>
++#include <linux/fsl_devices.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/stddef.h>
++
++#define USBGENCTRL		0x200	/* NOTE: big endian */
++#define GC_WU_INT_CLR		(1 << 5)	/* Wakeup int clear */
++#define GC_ULPI_SEL		(1 << 4)	/* ULPI i/f select (usb0 only)*/
++#define GC_PPP			(1 << 3)	/* Port Power Polarity */
++#define GC_PFP			(1 << 2)	/* Power Fault Polarity */
++#define GC_WU_ULPI_EN		(1 << 1)	/* Wakeup on ULPI event */
++#define GC_WU_IE		(1 << 1)	/* Wakeup interrupt enable */
++
++#define ISIPHYCTRL		0x204	/* NOTE: big endian */
++#define PHYCTRL_PHYE		(1 << 4)	/* On-chip UTMI PHY enable */
++#define PHYCTRL_BSENH		(1 << 3)	/* Bit Stuff Enable High */
++#define PHYCTRL_BSEN		(1 << 2)	/* Bit Stuff Enable */
++#define PHYCTRL_LSFE		(1 << 1)	/* Line State Filter Enable */
++#define PHYCTRL_PXE		(1 << 0)	/* PHY oscillator enable */
++
++
++int usb_platform_mph_init(struct platform_device *pdev)
++{
++	return -ENODEV;		/* no MPH port on 5121 */
++}
++EXPORT_SYMBOL_GPL(usb_platform_mph_init);
++
++
++void usb_platform_mph_uninit(struct fsl_usb2_platform_data *pdata)
++{
++}
++EXPORT_SYMBOL_GPL(usb_platform_mph_uninit);
++
++static struct clk *dr_clk;
++static int dr_used;
++
++int usb_platform_dr_init(struct platform_device *pdev)
++{
++	struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
++
++	pr_debug("%s:  pdata %p\n\n", __FUNCTION__, pdata);
++
++	/* enable the clock if we haven't already */
++	if (!dr_used) {
++		dr_clk = clk_get(&pdev->dev, "usb2_clk");
++		if (IS_ERR(dr_clk)) {
++			dev_err(&pdev->dev, "usb: clk_get failed\n");
++			return -ENODEV;
++		}
++		clk_enable(dr_clk);
++	}
++	dr_used++;
++
++	pdata->big_endian_desc = 1;
++	pdata->le_setup_buf = 1;
++	pdata->es = 1;
++
++	if (pdata->phy_mode == FSL_USB2_PHY_UTMI_WIDE) {
++		void __iomem *base = pdata->regs;
++
++		out_be32(base + ISIPHYCTRL, PHYCTRL_PHYE | PHYCTRL_PXE);
++		out_be32(base + USBGENCTRL, GC_PPP | GC_PFP);
++	}
++	pr_debug("%s: success\n", __FUNCTION__);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(usb_platform_dr_init);
++
++void usb_platform_dr_uninit(struct fsl_usb2_platform_data *pdata)
++{
++	pr_debug("%s\n", __FUNCTION__);
++
++	pdata->regs = NULL;
++	// DDD no longer used pdata->r_start = pdata->r_len = 0;
++
++	dr_used--;
++	if (!dr_used) {
++		clk_disable(dr_clk);
++		clk_put(dr_clk);
++		dr_clk = NULL;
++	}
++}
++EXPORT_SYMBOL_GPL(usb_platform_dr_uninit);
++
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/mpc5125_twr.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc5125_twr.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/mpc5125_twr.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc5125_twr.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,584 @@
++/*
++ * Provider: LimePC Multimedia Technologies Co., Limited
++ * Date:02/02/2010
++ * autor:Cloudy Chen <chen_yunsong@mtcera.com>
++ * Description:
++ * MPC5125 tower board setup
++ *
++ * This is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/of_platform.h>
++
++#include <asm/machdep.h>
++#include <asm/ipic.h>
++#include <asm/prom.h>
++#include <asm/time.h>
++
++#include <asm/mpc512x.h>
++#include <sysdev/fsl_soc.h>
++
++#include <linux/bootmem.h>
++#include <asm/rheap.h>
++
++#include "mpc512x.h"
++
++#ifdef DEBUG
++#define DPRINTK(fmt, args...) printk("%s: " fmt,__FUNCTION__,## args)
++#else
++#define DPRINTK(fmt, args...)
++#endif
++asmlinkage long sys_mtc_system_call( int cmd, int arg)
++{
++	void __user *argp = (void __user *)arg;
++	int error=-1;
++	return error;
++}
++static u32 get_busfreq(void)
++{
++	struct device_node *node;
++
++	u32 fs_busfreq=0;
++	node = of_find_node_by_type(NULL, "cpu");
++	if (node) {
++		unsigned int size;
++		const unsigned int *prop = of_get_property(node,"bus-frequency", &size);
++		if (prop)
++		fs_busfreq = *prop;
++		of_node_put(node);
++	};
++	return fs_busfreq;
++}
++
++#ifdef CONFIG_FB_FSL_DIU
++#define DISABLE_RH_MEMORY	0
++
++static rh_block_t diu_rh_block[16];
++static rh_info_t diu_rh_info;
++static unsigned long diu_size = 1280 * 1024 * 4; /* One 1280x1024 buffer */
++static void *diu_mem;
++
++unsigned int platform_get_pixel_format(unsigned int bits_per_pixel,
++					int monitor_port,
++					char byte_flip)
++{
++	unsigned int pix_fmt;
++
++	if (bits_per_pixel == 32) {
++		if (byte_flip)
++			pix_fmt = 0x88883316;
++		else
++			pix_fmt = 0x88883306;
++	} else if (bits_per_pixel == 24) {
++		pix_fmt = 0x88082219;
++	} else if (bits_per_pixel == 16) {
++		if (byte_flip)
++			pix_fmt = 0x65053118;
++		else
++			pix_fmt = 0x65052908;
++	} else /* bits_per_pixel == 8, need to enable pallete table */
++		pix_fmt = 0x00000400;
++
++	return pix_fmt;
++}
++EXPORT_SYMBOL(platform_get_pixel_format);
++
++void platform_set_gamma_table(int monitor_port, char *gamma_table_base)
++{
++}
++EXPORT_SYMBOL(platform_set_gamma_table);
++
++void platform_set_monitor_port(int monitor_port)
++{
++}
++EXPORT_SYMBOL(platform_set_monitor_port);
++
++void platform_set_pixel_clock(unsigned int pixclock)
++{
++	u32 * clkdvdr, temp;
++	/* variables for pixel clock calcs */
++	unsigned long  bestval, bestfreq, speed_ccb, minpixclock, maxpixclock, pixval;
++	long err;
++	int i;
++
++	clkdvdr = (u32 *)ioremap(get_immrbase() + 0xf0c, sizeof(u32));
++
++	/* Pixel Clock configuration */
++	DPRINTK("DIU: Bus Frequency = %d\n",get_busfreq());
++	speed_ccb = get_busfreq() * 4;
++
++	/* Calculate the pixel clock with the smallest error */
++	/* calculate the following in steps to avoid overflow */
++	DPRINTK("DIU pixclock in ps - %d\n",pixclock);
++	temp = 1;
++	temp *= 1000000000;
++	temp /= pixclock;
++	temp *= 1000;
++	pixclock = temp;
++	DPRINTK("DIU pixclock freq - %lu\n",pixclock);
++
++	temp *= 5;
++	temp /= 100;  /* pixclock * 0.05 */
++	DPRINTK("deviation = %d\n", temp);
++	minpixclock = pixclock - temp;
++	maxpixclock = pixclock + temp;
++	DPRINTK("DIU minpixclock - %lu\n", minpixclock);
++	DPRINTK("DIU maxpixclock - %lu\n", maxpixclock);
++	pixval = speed_ccb/pixclock;
++	DPRINTK("DIU pixval = %lu\n",pixval);
++
++	err = 100000000;
++	bestval = pixval;
++	DPRINTK("DIU bestval = %lu\n", bestval);
++
++	bestfreq = 0;
++	for (i = -1; i <= 1; i++) {
++		temp = speed_ccb / (pixval+i);
++		DPRINTK("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",i,pixval,temp);
++		if ((temp < minpixclock) || (temp > maxpixclock))
++			DPRINTK("DIU exceeds monitor range (%lu to %lu)\n",
++				minpixclock,maxpixclock);
++		else if (abs(temp - pixclock) < err) {
++		  DPRINTK("Entered the else if block %d\n", i);
++			err = abs(temp - pixclock);
++			bestval = pixval+i;
++			bestfreq = temp;
++		}
++	}
++
++	DPRINTK("DIU chose = %lx\n", bestval);
++	DPRINTK("DIU error = %ld\n NomPixClk ", err);
++	DPRINTK("DIU: Best Freq = %lx\n",bestfreq);
++	/* Modify PXCLK in GUTS CLKDVDR */
++	DPRINTK("DIU: Current value of CLKDVDR = 0x%08x\n",(*clkdvdr));
++	temp = (* clkdvdr) & 0xffffff00;
++	* clkdvdr = temp | (bestval & 0xFF);
++	DPRINTK("DIU: Modified value of CLKDVDR = 0x%08x\n",(*clkdvdr));
++}
++EXPORT_SYMBOL(platform_set_pixel_clock);
++
++ssize_t platform_show_monitor_port(int monitor_port, char * buf)
++{
++	return snprintf(buf, PAGE_SIZE, "0 - 5121ads DVI & LCD\n");
++}
++EXPORT_SYMBOL(platform_show_monitor_port);
++
++int platform_set_sysfs_monitor_port(int val)
++{
++	return 0;
++}
++EXPORT_SYMBOL(platform_set_sysfs_monitor_port);
++
++static void __init preallocate_diu_videomemory(void)
++{
++#if DISABLE_RH_MEMORY
++#else
++	printk(KERN_INFO "%s: diu_size=%lu\n", __FUNCTION__, diu_size);
++
++	diu_mem = __alloc_bootmem(diu_size, 8, 0);
++
++	if (!diu_mem) {
++		printk(KERN_ERR "fsl-diu: cannot allocate %lu bytes\n",
++			diu_size);
++		return;
++	}
++
++	printk(KERN_INFO "%s: diu_mem=%p\n", __FUNCTION__, diu_mem);
++
++	rh_init(&diu_rh_info, 4096, ARRAY_SIZE(diu_rh_block), diu_rh_block);
++	rh_attach_region(&diu_rh_info, (unsigned long) diu_mem, diu_size);
++#endif
++}
++
++void *fsl_diu_alloc(unsigned long size, unsigned long *phys)
++{
++	 void *virt;
++#if DISABLE_RH_MEMORY
++	virt=dma_alloc_coherent(NULL, size,
++                       phys, GFP_KERNEL|GFP_DMA);
++#else
++
++	 printk(KERN_ERR "%s: size=%lu\n", __FUNCTION__, size);
++	 if (!diu_mem) {
++		printk(KERN_INFO "%s: no diu_mem\n", __FUNCTION__);
++		return NULL;
++	 }
++
++	 virt = (void *) rh_alloc(&diu_rh_info, size, "DIU");
++	 if (virt)
++		*phys = virt_to_bus(virt);
++
++	 printk(KERN_DEBUG "%s:%u rh virt=%p phys=%lx\n",
++			 __FUNCTION__, __LINE__, virt, *phys);
++#endif
++	 return virt;
++}
++EXPORT_SYMBOL(fsl_diu_alloc);
++
++void fsl_diu_free(void *p, unsigned long size)
++{
++#if DISABLE_RH_MEMORY
++	if(!p)return;
++	dma_free_coherent(0, size, p, 0);
++#else
++	printk(KERN_DEBUG "%s: p=%p size=%lu\n", __FUNCTION__, p, size);
++
++	if (!p)
++		return;
++
++	if ((p >= diu_mem) && (p < (diu_mem + diu_size))) {
++		printk(KERN_DEBUG "%s:%u rh\n", __FUNCTION__, __LINE__);
++		rh_free(&diu_rh_info, (unsigned long) p);
++	} else {
++		printk(KERN_DEBUG "%s:%u dma\n", __FUNCTION__, __LINE__);
++		dma_free_coherent(0, size, p, 0);
++	}
++#endif
++}
++EXPORT_SYMBOL(fsl_diu_free);
++
++static int __init early_parse_diufb(char *p)
++{
++	if (!p)
++		return 1;
++
++	diu_size = _ALIGN_UP(memparse(p, &p), 8);
++
++	printk(KERN_INFO "%s: diu_size=%lu\n", __FUNCTION__, diu_size);
++
++	return 0;
++}
++early_param("diufb", early_parse_diufb);
++
++#else
++
++#define preallocate_diu_videomemory() do { } while (0)
++
++#endif
++
++/**
++ * 	mpc512x_find_ips_freq - Find the IPS bus frequency for a device
++ * 	@node:	device node
++ *
++ * 	Returns IPS bus frequency, or 0 if the bus frequency cannot be found.
++ */
++unsigned long
++mpc512x_find_ips_freq(struct device_node *node)
++{
++	struct device_node *np;
++	const unsigned int *p_ips_freq = NULL;
++
++	of_node_get(node);
++	while (node) {
++		p_ips_freq = of_get_property(node, "bus-frequency", NULL);
++		if (p_ips_freq)
++			break;
++
++		np = of_get_parent(node);
++		of_node_put(node);
++		node = np;
++	}
++	if (node)
++		of_node_put(node);
++
++	return p_ips_freq ? *p_ips_freq : 0;
++}
++EXPORT_SYMBOL(mpc512x_find_ips_freq);
++#define DEFAULT_FIFO_SIZE 16
++
++static unsigned int get_fifo_size(struct device_node *np, int psc_num, char *fifo_name)
++{
++	const unsigned int *fp;
++
++	fp = of_get_property(np, fifo_name, NULL);
++	if (fp)
++		return *fp;
++	printk(KERN_WARNING "no %s property for psc%d defaulting to %d\n",
++		fifo_name, psc_num, DEFAULT_FIFO_SIZE);
++	return DEFAULT_FIFO_SIZE;
++}
++
++static int psc_fifo_base[12];
++static void mpc5125_psc_fifo_init(char *name)
++{
++	struct device_node *np;
++	const u32 *cell_index;
++	int fifobase = 0; /* current fifo address in 32 bit words */
++	char *default_psc = "fsl,mpc5125-psc";
++	char *psc_name;
++
++	if (name)
++		psc_name = name;
++	else
++		psc_name = default_psc;
++
++	for_each_compatible_node(np, NULL, psc_name) {
++		cell_index = of_get_property(np, "cell-index", NULL);
++		if (cell_index) {
++			int psc_num = *cell_index;
++			unsigned int tx_fifo_size;
++			unsigned int rx_fifo_size;
++			void __iomem *psc;
++
++			tx_fifo_size = get_fifo_size(np, psc_num, "tx-fifo-size");
++			rx_fifo_size = get_fifo_size(np, psc_num, "rx-fifo-size");
++
++			/* size in register is in 4 byte words */
++			tx_fifo_size /= 4;
++			rx_fifo_size /= 4;
++
++			psc = of_iomap(np, 0);
++
++			if(strcmp(psc_name, default_psc)) {
++				fifobase = psc_fifo_base[psc_num];
++				/* tx fifo size register is at 0x9c and rx at 0xdc */
++				out_be32(psc + 0x9c, (fifobase << 16) | tx_fifo_size);
++				fifobase += tx_fifo_size;
++				out_be32(psc + 0xdc, (fifobase << 16) | rx_fifo_size);
++			} else {
++				psc_fifo_base[psc_num] = fifobase;
++				/* tx fifo size register is at 0x9c and rx at 0xdc */
++				out_be32(psc + 0x9c, (fifobase << 16) | tx_fifo_size);
++				fifobase += tx_fifo_size;
++				out_be32(psc + 0xdc, (fifobase << 16) | rx_fifo_size);
++				fifobase += rx_fifo_size;
++			}
++			printk("PSC%d psc_fifo_base:%d tx_fifo_size:%08x rx_fifo_size:%08x\n",psc_num,psc_fifo_base[psc_num],tx_fifo_size,rx_fifo_size);
++			/* reset and enable the slices */
++			out_be32(psc + 0x80, 0x80);
++			out_be32(psc + 0x80, 0x01);
++			out_be32(psc + 0xc0, 0x80);
++			out_be32(psc + 0xc0, 0x01);
++
++			iounmap(psc);
++		}
++	}
++}
++static void mpc5125_psc_iopad_init(void __iomem *ioctl, char *name)
++{
++	struct device_node *np;
++	const u32 *cell_index;
++	char *default_psc = "fsl,mpc5125-psc";
++	char *psc_name;
++
++	if (name)
++		psc_name = name;
++	else
++		psc_name = default_psc;
++
++	for_each_compatible_node(np, NULL, psc_name) {
++		cell_index = of_get_property(np, "cell-index", NULL);
++		if (cell_index) {
++			u8 __iomem *pscioctl;
++			int psc_num = *cell_index;
++			if(psc_num>1)continue;
++			pscioctl = ioctl + 0x76+5*psc_num;
++			out_8(pscioctl++, 0x07);
++			out_8(pscioctl++, 0x03);
++			out_8(pscioctl++, 0x03);
++			out_8(pscioctl++, 0x03);
++			out_8(pscioctl++, 0x03);
++		}
++	}
++}
++
++void mpc5121ads_diu_io_pm_restore(void)
++ {
++        struct device_node *np;
++#ifndef CONFIG_MPC5125_TWR
++#define DIU_CLK                0x284
++#define DIU_HSYN       0x288
++#define DIU_IO_OFFSET  0x294
++#define DIU_IO_SIZE    0x68
++#else
++#define DIU_CLK                0x2f
++#define DIU_DE			0x30
++#define DIU_HSYN		0x31
++#define DIU_VSYN		0x32
++#endif
++        /*
++         * io pad config
++       */
++       np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ioctl");
++	if(!np)
++		np = of_find_compatible_node(NULL, NULL, "fsl,mpc5125-ioctl");
++        if (np) {
++#ifndef CONFIG_MPC5125_TWR
++                void __iomem *ioctl = of_iomap(np, 0);
++               int i, count = DIU_IO_SIZE / 4;
++               u32 *reg;
++
++               reg = ioctl + DIU_CLK;
++               *reg = 0x107;
++               reg = ioctl + DIU_HSYN;
++               *reg = 0x103;
++               reg = ioctl + DIU_IO_OFFSET;
++               for (i = 0; i < count; i++)
++                       *reg++ = 0x103;
++#else
++		 u8 __iomem *ioctl = of_iomap(np, 0);
++		out_8(ioctl + DIU_CLK,0x07);
++		out_8( ioctl + DIU_DE,0x03);
++		out_8(ioctl + DIU_HSYN,0x03);
++		out_8(ioctl + DIU_VSYN,0x03);
++
++#endif
++               mpc5125_psc_iopad_init(ioctl, "fsl,mpc5125-psc-ac97");
++
++                of_node_put(np);
++               iounmap(ioctl);
++        }
++}
++
++EXPORT_SYMBOL(mpc5121ads_diu_io_pm_restore);
++
++void mpc5121ads_ac97_pm_restore(void)
++{
++	struct device_node *np;
++
++	/*
++	 * io pad config
++	 */
++	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5125-ioctl");
++	if (np) {
++		void __iomem *ioctl = of_iomap(np, 0);
++
++		mpc5125_psc_iopad_init(ioctl, "fsl,mpc5125-psc-ac97");
++
++		of_node_put(np);
++		iounmap(ioctl);
++	}
++
++	mpc5125_psc_fifo_init("fsl,mpc5125-psc-ac97");
++}
++EXPORT_SYMBOL(mpc5121ads_ac97_pm_restore);
++#if CONFIG_PPC_MPC5125
++static void mpc5125_can_io_controller_init(void)
++{
++	/*can1_tx psc9 pin 0*/
++	/*mpc5125_psc_io_controller_set(9, 0, 0x03);*/
++	/*can2_tx psc9 pin 1*/
++	/*mpc5125_psc_io_controller_set(9, 1, 0xc3);*/
++}
++#endif
++static void __init mpc5125_board_setup(void)
++{
++	struct device_node *np;
++	void __iomem *i2cctl;
++
++	/*
++	 * io pad config
++	 */
++	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5125-ioctl");
++	if (np) {
++		void __iomem *ioctl = of_iomap(np, 0);
++
++		mpc5125_psc_iopad_init(ioctl, NULL);
++		/*mpc5121_can_iopad_init(ioctl);*/
++
++		of_node_put(np);
++		iounmap(ioctl);
++	}
++	mpc5125_psc_fifo_init(NULL);
++}
++/*
++	isusb:0 init as fec2
++	isusb:1 init as usb
++*/
++void mpc5125_fec2_usb_io_init(unsigned char isusb)
++{
++	unsigned int offset[]={0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a,
++		0x6b,0x6c,0x6d,0x6e
++		};
++	unsigned char usb_init[]={0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,
++		0x03,0x03,0x03,0x03
++		};
++	unsigned char fec2_init[]={	0x43,0x43,0x43,0x43,0x43,0x43,0x43,0x43,
++		0x43,0x43,0x43,0x43
++		};
++	unsigned int i;
++	for(i=0;i<sizeof(offset)/sizeof(offset[0]);i++)
++	{
++		mpc5125_io_controller_set(offset[i],(isusb)?usb_init[i]:fec2_init[i]);
++	}
++}
++EXPORT_SYMBOL(mpc5125_fec2_usb_io_init);
++extern int __init ads5121_pm_init(void);
++static void __init mpc5125_ads_setup_arch(void)
++{
++	printk(KERN_INFO "MPC5125 ADS board from Freescale Semiconductor\n");
++
++	preallocate_diu_videomemory();
++	mpc5125_board_setup();
++#if CONFIG_PPC_MPC5125
++	mpc5125_can_io_controller_init();
++#endif
++
++#ifdef CONFIG_PM
++#ifdef CONFIG_MPC5121_ADS_HIB
++	ads5121_pm_init();
++#else
++	mpc512x_pm_init();
++#endif
++#endif
++
++}
++
++static struct of_device_id __initdata of_bus_ids[] = {
++	{ .name = "soc", },
++	{ .name = "localbus", },
++	{ .compatible = "fsl,mpc5125-nfc", },
++	{},
++};
++
++static void __init mpc5125_ads_declare_of_platform_devices(void)
++{
++	if (of_platform_bus_probe(NULL, of_bus_ids, NULL))
++		printk(KERN_ERR __FILE__ ": "
++			"Error while probing of_platform bus\n");
++}
++
++static void __init mpc5125_ads_init_IRQ(void)
++{
++	struct device_node *np;
++
++	np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
++	if (!np)
++		return;
++
++	ipic_init(np, 0);
++	of_node_put(np);
++
++	/*
++	 * Initialize the default interrupt mapping priorities,
++	 * in case the boot rom changed something on us.
++	 */
++	ipic_set_default_priority();
++}
++
++/*
++ * Called very early, MMU is off, device-tree isn't unflattened
++ */
++static int __init mpc5125_ads_probe(void)
++{
++	unsigned long root = of_get_flat_dt_root();
++
++	return of_flat_dt_is_compatible(root, "fsl,mpc5125ads");
++}
++
++define_machine(mpc5125_ads) {
++	.name			= "MPC5125 ADS",
++	.probe			= mpc5125_ads_probe,
++	.setup_arch		= mpc5125_ads_setup_arch,
++	.init			= mpc5125_ads_declare_of_platform_devices,
++	.init_IRQ		= mpc5125_ads_init_IRQ,
++	.get_irq		= ipic_get_irq,
++	.calibrate_decr		= generic_calibrate_decr,
++};
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/mpc512x_pm.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc512x_pm.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/mpc512x_pm.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc512x_pm.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,602 @@
++/*
++ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Description:
++ * This file contains power management code for MPC5121eADS
++ *
++ * This file is part of the Linux kernel
++ *
++ * This is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/suspend.h>
++#include <linux/of_platform.h>
++#include <asm/time.h>
++#include <asm/mpc512x.h>
++#include <asm/ipic.h>
++#include <asm/reg.h>
++#include <sysdev/fsl_soc.h>
++
++#include "mpc512x_pm.h"
++
++#include <linux/delay.h>
++
++
++struct mpc512x_pm mpc512x_pm_data;
++static u32 mpc512x_targeted_state = MPC512x_PM_NONE;
++
++/*
++ * Name       : mpc512x_clrevents
++ * Desc       : This function clears the GPIo events and the CAN events
++ *
++ * Parameters : void
++ * Return     : void
++ */
++void  mpc512x_clrevents(struct mpc512x_pm *p_pmdata)
++{
++
++	u32	*gpio, reg;
++	u8	*mscan = NULL;
++
++	gpio = (u32 *)((u32)p_pmdata->mbar + MPC512x_IMMRBAR_GPIO_OFFSET);
++	mscan = (u8 *)((u32)p_pmdata->mbar + MPC512x_IMMRBAR_MSCAN_OFFSET);
++
++	reg = in_be32(&gpio[MPC512x_GPIO_GPIER >> 2]);
++	out_be32(&gpio[MPC512x_GPIO_GPIER >> 2], reg);
++}
++
++/*
++ * Name       : mpc512x_pm_setup
++ * Desc       : This function is called to setup and map the IO region.
++ *
++ * Parameters : struct mpc512x_pm *p_pmdata
++ * Return     : void
++ */
++int mpc512x_pm_setup(struct mpc512x_pm *p_pmdata)
++{
++	memset(p_pmdata, 0, sizeof(struct mpc512x_pm));
++
++	p_pmdata->mbar = ioremap(get_immrbase(), MPC512x_IMMRBAR_MEM_MAPPED);
++	if (!p_pmdata->mbar) {
++		printk(KERN_ERR "Error mapping MBAR registers\n");
++		return -1;
++	}
++#ifdef CONFIG_MPC5121_PM_TEST
++	mpc512x_pm_test_setup();
++#endif
++	return 0;
++}
++
++/*
++ * Name       : mpc512x_pm_release
++ * Desc       : This is called to unmap/release the allocated resources.
++ *
++ * Parameters : void
++ * Return     : void
++ */
++void mpc512x_pm_release(struct mpc512x_pm *p_pmdata)
++{
++	unsigned long flags;
++	if (!p_pmdata->mbar)
++		return;
++	local_irq_save(flags);
++	iounmap(p_pmdata->mbar);
++	memset(p_pmdata, 0, sizeof(struct mpc512x_pm));
++	local_irq_restore(flags);
++}
++
++/*
++ * Name       : mpc512x_sleep
++ * Desc       : This function is called to enter the Sleep mode by setting the
++ *		[SLEEP] bit in HID0 and [POW] bit in MSR.
++ *
++ * Parameters : void
++ * Return     : void
++ */
++static void mpc512x_sleep(void)
++{
++	u32 hid0, msr;
++
++	/* Enable SLEEP mode and disable the rest */
++	hid0 = mfspr(SPRN_HID0);
++	mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP
++			 | HID0_DPM)) | HID0_SLEEP);
++	asm volatile("isync" : : : "memory");
++	asm volatile("sync" : : : "memory");
++
++	msr = mfmsr();
++	mtmsr(msr | MSR_EE);
++	asm volatile("isync" : : : "memory");
++	asm volatile("sync" : : : "memory");
++
++	/* Enter Sleep mode*/
++	msr = mfmsr();
++	mtmsr(msr | MSR_POW);
++	asm volatile("isync" : : : "memory");
++	asm volatile("sync" : : : "memory");
++
++	msr = mfmsr();
++	mtmsr(msr & ~MSR_EE);
++	asm volatile("isync" : : : "memory");
++	asm volatile("sync" : : : "memory");
++
++	/* Disable sleep modes */
++	hid0 = mfspr(SPRN_HID0);
++	mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_SLEEP)));
++	asm volatile("isync" : : : "memory");
++	asm volatile("sync" : : : "memory");
++}
++/*
++ * Name       : mpc512x_pmc_clrevent
++ * Desc       : This function needs to be called by the interrupt handlers of
++ * 		the wakeup sources. This is needed since a PMC interrupt is
++ *		not guaranteed on MPC5121 v1.0, while an interrupt from the
++ * 		wakeup source (GPIO / CAN) is.
++ *
++ * Parameters : void
++ * Return     : void
++ */
++void mpc512x_pmc_clrevent(void)
++{
++	struct mpc512x_pmc *pmc;
++
++	if(mpc512x_pm_data.mbar){
++		pmc = (struct mpc512x_pmc *)((u32)mpc512x_pm_data.mbar +
++					MPC512x_IMMRBAR_PMC_OFFSET);
++		if(in_be32(&pmc->pmc_er)& 0x1){
++			out_be32(&pmc->pmc_er, 0x1);
++		}
++		out_be32(&pmc->pmc_er, 0x7);
++	}
++}
++EXPORT_SYMBOL_GPL(mpc512x_pmc_clrevent);
++
++/*
++ * Name       : mpc512x_set_gpio_wakeup
++ * Desc       : This function would initialise the gpio with the given detection mode
++ * 		and enable the interrupt.
++ *
++ * Parameters :
++ * Return     : int
++ */
++int mpc512x_set_gpio_wakeup(unsigned int gpio_num, unsigned int detect_mode)
++{
++	volatile u32 reg;
++	u32 __iomem *gpio;
++
++	gpio = ioremap((u32)get_immrbase() + MPC512x_IMMRBAR_GPIO_OFFSET,
++			 MPC512x_GPIO_MEM_MAP);
++	if (!gpio) {
++		printk("GPIO memory could not be mapped. \n");
++		return -1;
++	}
++	gpio_num = 31 - gpio_num;
++	reg = in_be32(&gpio[MPC512x_GPIO_IMR >> 2]);
++	reg |= 1 << gpio_num;
++	out_be32(&gpio[MPC512x_GPIO_IMR >> 2], reg);
++
++	reg = in_be32(&gpio[MPC512x_GPIO_ICR1 >> 2]);
++	reg &= ~(0x3 << (gpio_num * 2));
++	reg |= ((detect_mode & 3)<< (gpio_num * 2));
++	out_be32(&gpio[MPC512x_GPIO_ICR1 >> 2], reg);
++
++	iounmap(gpio);
++	return 0;
++}
++
++EXPORT_SYMBOL_GPL(mpc512x_set_gpio_wakeup);
++
++/*
++ * Name       : mpc512x_pm_valid
++ * Desc       : Checks whether the PM state is valid
++ *
++ * Parameters : void
++ * Return     : 1 - Valid , 0 - Invalid
++ */
++static int mpc512x_pm_valid(suspend_state_t state)
++{
++	switch(state){
++	case PM_SUSPEND_STANDBY:
++	case PM_SUSPEND_MEM:
++		return 1;
++	default:
++		return 0;
++	}
++}
++
++/*
++ * Name       : mpc512x_pm_settarget
++ * Desc       : Set the state to which the system is to enter.
++ *
++ * Parameters : void
++ * Return     : 0 - Success
++ */
++static int mpc512x_pm_settarget(suspend_state_t state)
++{
++	switch(state){
++	case PM_SUSPEND_STANDBY:
++		mpc512x_targeted_state = MPC512x_PM_STANDBY;
++		break;
++	case PM_SUSPEND_MEM:
++		mpc512x_targeted_state = MPC512x_PM_SUSP_MEM;
++		break;
++	default:
++		mpc512x_targeted_state = MPC512x_PM_NONE;
++	}
++	return 0;
++}
++
++/*
++ * Name       : mpc512x_set_ipic_regs
++ * Desc       : Save the IPIC Mask registers and enable the wakeup interrupts
++ *
++ * Parameters : void
++ * Return     : void
++ */
++static void mpc512x_set_ipic_regs(struct mpc512x_pm *p_pmdata)
++{
++	u32 *ipic = (u32 *)((u32)p_pmdata->mbar +
++					MPC512x_IMMRBAR_IPIC_OFFSET);
++
++	/* Save the current IPIC mask register values. */
++	p_pmdata->ipic_simsr_h = in_be32(&ipic[IPIC_SIMSR_H >> 2]);
++	p_pmdata->ipic_simsr_l = in_be32(&ipic[IPIC_SIMSR_L >> 2]);
++
++	/* Disable all the interrupts except the wakeup sources */
++	out_be32(&ipic[IPIC_SIMSR_H >> 2], MPC512x_IPIC_MSRH_MSCAN1
++					 | MPC512x_IPIC_MSRH_MSCAN2);
++	out_be32(&ipic[IPIC_SIMSR_L >> 2], MPC512x_IPIC_MSRL_RTCSEC |
++					MPC512x_IPIC_MSRL_PMC |  MPC512x_IPIC_MSRL_GPIO);
++}
++
++/*
++ * Name       : mpc512x_restore_ipic_regs
++ * Desc       : Restore the IPIC Mask registers to original values.
++ *
++ * Parameters : void
++ * Return     : void
++ */
++static void mpc512x_restore_ipic_regs(struct mpc512x_pm *p_pmdata)
++{
++	u32 *ipic = (u32 *)((u32)p_pmdata->mbar +
++					MPC512x_IMMRBAR_IPIC_OFFSET);
++	/* Restore the IPIC masks to saved values */
++	out_be32(&ipic[IPIC_SIMSR_L >> 2], p_pmdata->ipic_simsr_l );
++	out_be32(&ipic[IPIC_SIMSR_H >> 2], p_pmdata->ipic_simsr_h);
++}
++/*
++ * Name       : mpc512x_set_rtc_wakeup
++ * Desc       : This Function would set up the Wake-Up source configurations
++ * in the RTC registers. The RTC interrupts would be generated for GPIO[28-31]
++ * and CAN 1 & 2 receive Interrupts.
++ *
++ * Parameters : void
++ * Return     : void
++ */
++static void mpc512x_set_rtc_wakeup(struct mpc512x_pm *p_pmdata)
++{
++	u32 rtc_reg;
++	u32 *rtc;
++	u32 alm_hr, alm_min, cur_hr, cur_min;
++	int offset_minutes;
++
++	if (!p_pmdata->mbar)
++		return;
++
++	rtc = (u32 *)((u32)p_pmdata->mbar + MPC512x_IMMRBAR_RTC_OFFSET);
++
++	rtc_reg = in_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2]);
++	p_pmdata->rtc_keepalive = rtc_reg;
++
++	/* Set the Active LVL values for the Wake-up Sources[1-5] */
++	rtc_reg |= MPC512x_RTCKAR_WKUP_SRCLVL;
++	out_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2], rtc_reg);
++
++	/* Enable the Wake-Up sources and disable Hibernate mode. */
++	rtc_reg |= (MPC512x_RTCKAR_WKUP_SRCEN | MPC512x_RTCKAR_DIS_HIBMODE);
++	out_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2], rtc_reg);
++
++	/* Set the Target Time Register to a Future Value */
++	p_pmdata->rtc_targettime = in_be32(&rtc[MPC512x_RTC_TTR >> 2]);
++
++	rtc_reg = in_be32(&rtc[MPC512x_RTC_AIER >> 2]);
++
++	if (rtc_reg & MPC512x_RTCAIER_ALMEN_MASK) {
++		/*Alarm was set.. Let us wakeup in that time..*/
++		alm_hr = (rtc_reg >> MPC512x_RTC_HR_OFFSET)
++			    & MPC512x_RTC_HR_MASK;
++		alm_min = (rtc_reg >> MPC512x_RTC_MIN_OFFSET)
++			    & MPC512x_RTC_MIN_MASK;
++		rtc_reg = in_be32(&rtc[MPC512x_RTC_CTR >> 2]);
++		cur_min = (rtc_reg >> MPC512x_RTC_MIN_OFFSET)
++			    & MPC512x_RTC_MIN_MASK;
++
++		if (in_be32(&rtc[MPC512x_RTC_TSR >> 2])
++			    & MPC512x_RTCTSR_SLCHR_MASK) {
++			/* 12 Hour Format*/
++			cur_hr = (rtc_reg >> MPC512x_RTC_HR_OFFSET) & 0xF;
++			if (rtc_reg & MPC512x_RTC_CTR_PM)
++				cur_hr += 12;
++		} else
++			cur_hr = (rtc_reg >> MPC512x_RTC_HR_OFFSET)
++			    & MPC512x_RTC_HR_MASK;
++		offset_minutes = (alm_hr * MPC512x_RTC_MINS_PER_HR + alm_min) -
++				(cur_hr * MPC512x_RTC_MINS_PER_HR + cur_min);
++
++		if (offset_minutes > 0) {
++			out_be32(&rtc[MPC512x_RTC_TTR >> 2],
++				in_be32(&rtc[MPC512x_RTC_ATR >> 2]) +
++				(offset_minutes * MPC512x_RTC_MINS_PER_HR));
++		} else
++			out_be32(&rtc[MPC512x_RTC_TTR >> 2],
++				    MPC512x_RTCTTR_MAXTIMEOUT);
++	} else
++		out_be32(&rtc[MPC512x_RTC_TTR >> 2], MPC512x_RTCTTR_MAXTIMEOUT);
++
++}
++
++static void mpc512x_restore_rtc_regs(struct mpc512x_pm *p_pmdata)
++{
++	u32 *rtc;
++
++	if (!p_pmdata->mbar)
++		return;
++
++	rtc = (u32 *)((u32)p_pmdata->mbar + MPC512x_IMMRBAR_RTC_OFFSET);
++
++	/* Restore the RTC Registers */
++	out_be32(&rtc[MPC512x_RTC_KEEPALIVE >> 2],
++				 p_pmdata->rtc_keepalive);
++	out_be32(&rtc[MPC512x_RTC_TTR >> 2], p_pmdata->rtc_targettime);
++}
++
++/*
++ * Name       : mpc512x_set_ddr_selfrefresh
++ * Desc       : Set the DDRC SELFREFRESH registers, to enter and exit
++ *		DDR Self Refresh mode on entering Deep Sleep mode.
++ *
++ * Parameters : void
++ * Return     : void
++ */
++static void mpc512x_set_ddr_selfrefresh(struct mpc512x_pm *p_pmdata)
++{
++	struct ddr512x *ddrc;
++
++	if (!p_pmdata->mbar)
++		return;
++
++	ddrc = (struct ddr512x *)((u32)p_pmdata->mbar +
++					MPC512x_IMMRBAR_DDRC_OFFSET);
++
++	p_pmdata->ddrc_sysconfig = in_be32(&ddrc->ddr_sys_config);
++
++	/* Write the register contents with SELF-REFRESH EN bit set.*/
++	out_be32(&ddrc->ddr_sys_config,	p_pmdata->ddrc_sysconfig
++					 | MPC512x_DDRC_SELFREFEN);
++
++	/* Set the Self Refresh Entry Commands */
++	out_be16(&ddrc->self_refresh_cmd_0, MPC512x_DDRC_SELF_REF_CMD0);
++	out_be16(&ddrc->self_refresh_cmd_1, MPC512x_DDRC_SELF_REF_CMD1);
++	out_be16(&ddrc->self_refresh_cmd_2, MPC512x_DDRC_SELF_REF_CMD2);
++	out_be16(&ddrc->self_refresh_cmd_3, MPC512x_DDRC_SELF_REF_CMD3);
++
++	/* Set the Self Refresh Exit Commands */
++	out_be16(&ddrc->self_refresh_cmd_4, MPC512x_DDRC_SELF_REF_CMD4);
++	out_be16(&ddrc->self_refresh_cmd_5, MPC512x_DDRC_SELF_REF_CMD5);
++	out_be16(&ddrc->self_refresh_cmd_6, MPC512x_DDRC_SELF_REF_CMD6);
++	out_be16(&ddrc->self_refresh_cmd_7, MPC512x_DDRC_SELF_REF_CMD7);
++}
++
++static void mpc512x_restore_ddr_regs(struct mpc512x_pm *p_pmdata)
++{
++	struct ddr512x *ddrc;
++
++	if (!p_pmdata->mbar)
++		return;
++
++	ddrc = (struct ddr512x *)((u32)p_pmdata->mbar +
++					MPC512x_IMMRBAR_DDRC_OFFSET);
++	out_be32(&ddrc->ddr_sys_config, p_pmdata->ddrc_sysconfig);
++}
++
++void mpc512x_prepare_deepsleep(struct mpc512x_pm *p_pmdata)
++{
++	mpc512x_set_ddr_selfrefresh(p_pmdata);
++
++	/*
++	 *  Enable the wakeup sources and set RTC Target Time
++	 *  to future
++	 */
++	mpc512x_set_rtc_wakeup(p_pmdata);
++
++#ifdef CONFIG_PPC_MPC5125
++	struct mpc512x_pmc *pmc;
++	pmc = (struct mpc512x_pmc *)((u32)p_pmdata->mbar +
++					MPC512x_IMMRBAR_PMC_OFFSET);
++	out_be32(&pmc->pmc_wse,0xff);
++	out_be32(&pmc->pmc_wsp,0x00);
++	mpc512x_set_gpio_wakeup(0, 3);
++#endif
++//	mpc512x_set_gpio_wakeup(31, 3);
++}
++
++void mpc512x_finish_deepsleep(struct mpc512x_pm *p_pmdata)
++{
++	/* Restore the DDR and RTC registers on wake-up.*/
++	mpc512x_restore_ddr_regs(p_pmdata);
++	mpc512x_restore_rtc_regs(p_pmdata);
++
++}
++
++/*
++ * Name       : mpc512x_pm_prepare
++ * Desc       : This function would map the IO regions. Also sets the DDRC and
++ * 		RTC regs for Deep Sleep Mode.
++ *
++ * Parameters : void
++ * Return     : int
++ *		ENOSYS
++ *
++ */
++static int mpc512x_pm_prepare(void)
++{
++	mpc512x_pm_setup(&mpc512x_pm_data);
++
++	switch(mpc512x_targeted_state) {
++	case MPC512x_PM_STANDBY:
++		mpc512x_prepare_deepsleep(&mpc512x_pm_data);
++		break;
++	case MPC512x_PM_SUSP_MEM:
++		mpc512x_prepare_deepsleep(&mpc512x_pm_data);
++		break;
++	}
++	return 0;
++}
++
++/*
++ * Name       : mpc512x_enter_deepsleep
++ * Desc       : This function puts the MPC5121e system to Deep-Sleep State. The
++ *		Core is first put to sleep. After this the H/W sequencers take
++ *		the system to Deep-Sleep. Before entering the Deep-
++ *		Sleep state the Wake-Up sources are set for GPIO[28-31] and CAN
++ *		1 & 2 receiver interrupts.
++ *
++ * Parameters : void
++ * Return     : int
++ *
++ */
++int mpc512x_enter_deepsleep(struct mpc512x_pm *p_pmdata)
++{
++	struct mpc512x_pmc *pmc;
++	/* Enable the GPIO and CAN Interrupts */
++	mpc512x_set_ipic_regs(p_pmdata);
++
++	/* Don't let DEC expire any time soon */
++	mtspr(SPRN_DEC, MPC512x_DEC_MAXTIMEOUT);
++
++	pmc = (struct mpc512x_pmc *)((u32)p_pmdata->mbar +
++					MPC512x_IMMRBAR_PMC_OFFSET);
++	/* Set the DSM, DDROFF & COREOFF bits in PMC CR register.*/
++	out_be32(&pmc->pmc_cr, MPC512x_PMCCR_DSMEN | MPC512x_PMCCR_DDROFF
++				 | MPC512x_PMCCR_COREOFF);
++	out_be32(&pmc->pmc_mr, MPC512x_PMCMR_PMCIE);
++
++#ifdef CONFIG_PPC_MPC5125
++	out_be32(&pmc->pmc_wse, 0x48);
++	out_be32(&pmc->pmc_wsp, 0x40);
++#endif
++
++	/* Replace the Exception handler at 0x500 with our custom
++	 * handler to clear the PMC bit.
++	 */
++	mpc5121_copy_pmcclr();
++
++	/* Put core to SLEEP so that MPC512x enters Deep-Sleep.*/
++	mpc512x_sleep();
++
++	/* Restore the Original exception handler at 0x500 */
++	mpc5121_reinstall_handler();
++
++	/* We are out of Deep Sleep.. Lets restart jiffies */
++	wakeup_decrementer();
++
++	/* clearing the events of wake-up for GPIO and CAN */
++	mpc512x_clrevents(p_pmdata);
++
++	/* Reset the PMC CR register. */
++	out_be32(&pmc->pmc_cr, 0x0);
++	out_be32(&pmc->pmc_mr, 0x0);
++
++	/* Restore the IPIC regs to their original values */
++	mpc512x_restore_ipic_regs(p_pmdata);
++	return 0;
++}
++
++/*
++ * Name       : mpc512x_pm_enter
++ * Desc       : This function is exported to the Power Management Core. This
++ *	`	function is called with the state which the system should enter.
++ *
++ * Parameters : state 	- PM_SUSPEND_STANDBY
++			- PM_SUSPEND_MEM
++ * Return     : int
++ * 		-1 : FAILED
++ *		0  : SUCCESS
++ */
++static int mpc512x_pm_enter(suspend_state_t state)
++{
++	if (!mpc512x_pm_data.mbar)
++	{
++		printk(KERN_ERR "Failed to enter PM mode as IO not mapped.\n");
++		return -1;
++	}
++
++	switch(mpc512x_targeted_state){
++	case MPC512x_PM_STANDBY:
++		mpc512x_enter_deepsleep(&mpc512x_pm_data);
++		break;
++	case MPC512x_PM_SUSP_MEM:
++		printk(KERN_ERR "Suspend to RAM not implemented\n");
++		mpc512x_enter_deepsleep(&mpc512x_pm_data);
++	default:
++		break;
++	}
++	return 0;
++}
++
++/*
++ * Name       : mpc512x_pm_finish
++ * Desc       : This routine is called by the kernel on exit from
++ * 		power down modes. Restores the DDRC and RTC regs
++ * 		suspend to memory. Also releases allocated resources.
++ *
++ * Parameters : void
++ * Return     : void
++ */
++static void mpc512x_pm_finish(void)
++{
++	switch(mpc512x_targeted_state){
++	case MPC512x_PM_STANDBY:
++		mpc512x_finish_deepsleep(&mpc512x_pm_data);
++		break;
++	case MPC512x_PM_SUSP_MEM:
++		mpc512x_finish_deepsleep(&mpc512x_pm_data);
++		break;
++	}
++	mpc512x_targeted_state = MPC512x_PM_NONE;
++
++	mpc512x_pm_release(&mpc512x_pm_data);
++}
++
++static struct platform_suspend_ops mpc512x_pm_ops = {
++	.valid		= mpc512x_pm_valid,
++	.begin	= mpc512x_pm_settarget,
++	.prepare	= mpc512x_pm_prepare,
++	.enter		= mpc512x_pm_enter,
++	.finish		= mpc512x_pm_finish,
++};
++#ifndef  CONFIG_MPC5121_ADS_HIB
++int fsl_deep_sleep(void)
++{
++	return mpc512x_targeted_state;
++}
++#endif
++/*
++ * Name       : mpc512x_pm_init
++ * Desc       : This function registers the platform_suspend_ops
++ * 		structure with the kernel.
++ *
++ * Parameters : void
++ * Return     : int
++ */
++int __init mpc512x_pm_init(void)
++{
++	suspend_set_ops(&mpc512x_pm_ops);
++	return 0;
++}
++
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/mpc512x_pm.h linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc512x_pm.h
+--- linux-2.6.29/arch/powerpc/platforms/512x/mpc512x_pm.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc512x_pm.h	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,159 @@
++/*
++ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Description:
++ * This file power management code for MPC5121eADS
++ *
++ * This file is part of the Linux kernel
++ *
++ * This is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#ifndef __MPC512x_PM_H__
++#define __MPC512x_PM_H__
++
++/* Peripheral address offsets from IMMRBAR */
++#define MPC512x_IMMRBAR_RTC_OFFSET		0xA00
++#define MPC512x_IMMRBAR_IPIC_OFFSET		0xC00
++#define MPC512x_IMMRBAR_PMC_OFFSET		0x1000
++#define MPC512x_IMMRBAR_GPIO_OFFSET		0x1100
++#define MPC512x_IMMRBAR_DDRC_OFFSET		0x9000
++#define MPC512x_IMMRBAR_CLK_OFFSET      	0x00F00
++#define MPC512x_IMMRBAR_GPT_OFFSET      	0x00B00
++#define MPC512x_IMMRBAR_FEC_OFFSET      	0x02800
++#define MPC512x_IMMRBAR_SRAM_OFFSET     	0x000C4
++#define MPC512x_IMMRBAR_MSCAN_OFFSET		0x01300
++
++/* Memory mapped by Power management module */
++#define MPC512x_IMMRBAR_MEM_MAPPED		0x10000
++#define MPC512x_GPIO_MEM_MAP			0x100
++
++/* Register offsets for RTC */
++#define MPC512x_RTC_TSR				0x00
++#define MPC512x_RTC_AIER			0x0C
++#define MPC512x_RTC_CTR				0x10
++#define MPC512x_RTC_TTR				0x20
++#define MPC512x_RTC_ATR				0x24
++#define MPC512x_RTC_KEEPALIVE			0x28
++
++/* RTC bit positions and masks*/
++#define MPC512x_RTCTSR_SLCHR_MASK		(1 << 21)
++#define MPC512x_RTCAIER_ALMEN_MASK		(1 << 24)
++#define MPC512x_RTC_CTR_PM			(1 << 20)
++#define MPC512x_RTC_HR_OFFSET			16
++#define MPC512x_RTC_HR_MASK			0x1F
++#define MPC512x_RTC_MIN_OFFSET			8
++#define MPC512x_RTC_MIN_MASK			0x3F
++#define MPC512x_RTC_MINS_PER_HR			60
++
++/* Register offsets for GPIO */
++#define MPC512x_GPIO_IMR			0x10
++#define MPC512x_GPIO_ICR1			0x14
++#define MPC512x_GPIO_ICR2			0x18
++#define MPC512x_GPIO_GPIER			0x0C
++
++/* Register offsets for MSCAN */
++#define MPC512x_MSCAN_CANRFLG			0x08
++#define MPC512x_MSCAN_CANRIER			0x09
++
++/* Bit positions in IPIC memory region */
++#define MPC512x_IPIC_MSRH_MSCAN1		(1 << 4)
++#define MPC512x_IPIC_MSRH_MSCAN2		(1 << 3)
++
++#define MPC512x_IPIC_MSRL_GPIO			(1 << 17)
++#define MPC512x_IPIC_MSRL_RTCSEC		(1 << 16)
++#define MPC512x_IPIC_MSRL_RTCALRM		(1 << 15)
++#define MPC512x_IPIC_MSRL_PMC			(1 << 12)
++
++/* Bit positions in PMC memory region */
++#define MPC512x_PMCCR_DSMEN			(1 << 2)
++#define MPC512x_PMCCR_DDROFF			(1 << 1)
++#define MPC512x_PMCCR_COREOFF			(1 << 0)
++#define MPC512x_PMCMR_PMCIE			(1 << 0)
++
++/* Bit positions in DDRC memory region */
++#define MPC512x_DDRC_SELFREFEN			(1 << 18)
++
++/* DDRC commands to set the DRAM in and out of Self Refresh */
++/* These commands have worked on the MPC5121ADS board */
++#define MPC512x_DDRC_SELF_REF_CMD0		0x3C00
++#define MPC512x_DDRC_SELF_REF_CMD1		0x4420
++#define MPC512x_DDRC_SELF_REF_CMD2		0x4210
++#define MPC512x_DDRC_SELF_REF_CMD3		0x1410
++
++#define MPC512x_DDRC_SELF_REF_CMD4		0x1C00
++#define MPC512x_DDRC_SELF_REF_CMD5		0x3C08
++#define MPC512x_DDRC_SELF_REF_CMD6		0x4200
++#define MPC512x_DDRC_SELF_REF_CMD7		0x3800
++
++/* RTC Keep alive register values*/
++#define MPC512x_RTCKAR_WKUP_SRCLVL		0x001C0000
++#define MPC512x_RTCKAR_WKUP_SRCEN		0x1F000000
++#define MPC512x_RTCKAR_DIS_HIBMODE		0x00000080
++
++/* RTC Target Time register Timeout*/
++#define MPC512x_RTCTTR_MAXTIMEOUT		0xFFFFFFFF
++
++/* Decrementer timeout */
++#define MPC512x_DEC_MAXTIMEOUT			0x7FFFFFFF
++
++/* Power Management states */
++#define MPC512x_PM_NONE				0
++#define MPC512x_PM_STANDBY			1
++#define MPC512x_PM_SUSP_MEM			2
++
++/* PMC registers*/
++struct mpc512x_pmc {
++	u32 pmc_cr;		/* Configuration register - 0x00 */
++	u32 pmc_er;		/* Event register	  - 0x04 */
++	u32 pmc_mr;		/* Mask register	  - 0x08 */
++	u32 pmc_sr;		/* Shadow register	  - 0x0C */
++#ifdef CONFIG_PPC_MPC5125
++	u32 pmc_wse;	/*MPC5125 PMC wakeup source register -0x10*/
++	u32 pmc_wsp;	/*MPC5125 PMC wakeup source polarity register -0x14*/
++#endif
++};
++
++/* Data structure used by the Power management module */
++struct mpc512x_pm{
++
++	/* Pointer to IMMRBAR (ioremaped) */
++	void __iomem *mbar;
++
++	/* Registers saved/restored by PM module */
++	u32 ipic_simsr_l;
++	u32 ipic_simsr_h;
++	u32 rtc_keepalive;
++	u32 rtc_targettime;
++	u32 ddrc_sysconfig;
++};
++
++/* Structure members used to store the resister contents
++ * for peripherals which cdont have a driver to restore.
++ */
++struct ads5121_hib_regs{
++	u32 ipic_regs[30];
++	u32 clk_regs[22];
++	u32 gpt_regs[32];
++	u32 gpio_regs[7];
++	u32 fec_regs[512];
++};
++
++int mpc512x_pm_setup(struct mpc512x_pm *p_pmdata);
++void mpc512x_pm_release(struct mpc512x_pm *p_pmdata);
++void mpc512x_prepare_deepsleep(struct mpc512x_pm *p_pmdata);
++int mpc512x_enter_deepsleep(struct mpc512x_pm *p_pmdata);
++void mpc512x_finish_deepsleep(struct mpc512x_pm *p_pmdata);
++
++extern void mpc5121_copy_pmcclr(void);
++extern void mpc5121_reinstall_handler(void);
++
++#ifdef CONFIG_MPC5121_PM_TEST
++extern void mpc512x_pm_test_setup(void);
++#endif
++
++#endif /* __MPC512x_PM_H__ */
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/mpc512x_pm_test.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc512x_pm_test.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/mpc512x_pm_test.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc512x_pm_test.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,192 @@
++/*
++ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Description:
++ * This file contains lowlevel PM test code
++ *
++ * This file is part of the Linux kernel
++ *
++ * This is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++#include <linux/interrupt.h>
++#include <linux/of_platform.h>
++#include <linux/io.h>
++#include <linux/delay.h>
++#include <asm/time.h>
++#include <asm/reg.h>
++#include <sysdev/fsl_soc.h>
++
++#define DEBUG
++
++u8 *xmscan = NULL;
++u32 *xgpio = NULL;
++u32 once = 0;
++u32 irq;
++
++extern int mpc512x_set_gpio_wakeup(unsigned int gpio_num,
++				   unsigned int detect_mode);
++extern void mpc512x_pmc_clrevent(void);
++
++static irqreturn_t mpc51xx_gpio_handler(int irq, void *dev_id)
++{
++	mpc512x_pmc_clrevent();
++	if (xgpio) {
++		out_be32((u32 *) ((u32) xgpio + 0x0C), 0xFFFFFFFF);
++#ifdef DEBUG
++		printk( " :)\n");
++#endif
++	}
++	return IRQ_HANDLED;
++}
++static irqreturn_t mpc51xx_can0_handler(int irq, void *dev_id)
++{
++	u8 *mscan = xmscan;
++	mpc512x_pmc_clrevent();
++
++	if (mscan)
++		out_8(mscan + 8, in_8(mscan + 8));
++
++#ifdef DEBUG
++	printk("c0 \n");
++#endif
++
++	return IRQ_HANDLED;
++}
++#ifndef CONFIG_MPC5125_TWR
++static irqreturn_t mpc51xx_can1_handler(int irq, void *dev_id)
++{
++	u8 *mscan = xmscan + 0x80;
++	mpc512x_pmc_clrevent();
++
++	if (mscan)
++		out_8(mscan + 8, in_8(mscan + 8));
++
++#ifdef DEBUG
++	printk("c1 \n");
++#endif
++	return IRQ_HANDLED;
++}
++
++void mpc512x_can_setup(u8 * addr)
++{
++	u32 reg = 0;
++
++	u8 *mscan = addr;
++
++	/* Enable the CAN Module */
++	reg = in_8(mscan + 0x01);
++	reg |= 0x80;		//Assert CANE
++	reg &= ~0x10;		//Deassert LISTEN
++	out_8(mscan + 1, reg);
++
++	reg = in_8(mscan);
++	reg |= 0x2;		//Sleep Req
++	out_8(mscan, reg);
++	mdelay(20);
++	reg = in_8(mscan);
++	reg |= 0x1;		//Init req
++	out_8(mscan, reg);
++
++#define MSCAN_CANIDMR0_OFFSET           0x28	/* Identifier Mask Registers */
++#define MSCAN_CANIDMR1_OFFSET           0x29	/* Identifier Mask Registers */
++#define MSCAN_CANIDMR2_OFFSET           0x2C	/* Identifier Mask Registers */
++#define MSCAN_CANIDMR3_OFFSET           0x2D	/* Identifier Mask Registers */
++#define MSCAN_CANIDMR4_OFFSET           0x38	/* Identifier Mask Registers */
++#define MSCAN_CANIDMR5_OFFSET           0x39	/* Identifier Mask Registers */
++#define MSCAN_CANIDMR6_OFFSET           0x3C	/* Identifier Mask Registers */
++#define MSCAN_CANIDMR7_OFFSET           0x3D	/* Identifier Mask Registers */
++	mdelay(20);
++	out_8(mscan + MSCAN_CANIDMR0_OFFSET, 0xFF);
++	out_8(mscan + MSCAN_CANIDMR1_OFFSET, 0xFF);
++	out_8(mscan + MSCAN_CANIDMR2_OFFSET, 0xFF);
++	out_8(mscan + MSCAN_CANIDMR3_OFFSET, 0xFF);
++	out_8(mscan + MSCAN_CANIDMR4_OFFSET, 0xFF);
++	out_8(mscan + MSCAN_CANIDMR5_OFFSET, 0xFF);
++	out_8(mscan + MSCAN_CANIDMR6_OFFSET, 0xFF);
++	out_8(mscan + MSCAN_CANIDMR7_OFFSET, 0xFF);
++
++	/* Come out of Init */
++	reg = in_8(mscan);
++	reg &= ~0x1;
++	reg |= 0x4;		//Set WUPE
++	out_8(mscan, reg);
++
++	mdelay(20);
++	/* Enabling the Interrupts for MSCAN 0 */
++	reg = in_8(mscan + 9);
++	reg |= 0xFF;
++	out_8(mscan + 9, reg);
++}
++#endif
++void mpc512x_pm_test_setup(void)
++{
++	struct device_node *ofn;
++	u32 reg;
++	u32 *clock = NULL;
++	const u32 *cell_index;
++
++	if (once == 0) {
++#ifndef CONFIG_MPC5125_TWR
++		/* Enable the BDLC/MSCAN Periperal Clock */
++		clock = ioremap((u32) get_immrbase() + 0xF00, 0x100);
++		reg = in_be32((u32 *) ((u32) clock + 0x08));
++		reg |= 0x02000000;
++		out_be32((u32 *) ((u32) clock + 0x08), reg);
++		iounmap(clock);
++
++		xgpio = ioremap((u32) get_immrbase() + 0x1100, 0x100);
++		xmscan = ioremap((u32) get_immrbase() + 0x1300, 0x100);
++
++		/*Setup the irq handlers with dummy event ids */
++		ofn = of_find_compatible_node(NULL, NULL, "fsl,mpc5125-gpio");
++		irq = irq_of_parse_and_map(ofn, 0);
++		of_node_put(ofn);
++		reg =
++		    request_irq(irq, mpc51xx_gpio_handler, IRQF_PERCPU, 		//|IRQF_DISABLED|IRQF_SHARED
++				"mpx512x_test_gpio", (void *)0);
++
++		for_each_compatible_node(ofn, NULL, "fsl,mpc5121-mscan") {
++			cell_index = of_get_property(ofn, "cell-index", NULL);
++			if (cell_index && *cell_index == 0) {
++				irq = irq_of_parse_and_map(ofn, 0);
++				reg = request_irq(irq, mpc51xx_can0_handler, IRQF_PERCPU,
++					"mpx512x_test_can0", (void *)1);
++			}
++			if (cell_index && *cell_index == 1) {
++				irq = irq_of_parse_and_map(ofn, 0);
++				reg = request_irq(irq, mpc51xx_can1_handler, IRQF_PERCPU,
++					"mpx512x_test_can1", (void *)2);
++			}
++		}
++
++	//	xgpio = ioremap((u32) get_immrbase() + 0x1100, 0x100);
++	//	xmscan = ioremap((u32) get_immrbase() + 0x1300, 0x100);
++
++		/* Setup the CAN modules for testing wakeup */
++		mpc512x_can_setup(xmscan);
++		mpc512x_can_setup(xmscan + 0x80);
++		out_be32((u32 *) ((u32) xgpio + 0xC), 0xFFFFFFFF);
++		mpc512x_set_gpio_wakeup(28, 3);
++		mpc512x_set_gpio_wakeup(29, 3);
++		mpc512x_set_gpio_wakeup(30, 3);
++		mpc512x_set_gpio_wakeup(31, 3);
++#else
++		xgpio = ioremap((u32) get_immrbase() + 0x1100, 0x100);
++
++		/*Setup the irq handlers with dummy event ids */
++		ofn = of_find_compatible_node(NULL, NULL, "fsl,mpc5125-gpio");
++		irq = irq_of_parse_and_map(ofn, 0);
++		of_node_put(ofn);
++		reg =
++		    request_irq(irq, mpc51xx_gpio_handler, IRQF_SHARED, 		//|IRQF_DISABLED|IRQF_SHARED
++				"mpx512x_test_gpio", (void *)xgpio);
++		mpc512x_set_gpio_wakeup(0, 3);
++
++#endif
++		once = 1;
++	}
++}
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/mpc512x.S linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc512x.S
+--- linux-2.6.29/arch/powerpc/platforms/512x/mpc512x.S	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc512x.S	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,117 @@
++#include <asm/reg.h>
++#include <asm/ppc_asm.h>
++#include <asm/processor.h>
++#include <asm/page.h>
++#include <asm/cache.h>
++
++#define NUM_CACHE_LINES (128*8)
++
++	/* this variable added to reserve 0x20*4 bytes.
++	 * This value has been derived by counting the
++	 * number of lines of the function "code_atzero".
++	 * In case if the size of this function increases
++	 * the number of bytes have to increased accordi-
++	 * ngly.
++	 */
++        .data
++mpc5121_data_temp:
++        .space 0x20*4
++
++        .text
++	.globl mpc5121_copy_pmcclr
++mpc5121_copy_pmcclr:
++	/* Coming here with interrupts disabled */
++	/* storing the content at 0x0 location
++	 * to mpc512_data_temp space */
++	lis     r6, CONFIG_KERNEL_START@h
++	mr	r4, r6
++	li	r3, (code_atzero_end - code_atzero)/4
++	mtctr	r3
++        lis     r3, mpc5121_data_temp@h
++        ori     r3, r3, mpc5121_data_temp@l
++	/* loops here till the counter is zero */
++loop:
++        lwz     r5, 0(r4)
++        stw     r5, 0(r3)
++        addi    r3, r3, 4
++        addi    r4, r4, 4
++        bdnz    loop
++
++	/* Copy code to Location 0x0 */
++	mr	r4, r6
++	li	r3, (code_atzero_end - code_atzero)/4
++	mtctr	r3
++	lis	r3, code_atzero@h
++	ori	r3, r3, code_atzero@l
++1:
++	lwz	r5, 0(r3)
++	stw	r5, 0(r4)
++	addi	r3, r3, 4
++	addi	r4, r4, 4
++	bdnz	1b
++
++	/* Copy the jump to 0x0 code at 0x500*/
++	lwz	r5, 0x500(r6)
++	stw	r5, 0(r6)
++	lwz	r5, 8(r6)
++	stw	r5, 0x500(r6)
++
++	/* Flush the cache */
++	lis	r3, CONFIG_KERNEL_START@h
++	ori	r3, r3, CONFIG_KERNEL_START@l
++
++	/* Let us load data starting from 0x600 loc */
++	addi	r3, r3, 0x600
++	li	r4, NUM_CACHE_LINES
++	mtctr	r4
++1:
++	lwz	r4, 0(r3)
++	addi	r3, r3, L1_CACHE_BYTES    /* Next line, please */
++	bdnz	1b
++	sync; isync
++	blr
++
++	.globl mpc5121_reinstall_handler
++mpc5121_reinstall_handler:
++
++	/* Rewrite original code at 0x500 */
++	lis	r6, CONFIG_KERNEL_START@h
++	lwz	r5, 0(r6)
++	stw	r5, 0x500(r6)
++	/* restoring content at 0x0 location */
++        mr      r4, r6
++        li      r3, (code_atzero_end - code_atzero)/4
++        mtctr   r3
++        lis     r3, mpc5121_data_temp@h
++        ori     r3, r3, mpc5121_data_temp@l
++        /* loops here till the counter is zero */
++loop1:
++        lwz     r5, 0(r3)
++        stw     r5, 0(r4)
++        addi    r3, r3, 4
++        addi    r4, r4, 4
++        bdnz    loop1
++	blr
++
++code_atzero:
++	.long 0x0  /*Space reserved for copying first word of code from 0x500 */
++	ba 0x504
++	ba 0xc  /* This code is not executed. This code is copied to 0x500 */
++	mtspr	SPRN_SPRG0, r3
++	mtspr	SPRN_SPRG1, r4
++	mfspr	r3, 311
++	addi	r3, r3, 0x1000  /* Assuming that MBAR is aligned to this size */
++	lwz	r4, 0x4(r3)
++	stw	r4, 0x4(r3)
++        /* clearing GPIO evnet registers */
++        mfspr   r3, 311
++        /* getting offset of GPIO */
++        addi    r3, r3,0x1100
++        lwz     r4, 0xC(r3)
++        stw     r4, 0xC(r3)
++	mfspr	r3, SPRN_SPRG0
++	mfspr	r4, SPRN_SPRG1
++	ba	0x0
++code_atzero_end:
++	b 	code_atzero_end   /* Should never reach here*/
++
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/mpc512x_shared.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc512x_shared.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/mpc512x_shared.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/mpc512x_shared.c	2010-04-13 20:23:26.000000000 +0200
+@@ -23,7 +23,7 @@
+ #include <asm/time.h>
+ 
+ #include "mpc512x.h"
+-
++#ifndef CONFIG_MPC5125_TWR
+ unsigned long
+ mpc512x_find_ips_freq(struct device_node *node)
+ {
+@@ -46,7 +46,7 @@
+ 	return p_ips_freq ? *p_ips_freq : 0;
+ }
+ EXPORT_SYMBOL(mpc512x_find_ips_freq);
+-
++#endif
+ void __init mpc512x_init_IRQ(void)
+ {
+ 	struct device_node *np;
+@@ -69,9 +69,16 @@
+  * Nodes to do bus probe on, soc and localbus
+  */
+ static struct of_device_id __initdata of_bus_ids[] = {
++	{ .name = "soc", },
++	{ .name = "localbus", },	
++	{ .compatible = "fsl,mpc5121-nfc", },
++	{ .compatible = "fsl,mpc5121-mbx", },
++	{},
++/*
+ 	{ .compatible = "fsl,mpc5121-immr", },
+ 	{ .compatible = "fsl,mpc5121-localbus", },
+ 	{},
++*/	
+ };
+ 
+ void __init mpc512x_declare_of_platform_devices(void)
+diff -Naur linux-2.6.29/arch/powerpc/platforms/512x/pci.c linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/pci.c
+--- linux-2.6.29/arch/powerpc/platforms/512x/pci.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/platforms/512x/pci.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,83 @@
++/*
++ * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Original copied from 83xx/pci.c:
++ *
++ *     FSL SoC setup code
++ *
++ *     Maintained by Kumar Gala (see MAINTAINERS for contact information)
++ *
++ *     This program is free software; you can redistribute  it and/or modify it
++ *     under  the terms of  the GNU General  Public License as published by the
++ *     Free Software Foundation;  either version 2 of the  License, or (at your
++ *     option) any later version.
++ */
++
++#include <linux/stddef.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/pci.h>
++#include <linux/delay.h>
++#include <linux/irq.h>
++#include <linux/module.h>
++
++#include <asm/system.h>
++#include <asm/atomic.h>
++#include <asm/io.h>
++#include <asm/pci-bridge.h>
++#include <asm/prom.h>
++#include <sysdev/fsl_soc.h>
++
++#undef DEBUG
++
++#ifdef DEBUG
++#define DBG(x...) printk(x)
++#else
++#define DBG(x...)
++#endif
++
++int __init mpc512x_add_bridge(struct device_node *dev)
++{
++	int len;
++	struct pci_controller *hose;
++	struct resource rsrc;
++	const int *bus_range;
++	int has_address = 0;
++	phys_addr_t immr = get_immrbase();
++
++	DBG("Adding PCI host bridge %s\n", dev->full_name);
++
++	/* Fetch host bridge registers address */
++	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
++
++	/* Get bus range if any */
++	bus_range = of_get_property(dev, "bus-range", &len);
++	if (bus_range == NULL || len < 2 * sizeof(int)) {
++		printk(KERN_WARNING "Can't get bus-range for %s, assume"
++		       " bus 0\n", dev->full_name);
++	}
++
++	hose = pcibios_alloc_controller(dev);
++	if (!hose)
++		return -ENOMEM;
++
++	hose->first_busno = bus_range ? bus_range[0] : 0;
++	hose->last_busno = bus_range ? bus_range[1] : 0xff;
++
++	setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0);
++
++	printk(KERN_INFO "Found MPC512x PCI host bridge at 0x%016llx. "
++	       "Firmware bus number: %d->%d\n",
++	       (unsigned long long)rsrc.start, hose->first_busno,
++	       hose->last_busno);
++
++	DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
++	    hose, hose->cfg_addr, hose->cfg_data);
++
++	/* Interpret the "ranges" property */
++	/* This also maps the I/O region and sets isa_io/mem_base */
++	pci_process_bridge_OF_ranges(hose, dev, 1);
++
++	return 0;
++}
+diff -Naur linux-2.6.29/arch/powerpc/sysdev/fsl_soc.c linux-2.6.29-v2010041601/arch/powerpc/sysdev/fsl_soc.c
+--- linux-2.6.29/arch/powerpc/sysdev/fsl_soc.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/sysdev/fsl_soc.c	2010-04-13 20:23:26.000000000 +0200
+@@ -43,6 +43,12 @@
+ extern void init_fcc_ioports(struct fs_platform_info*);
+ extern void init_fec_ioports(struct fs_platform_info*);
+ extern void init_smc_ioports(struct fs_uart_platform_info*);
++
++extern int usb_platform_dr_init(struct platform_device *);
++extern void usb_platform_dr_uninit(struct fsl_usb2_platform_data *);
++extern int usb_platform_mph_init(struct platform_device *);
++extern void usb_platform_mph_uninit(struct fsl_usb2_platform_data *);
++
+ static phys_addr_t immrbase = -1;
+ 
+ phys_addr_t get_immrbase(void)
+@@ -55,18 +61,10 @@
+ 	soc = of_find_node_by_type(NULL, "soc");
+ 	if (soc) {
+ 		int size;
+-		u32 naddr;
+-		const u32 *prop = of_get_property(soc, "#address-cells", &size);
++		const void *prop = of_get_property(soc, "reg", &size);
+ 
+-		if (prop && size == 4)
+-			naddr = *prop;
+-		else
+-			naddr = 2;
+-
+-		prop = of_get_property(soc, "ranges", &size);
+ 		if (prop)
+-			immrbase = of_translate_address(soc, prop + naddr);
+-
++			immrbase = of_translate_address(soc, prop);
+ 		of_node_put(soc);
+ 	}
+ 
+@@ -75,34 +73,7 @@
+ 
+ EXPORT_SYMBOL(get_immrbase);
+ 
+-static u32 sysfreq = -1;
+-
+-u32 fsl_get_sys_freq(void)
+-{
+-	struct device_node *soc;
+-	const u32 *prop;
+-	int size;
+-
+-	if (sysfreq != -1)
+-		return sysfreq;
+-
+-	soc = of_find_node_by_type(NULL, "soc");
+-	if (!soc)
+-		return -1;
+-
+-	prop = of_get_property(soc, "clock-frequency", &size);
+-	if (!prop || size != sizeof(*prop) || *prop == 0)
+-		prop = of_get_property(soc, "bus-frequency", &size);
+-
+-	if (prop && size == sizeof(*prop))
+-		sysfreq = *prop;
+-
+-	of_node_put(soc);
+-	return sysfreq;
+-}
+-EXPORT_SYMBOL(fsl_get_sys_freq);
+-
+-#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
++#if defined(CONFIG_CPM2) || defined(CONFIG_8xx)
+ 
+ static u32 brgfreq = -1;
+ 
+@@ -127,21 +98,11 @@
+ 
+ 	/* Legacy device binding -- will go away when no users are left. */
+ 	node = of_find_node_by_type(NULL, "cpm");
+-	if (!node)
+-		node = of_find_compatible_node(NULL, NULL, "fsl,qe");
+-	if (!node)
+-		node = of_find_node_by_type(NULL, "qe");
+-
+ 	if (node) {
+ 		prop = of_get_property(node, "brg-frequency", &size);
+ 		if (prop && size == 4)
+ 			brgfreq = *prop;
+ 
+-		if (brgfreq == -1 || brgfreq == 0) {
+-			prop = of_get_property(node, "bus-frequency", &size);
+-			if (prop && size == 4)
+-				brgfreq = *prop / 2;
+-		}
+ 		of_node_put(node);
+ 	}
+ 
+@@ -176,36 +137,329 @@
+ EXPORT_SYMBOL(get_baudrate);
+ #endif /* CONFIG_CPM2 */
+ 
+-#ifdef CONFIG_FIXED_PHY
+-static int __init of_add_fixed_phys(void)
++static int __init gfar_mdio_of_init(void)
+ {
++	struct device_node *np;
++	unsigned int i;
++	struct platform_device *mdio_dev;
++	struct resource res;
+ 	int ret;
++
++	for (np = NULL, i = 0;
++	     (np = of_find_compatible_node(np, "mdio", "gianfar")) != NULL;
++	     i++) {
++		int k;
++		struct device_node *child = NULL;
++		struct gianfar_mdio_data mdio_data;
++
++		memset(&res, 0, sizeof(res));
++		memset(&mdio_data, 0, sizeof(mdio_data));
++
++		ret = of_address_to_resource(np, 0, &res);
++		if (ret)
++			goto err;
++
++		mdio_dev =
++		    platform_device_register_simple("fsl-gianfar_mdio",
++						    res.start, &res, 1);
++		if (IS_ERR(mdio_dev)) {
++			ret = PTR_ERR(mdio_dev);
++			goto err;
++		}
++
++		for (k = 0; k < 32; k++)
++			mdio_data.irq[k] = PHY_POLL;
++
++		while ((child = of_get_next_child(np, child)) != NULL) {
++			int irq = irq_of_parse_and_map(child, 0);
++			if (irq != NO_IRQ) {
++				const u32 *id = of_get_property(child,
++							"reg", NULL);
++				mdio_data.irq[*id] = irq;
++			}
++		}
++
++		ret =
++		    platform_device_add_data(mdio_dev, &mdio_data,
++					     sizeof(struct gianfar_mdio_data));
++		if (ret)
++			goto unreg;
++	}
++
++	return 0;
++
++unreg:
++	platform_device_unregister(mdio_dev);
++err:
++	return ret;
++}
++
++arch_initcall(gfar_mdio_of_init);
++#if 0
++static const char *gfar_tx_intr = "tx";
++static const char *gfar_rx_intr = "rx";
++static const char *gfar_err_intr = "error";
++
++
++static int __init gfar_of_init(void)
++{
+ 	struct device_node *np;
+-	u32 *fixed_link;
+-	struct fixed_phy_status status = {};
++	unsigned int i;
++	struct platform_device *gfar_dev;
++	struct resource res;
++	int ret;
+ 
+-	for_each_node_by_name(np, "ethernet") {
+-		fixed_link  = (u32 *)of_get_property(np, "fixed-link", NULL);
+-		if (!fixed_link)
+-			continue;
++	for (np = NULL, i = 0;
++	     (np = of_find_compatible_node(np, "network", "gianfar")) != NULL;
++	     i++) {
++		struct resource r[4];
++		struct device_node *phy, *mdio;
++		struct gianfar_platform_data gfar_data;
++		const unsigned int *id;
++		const char *model;
++		const char *ctype;
++		const void *mac_addr;
++		const phandle *ph;
++		int n_res = 2;
+ 
+-		status.link = 1;
+-		status.duplex = fixed_link[1];
+-		status.speed = fixed_link[2];
+-		status.pause = fixed_link[3];
+-		status.asym_pause = fixed_link[4];
++		memset(r, 0, sizeof(r));
++		memset(&gfar_data, 0, sizeof(gfar_data));
+ 
+-		ret = fixed_phy_add(PHY_POLL, fixed_link[0], &status);
++		ret = of_address_to_resource(np, 0, &r[0]);
++		if (ret)
++			goto err;
++
++		of_irq_to_resource(np, 0, &r[1]);
++
++		model = of_get_property(np, "model", NULL);
++
++		/* If we aren't the FEC we have multiple interrupts */
++		if (model && strcasecmp(model, "FEC")) {
++			r[1].name = gfar_tx_intr;
++
++			r[2].name = gfar_rx_intr;
++			of_irq_to_resource(np, 1, &r[2]);
++
++			r[3].name = gfar_err_intr;
++			of_irq_to_resource(np, 2, &r[3]);
++
++			n_res += 2;
++		}
++
++		gfar_dev =
++		    platform_device_register_simple("fsl-gianfar", i, &r[0],
++						    n_res);
++
++		if (IS_ERR(gfar_dev)) {
++			ret = PTR_ERR(gfar_dev);
++			goto err;
++		}
++
++		mac_addr = of_get_mac_address(np);
++		if (mac_addr)
++			memcpy(gfar_data.mac_addr, mac_addr, 6);
++
++		if (model && !strcasecmp(model, "TSEC"))
++			gfar_data.device_flags =
++			    FSL_GIANFAR_DEV_HAS_GIGABIT |
++			    FSL_GIANFAR_DEV_HAS_COALESCE |
++			    FSL_GIANFAR_DEV_HAS_RMON |
++			    FSL_GIANFAR_DEV_HAS_MULTI_INTR;
++		if (model && !strcasecmp(model, "eTSEC"))
++			gfar_data.device_flags =
++			    FSL_GIANFAR_DEV_HAS_GIGABIT |
++			    FSL_GIANFAR_DEV_HAS_COALESCE |
++			    FSL_GIANFAR_DEV_HAS_RMON |
++			    FSL_GIANFAR_DEV_HAS_MULTI_INTR |
++			    FSL_GIANFAR_DEV_HAS_CSUM |
++			    FSL_GIANFAR_DEV_HAS_VLAN |
++			    FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
++
++		ctype = of_get_property(np, "phy-connection-type", NULL);
++
++		/* We only care about rgmii-id.  The rest are autodetected */
++		if (ctype && !strcmp(ctype, "rgmii-id"))
++			gfar_data.interface = PHY_INTERFACE_MODE_RGMII_ID;
++		else
++			gfar_data.interface = PHY_INTERFACE_MODE_MII;
++
++		ph = of_get_property(np, "phy-handle", NULL);
++		phy = of_find_node_by_phandle(*ph);
++
++		if (phy == NULL) {
++			ret = -ENODEV;
++			goto unreg;
++		}
++
++		mdio = of_get_parent(phy);
++
++		id = of_get_property(phy, "reg", NULL);
++		ret = of_address_to_resource(mdio, 0, &res);
+ 		if (ret) {
+-			of_node_put(np);
+-			return ret;
++			of_node_put(phy);
++			of_node_put(mdio);
++			goto unreg;
+ 		}
++
++		gfar_data.phy_id = *id;
++		gfar_data.bus_id = res.start;
++
++		of_node_put(phy);
++		of_node_put(mdio);
++
++		ret =
++		    platform_device_add_data(gfar_dev, &gfar_data,
++					     sizeof(struct
++						    gianfar_platform_data));
++		if (ret)
++			goto unreg;
+ 	}
+ 
+ 	return 0;
++
++unreg:
++	platform_device_unregister(gfar_dev);
++err:
++	return ret;
+ }
+-arch_initcall(of_add_fixed_phys);
+-#endif /* CONFIG_FIXED_PHY */
++
++arch_initcall(gfar_of_init);
++
++#endif
++
++#ifdef CONFIG_I2C_BOARDINFO
++#include <linux/i2c.h>
++struct i2c_driver_device {
++	char	*of_device;
++	char	*i2c_driver;
++	char	*i2c_type;
++};
++
++static struct i2c_driver_device i2c_devices[] __initdata = {
++	{"ricoh,rs5c372a", "rtc-rs5c372", "rs5c372a",},
++	{"ricoh,rs5c372b", "rtc-rs5c372", "rs5c372b",},
++	{"ricoh,rv5c386",  "rtc-rs5c372", "rv5c386",},
++	{"ricoh,rv5c387a", "rtc-rs5c372", "rv5c387a",},
++	{"dallas,ds1307",  "rtc-ds1307",  "ds1307",},
++	{"dallas,ds1337",  "rtc-ds1307",  "ds1337",},
++	{"dallas,ds1338",  "rtc-ds1307",  "ds1338",},
++	{"dallas,ds1339",  "rtc-ds1307",  "ds1339",},
++	{"dallas,ds1340",  "rtc-ds1307",  "ds1340",},
++	{"stm,m41t00",     "rtc-ds1307",  "m41t00"},
++	{"dallas,ds1374",  "rtc-ds1374",  "rtc-ds1374",},
++	{"sd,sd2068",  "rtc-sd2068",  "rtc-sd2068",},
++	{"topstd,chacha_mt4",  "chacha_mt4",  "chacha_mt4",},
++	{"mosart,ma17p0x",  "ma17p0x",  "ma17p0x",},
++};
++
++static int __init of_find_i2c_driver(struct device_node *node,
++				     struct i2c_board_info *info)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(i2c_devices); i++) {
++		if (!of_device_is_compatible(node, i2c_devices[i].of_device))
++			continue;
++
++		if (/*strlcpy(info->driver_name, i2c_devices[i].i2c_driver,
++			    KOBJ_NAME_LEN) >= KOBJ_NAME_LEN ||*/
++		    strlcpy(info->type, i2c_devices[i].i2c_type,
++			    I2C_NAME_SIZE) >= I2C_NAME_SIZE)
++		{
++			/*printk("%s() line:%d\n",__FUNCTION__,__LINE__);*/
++			return -ENOMEM;
++		}
++		return 0;
++	}
++	return -ENODEV;
++}
++
++static void __init of_register_i2c_devices(struct device_node *adap_node,
++					   int bus_num)
++{
++	struct device_node *node = NULL;
++
++	while ((node = of_get_next_child(adap_node, node))) {
++		struct i2c_board_info info = {};
++		const u32 *addr;
++		int len;
++		
++		addr = of_get_property(node, "reg", &len);
++		if (!addr || len < sizeof(int) || *addr > (1 << 10) - 1) {
++			printk(KERN_WARNING "fsl_soc.c: invalid i2c device entry\n");
++			continue;
++		}
++
++		info.irq = irq_of_parse_and_map(node, 0);
++		if (info.irq == NO_IRQ)
++			info.irq = -1;
++		
++		if (of_find_i2c_driver(node, &info) < 0)
++			continue;
++
++		info.addr = *addr;
++
++		i2c_register_board_info(bus_num, &info, 1);
++	}
++}
++
++static int __init fsl_i2c_of_init(void)
++{
++	struct device_node *np;
++	unsigned int i = 0;
++	struct platform_device *i2c_dev;
++	int ret;
++
++	for_each_compatible_node(np, NULL, "fsl-i2c") {
++		struct resource r[2];
++		struct fsl_i2c_platform_data i2c_data;
++		const unsigned char *flags = NULL;
++
++		memset(&r, 0, sizeof(r));
++		memset(&i2c_data, 0, sizeof(i2c_data));
++
++		ret = of_address_to_resource(np, 0, &r[0]);
++		if (ret)
++			goto err;
++
++		of_irq_to_resource(np, 0, &r[1]);
++
++		i2c_dev = platform_device_register_simple("fsl-i2c", i, r, 2);
++		if (IS_ERR(i2c_dev)) {
++			ret = PTR_ERR(i2c_dev);
++			goto err;
++		}
++
++		i2c_data.device_flags = 0;
++		flags = of_get_property(np, "dfsrr", NULL);
++		if (flags)
++			i2c_data.device_flags |= FSL_I2C_DEV_SEPARATE_DFSRR;
++
++		flags = of_get_property(np, "fsl5200-clocking", NULL);
++		if (flags)
++			i2c_data.device_flags |= FSL_I2C_DEV_CLOCK_5200;
++
++		ret =
++		    platform_device_add_data(i2c_dev, &i2c_data,
++					     sizeof(struct
++						    fsl_i2c_platform_data));
++		if (ret)
++			goto unreg;
++
++		of_register_i2c_devices(np, i++);
++	}
++
++	return 0;
++
++unreg:
++	platform_device_unregister(i2c_dev);
++err:
++	return ret;
++}
++
++arch_initcall(fsl_i2c_of_init);
++#endif
++
+ 
+ #ifdef CONFIG_PPC_83xx
+ static int __init mpc83xx_wdt_init(void)
+@@ -272,12 +526,14 @@
+ static int __init fsl_usb_of_init(void)
+ {
+ 	struct device_node *np;
+-	unsigned int i = 0;
+-	struct platform_device *usb_dev_mph = NULL, *usb_dev_dr_host = NULL,
+-		*usb_dev_dr_client = NULL;
++	unsigned int i;
++	struct platform_device *usb_dev_mph = NULL, *usb_dev_dr_otg = NULL,
++		*usb_dev_dr_host = NULL, *usb_dev_dr_client = NULL;
+ 	int ret;
+ 
+-	for_each_compatible_node(np, NULL, "fsl-usb2-mph") {
++	for (np = NULL, i = 0;
++	     (np = of_find_compatible_node(np, "usb", "fsl-usb2-mph")) != NULL;
++	     i++) {
+ 		struct resource r[2];
+ 		struct fsl_usb2_platform_data usb_data;
+ 		const unsigned char *prop = NULL;
+@@ -311,19 +567,25 @@
+ 		if (prop)
+ 			usb_data.port_enables |= FSL_USB2_PORT1_ENABLED;
+ 
++		if (of_get_property(np, "big-endian-regs", NULL))
++			usb_data.big_endian_mmio = 1;
+ 		prop = of_get_property(np, "phy_type", NULL);
+ 		usb_data.phy_mode = determine_usb_phy(prop);
+ 
++		usb_data.platform_init = usb_platform_mph_init;
++		usb_data.platform_uninit = usb_platform_mph_uninit;
++		
+ 		ret =
+ 		    platform_device_add_data(usb_dev_mph, &usb_data,
+ 					     sizeof(struct
+ 						    fsl_usb2_platform_data));
+ 		if (ret)
+ 			goto unreg_mph;
+-		i++;
+ 	}
+ 
+-	for_each_compatible_node(np, NULL, "fsl-usb2-dr") {
++	for (np = NULL;
++	     (np = of_find_compatible_node(np, "usb", "fsl-usb2-dr")) != NULL;
++	     i++) {
+ 		struct resource r[2];
+ 		struct fsl_usb2_platform_data usb_data;
+ 		const unsigned char *prop = NULL;
+@@ -357,26 +619,47 @@
+ 			}
+ 		} else if (prop && !strcmp(prop, "otg")) {
+ 			usb_data.operating_mode = FSL_USB2_DR_OTG;
++			usb_dev_dr_otg = platform_device_register_simple(
++					"fsl-usb2-otg", i, r, 2);
++			if (IS_ERR(usb_dev_dr_otg)) {
++				ret = PTR_ERR(usb_dev_dr_otg);
++				goto unreg_dr;
++			}
+ 			usb_dev_dr_host = platform_device_register_simple(
+ 					"fsl-ehci", i, r, 2);
+ 			if (IS_ERR(usb_dev_dr_host)) {
+ 				ret = PTR_ERR(usb_dev_dr_host);
+-				goto err;
++				goto unreg_dr;
+ 			}
+ 			usb_dev_dr_client = platform_device_register_simple(
+ 					"fsl-usb2-udc", i, r, 2);
+ 			if (IS_ERR(usb_dev_dr_client)) {
+ 				ret = PTR_ERR(usb_dev_dr_client);
+-				goto err;
++				goto unreg_dr;
+ 			}
+ 		} else {
+ 			ret = -EINVAL;
+ 			goto err;
+ 		}
++		if (of_get_property(np, "big-endian-regs", NULL))
++			usb_data.big_endian_mmio = 1;
+ 
+ 		prop = of_get_property(np, "phy_type", NULL);
+ 		usb_data.phy_mode = determine_usb_phy(prop);
+-
++	
++		usb_data.platform_init = usb_platform_dr_init;
++		usb_data.platform_uninit = usb_platform_dr_uninit;
++		
++
++		if (usb_dev_dr_otg) {
++			usb_dev_dr_otg->dev.coherent_dma_mask = 0xffffffffUL;
++			usb_dev_dr_otg->dev.dma_mask = &usb_dev_dr_otg->
++				dev.coherent_dma_mask;
++			if ((ret = platform_device_add_data(usb_dev_dr_otg,
++			    			&usb_data, sizeof(struct
++						fsl_usb2_platform_data))))
++				goto unreg_dr;
++		}
+ 		if (usb_dev_dr_host) {
+ 			usb_dev_dr_host->dev.coherent_dma_mask = 0xffffffffUL;
+ 			usb_dev_dr_host->dev.dma_mask = &usb_dev_dr_host->
+@@ -395,7 +678,6 @@
+ 						fsl_usb2_platform_data))))
+ 				goto unreg_dr;
+ 		}
+-		i++;
+ 	}
+ 	return 0;
+ 
+@@ -404,6 +686,8 @@
+ 		platform_device_unregister(usb_dev_dr_host);
+ 	if (usb_dev_dr_client)
+ 		platform_device_unregister(usb_dev_dr_client);
++	if (usb_dev_dr_otg)
++		platform_device_unregister(usb_dev_dr_otg);
+ unreg_mph:
+ 	if (usb_dev_mph)
+ 		platform_device_unregister(usb_dev_mph);
+@@ -413,17 +697,572 @@
+ 
+ arch_initcall(fsl_usb_of_init);
+ 
+-static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
+-				   struct spi_board_info *board_infos,
+-				   unsigned int num_board_infos,
+-				   void (*activate_cs)(u8 cs, u8 polarity),
+-				   void (*deactivate_cs)(u8 cs, u8 polarity))
++#ifndef CONFIG_PPC_CPM_NEW_BINDING
++#ifdef CONFIG_CPM2
++
++extern void init_scc_ioports(struct fs_uart_platform_info*);
++
++static const char fcc_regs[] = "fcc_regs";
++static const char fcc_regs_c[] = "fcc_regs_c";
++static const char fcc_pram[] = "fcc_pram";
++static char bus_id[9][BUS_ID_SIZE];
++
++static int __init fs_enet_of_init(void)
+ {
+ 	struct device_node *np;
+-	unsigned int i = 0;
++	unsigned int i;
++	struct platform_device *fs_enet_dev;
++	struct resource res;
++	int ret;
++
++	for (np = NULL, i = 0;
++	     (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
++	     i++) {
++		struct resource r[4];
++		struct device_node *phy, *mdio;
++		struct fs_platform_info fs_enet_data;
++		const unsigned int *id, *phy_addr, *phy_irq;
++		const void *mac_addr;
++		const phandle *ph;
++		const char *model;
++
++		memset(r, 0, sizeof(r));
++		memset(&fs_enet_data, 0, sizeof(fs_enet_data));
++
++		ret = of_address_to_resource(np, 0, &r[0]);
++		if (ret)
++			goto err;
++		r[0].name = fcc_regs;
++
++		ret = of_address_to_resource(np, 1, &r[1]);
++		if (ret)
++			goto err;
++		r[1].name = fcc_pram;
++
++		ret = of_address_to_resource(np, 2, &r[2]);
++		if (ret)
++			goto err;
++		r[2].name = fcc_regs_c;
++		fs_enet_data.fcc_regs_c = r[2].start;
++
++		of_irq_to_resource(np, 0, &r[3]);
++
++		fs_enet_dev =
++		    platform_device_register_simple("fsl-cpm-fcc", i, &r[0], 4);
++
++		if (IS_ERR(fs_enet_dev)) {
++			ret = PTR_ERR(fs_enet_dev);
++			goto err;
++		}
++
++		model = of_get_property(np, "model", NULL);
++		if (model == NULL) {
++			ret = -ENODEV;
++			goto unreg;
++		}
++
++		mac_addr = of_get_mac_address(np);
++		if (mac_addr)
++			memcpy(fs_enet_data.macaddr, mac_addr, 6);
++
++		ph = of_get_property(np, "phy-handle", NULL);
++		phy = of_find_node_by_phandle(*ph);
++
++		if (phy == NULL) {
++			ret = -ENODEV;
++			goto unreg;
++		}
++
++		phy_addr = of_get_property(phy, "reg", NULL);
++		fs_enet_data.phy_addr = *phy_addr;
++
++		phy_irq = of_get_property(phy, "interrupts", NULL);
++
++		id = of_get_property(np, "device-id", NULL);
++		fs_enet_data.fs_no = *id;
++		strcpy(fs_enet_data.fs_type, model);
++
++		mdio = of_get_parent(phy);
++                ret = of_address_to_resource(mdio, 0, &res);
++                if (ret) {
++                        of_node_put(phy);
++                        of_node_put(mdio);
++                        goto unreg;
++                }
++
++		fs_enet_data.clk_rx = *((u32 *)of_get_property(np,
++						"rx-clock", NULL));
++		fs_enet_data.clk_tx = *((u32 *)of_get_property(np,
++						"tx-clock", NULL));
++
++		if (strstr(model, "FCC")) {
++			int fcc_index = *id - 1;
++			const unsigned char *mdio_bb_prop;
++
++			fs_enet_data.dpram_offset = (u32)cpm_dpram_addr(0);
++			fs_enet_data.rx_ring = 32;
++			fs_enet_data.tx_ring = 32;
++			fs_enet_data.rx_copybreak = 240;
++			fs_enet_data.use_napi = 0;
++			fs_enet_data.napi_weight = 17;
++			fs_enet_data.mem_offset = FCC_MEM_OFFSET(fcc_index);
++			fs_enet_data.cp_page = CPM_CR_FCC_PAGE(fcc_index);
++			fs_enet_data.cp_block = CPM_CR_FCC_SBLOCK(fcc_index);
++
++			snprintf((char*)&bus_id[(*id)], BUS_ID_SIZE, "%x:%02x",
++							(u32)res.start, fs_enet_data.phy_addr);
++			fs_enet_data.bus_id = (char*)&bus_id[(*id)];
++			fs_enet_data.init_ioports = init_fcc_ioports;
++
++			mdio_bb_prop = of_get_property(phy, "bitbang", NULL);
++			if (mdio_bb_prop) {
++				struct platform_device *fs_enet_mdio_bb_dev;
++				struct fs_mii_bb_platform_info fs_enet_mdio_bb_data;
++
++				fs_enet_mdio_bb_dev =
++					platform_device_register_simple("fsl-bb-mdio",
++							i, NULL, 0);
++				memset(&fs_enet_mdio_bb_data, 0,
++						sizeof(struct fs_mii_bb_platform_info));
++				fs_enet_mdio_bb_data.mdio_dat.bit =
++					mdio_bb_prop[0];
++				fs_enet_mdio_bb_data.mdio_dir.bit =
++					mdio_bb_prop[1];
++				fs_enet_mdio_bb_data.mdc_dat.bit =
++					mdio_bb_prop[2];
++				fs_enet_mdio_bb_data.mdio_port =
++					mdio_bb_prop[3];
++				fs_enet_mdio_bb_data.mdc_port =
++					mdio_bb_prop[4];
++				fs_enet_mdio_bb_data.delay =
++					mdio_bb_prop[5];
++
++				fs_enet_mdio_bb_data.irq[0] = phy_irq[0];
++				fs_enet_mdio_bb_data.irq[1] = -1;
++				fs_enet_mdio_bb_data.irq[2] = -1;
++				fs_enet_mdio_bb_data.irq[3] = phy_irq[0];
++				fs_enet_mdio_bb_data.irq[31] = -1;
++
++				fs_enet_mdio_bb_data.mdio_dat.offset =
++					(u32)&cpm2_immr->im_ioport.iop_pdatc;
++				fs_enet_mdio_bb_data.mdio_dir.offset =
++					(u32)&cpm2_immr->im_ioport.iop_pdirc;
++				fs_enet_mdio_bb_data.mdc_dat.offset =
++					(u32)&cpm2_immr->im_ioport.iop_pdatc;
++
++				ret = platform_device_add_data(
++						fs_enet_mdio_bb_dev,
++						&fs_enet_mdio_bb_data,
++						sizeof(struct fs_mii_bb_platform_info));
++				if (ret)
++					goto unreg;
++			}
++
++			of_node_put(phy);
++			of_node_put(mdio);
++
++			ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
++						     sizeof(struct
++							    fs_platform_info));
++			if (ret)
++				goto unreg;
++		}
++	}
++	return 0;
++
++unreg:
++	platform_device_unregister(fs_enet_dev);
++err:
++	return ret;
++}
++
++arch_initcall(fs_enet_of_init);
++
++static const char scc_regs[] = "regs";
++static const char scc_pram[] = "pram";
+ 
+-	for_each_compatible_node(np, type, compatible) {
+-		int ret;
++static int __init cpm_uart_of_init(void)
++{
++	struct device_node *np;
++	unsigned int i;
++	struct platform_device *cpm_uart_dev;
++	int ret;
++
++	for (np = NULL, i = 0;
++	     (np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
++	     i++) {
++		struct resource r[3];
++		struct fs_uart_platform_info cpm_uart_data;
++		const int *id;
++		const char *model;
++
++		memset(r, 0, sizeof(r));
++		memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
++
++		ret = of_address_to_resource(np, 0, &r[0]);
++		if (ret)
++			goto err;
++
++		r[0].name = scc_regs;
++
++		ret = of_address_to_resource(np, 1, &r[1]);
++		if (ret)
++			goto err;
++		r[1].name = scc_pram;
++
++		of_irq_to_resource(np, 0, &r[2]);
++
++		cpm_uart_dev =
++		    platform_device_register_simple("fsl-cpm-scc:uart", i, &r[0], 3);
++
++		if (IS_ERR(cpm_uart_dev)) {
++			ret = PTR_ERR(cpm_uart_dev);
++			goto err;
++		}
++
++		id = of_get_property(np, "device-id", NULL);
++		cpm_uart_data.fs_no = *id;
++
++		model = of_get_property(np, "model", NULL);
++		strcpy(cpm_uart_data.fs_type, model);
++
++		cpm_uart_data.uart_clk = ppc_proc_freq;
++
++		cpm_uart_data.tx_num_fifo = 4;
++		cpm_uart_data.tx_buf_size = 32;
++		cpm_uart_data.rx_num_fifo = 4;
++		cpm_uart_data.rx_buf_size = 32;
++		cpm_uart_data.clk_rx = *((u32 *)of_get_property(np,
++						"rx-clock", NULL));
++		cpm_uart_data.clk_tx = *((u32 *)of_get_property(np,
++						"tx-clock", NULL));
++
++		ret =
++		    platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
++					     sizeof(struct
++						    fs_uart_platform_info));
++		if (ret)
++			goto unreg;
++	}
++
++	return 0;
++
++unreg:
++	platform_device_unregister(cpm_uart_dev);
++err:
++	return ret;
++}
++
++arch_initcall(cpm_uart_of_init);
++#endif /* CONFIG_CPM2 */
++
++#ifdef CONFIG_8xx
++
++extern void init_scc_ioports(struct fs_platform_info*);
++extern int platform_device_skip(const char *model, int id);
++
++static int __init fs_enet_mdio_of_init(void)
++{
++	struct device_node *np;
++	unsigned int i;
++	struct platform_device *mdio_dev;
++	struct resource res;
++	int ret;
++
++	for (np = NULL, i = 0;
++	     (np = of_find_compatible_node(np, "mdio", "fs_enet")) != NULL;
++	     i++) {
++		struct fs_mii_fec_platform_info mdio_data;
++
++		memset(&res, 0, sizeof(res));
++		memset(&mdio_data, 0, sizeof(mdio_data));
++
++		ret = of_address_to_resource(np, 0, &res);
++		if (ret)
++			goto err;
++
++		mdio_dev =
++		    platform_device_register_simple("fsl-cpm-fec-mdio",
++						    res.start, &res, 1);
++		if (IS_ERR(mdio_dev)) {
++			ret = PTR_ERR(mdio_dev);
++			goto err;
++		}
++
++		mdio_data.mii_speed = ((((ppc_proc_freq + 4999999) / 2500000) / 2) & 0x3F) << 1;
++
++		ret =
++		    platform_device_add_data(mdio_dev, &mdio_data,
++					     sizeof(struct fs_mii_fec_platform_info));
++		if (ret)
++			goto unreg;
++	}
++	return 0;
++
++unreg:
++	platform_device_unregister(mdio_dev);
++err:
++	return ret;
++}
++
++arch_initcall(fs_enet_mdio_of_init);
++
++static const char *enet_regs = "regs";
++static const char *enet_pram = "pram";
++static const char *enet_irq = "interrupt";
++static char bus_id[9][BUS_ID_SIZE];
++
++static int __init fs_enet_of_init(void)
++{
++	struct device_node *np;
++	unsigned int i;
++	struct platform_device *fs_enet_dev = NULL;
++	struct resource res;
++	int ret;
++
++	for (np = NULL, i = 0;
++	     (np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
++	     i++) {
++		struct resource r[4];
++		struct device_node *phy = NULL, *mdio = NULL;
++		struct fs_platform_info fs_enet_data;
++		const unsigned int *id;
++		const unsigned int *phy_addr;
++		const void *mac_addr;
++		const phandle *ph;
++		const char *model;
++
++		memset(r, 0, sizeof(r));
++		memset(&fs_enet_data, 0, sizeof(fs_enet_data));
++
++		model = of_get_property(np, "model", NULL);
++		if (model == NULL) {
++			ret = -ENODEV;
++			goto unreg;
++		}
++
++		id = of_get_property(np, "device-id", NULL);
++		fs_enet_data.fs_no = *id;
++
++		if (platform_device_skip(model, *id))
++			continue;
++
++		ret = of_address_to_resource(np, 0, &r[0]);
++		if (ret)
++			goto err;
++		r[0].name = enet_regs;
++
++		mac_addr = of_get_mac_address(np);
++		if (mac_addr)
++			memcpy(fs_enet_data.macaddr, mac_addr, 6);
++
++		ph = of_get_property(np, "phy-handle", NULL);
++		if (ph != NULL)
++			phy = of_find_node_by_phandle(*ph);
++
++		if (phy != NULL) {
++			phy_addr = of_get_property(phy, "reg", NULL);
++			fs_enet_data.phy_addr = *phy_addr;
++			fs_enet_data.has_phy = 1;
++
++			mdio = of_get_parent(phy);
++			ret = of_address_to_resource(mdio, 0, &res);
++			if (ret) {
++				of_node_put(phy);
++				of_node_put(mdio);
++                                goto unreg;
++			}
++		}
++
++		model = of_get_property(np, "model", NULL);
++		strcpy(fs_enet_data.fs_type, model);
++
++		if (strstr(model, "FEC")) {
++			r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
++			r[1].flags = IORESOURCE_IRQ;
++			r[1].name = enet_irq;
++
++			fs_enet_dev =
++				    platform_device_register_simple("fsl-cpm-fec", i, &r[0], 2);
++
++			if (IS_ERR(fs_enet_dev)) {
++				ret = PTR_ERR(fs_enet_dev);
++				goto err;
++			}
++
++			fs_enet_data.rx_ring = 128;
++			fs_enet_data.tx_ring = 16;
++			fs_enet_data.rx_copybreak = 240;
++			fs_enet_data.use_napi = 1;
++			fs_enet_data.napi_weight = 17;
++
++			snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%x:%02x",
++							(u32)res.start, fs_enet_data.phy_addr);
++			fs_enet_data.bus_id = (char*)&bus_id[i];
++			fs_enet_data.init_ioports = init_fec_ioports;
++		}
++		if (strstr(model, "SCC")) {
++			ret = of_address_to_resource(np, 1, &r[1]);
++			if (ret)
++				goto err;
++			r[1].name = enet_pram;
++
++			r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
++			r[2].flags = IORESOURCE_IRQ;
++			r[2].name = enet_irq;
++
++			fs_enet_dev =
++				    platform_device_register_simple("fsl-cpm-scc", i, &r[0], 3);
++
++			if (IS_ERR(fs_enet_dev)) {
++				ret = PTR_ERR(fs_enet_dev);
++				goto err;
++			}
++
++			fs_enet_data.rx_ring = 64;
++			fs_enet_data.tx_ring = 8;
++			fs_enet_data.rx_copybreak = 240;
++			fs_enet_data.use_napi = 1;
++			fs_enet_data.napi_weight = 17;
++
++			snprintf((char*)&bus_id[i], BUS_ID_SIZE, "%s", "fixed@10:1");
++                        fs_enet_data.bus_id = (char*)&bus_id[i];
++			fs_enet_data.init_ioports = init_scc_ioports;
++		}
++
++		of_node_put(phy);
++		of_node_put(mdio);
++
++		ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
++					     sizeof(struct
++						    fs_platform_info));
++		if (ret)
++			goto unreg;
++	}
++	return 0;
++
++unreg:
++	platform_device_unregister(fs_enet_dev);
++err:
++	return ret;
++}
++
++arch_initcall(fs_enet_of_init);
++
++static int __init fsl_pcmcia_of_init(void)
++{
++	struct device_node *np = NULL;
++	/*
++	 * Register all the devices which type is "pcmcia"
++	 */
++	while ((np = of_find_compatible_node(np,
++			"pcmcia", "fsl,pq-pcmcia")) != NULL)
++			    of_platform_device_create(np, "m8xx-pcmcia", NULL);
++	return 0;
++}
++
++arch_initcall(fsl_pcmcia_of_init);
++
++static const char *smc_regs = "regs";
++static const char *smc_pram = "pram";
++
++static int __init cpm_smc_uart_of_init(void)
++{
++	struct device_node *np;
++	unsigned int i;
++	struct platform_device *cpm_uart_dev;
++	int ret;
++
++	for (np = NULL, i = 0;
++	     (np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
++	     i++) {
++		struct resource r[3];
++		struct fs_uart_platform_info cpm_uart_data;
++		const int *id;
++		const char *model;
++
++		memset(r, 0, sizeof(r));
++		memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
++
++		ret = of_address_to_resource(np, 0, &r[0]);
++		if (ret)
++			goto err;
++
++		r[0].name = smc_regs;
++
++		ret = of_address_to_resource(np, 1, &r[1]);
++		if (ret)
++			goto err;
++		r[1].name = smc_pram;
++
++		r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
++		r[2].flags = IORESOURCE_IRQ;
++
++		cpm_uart_dev =
++		    platform_device_register_simple("fsl-cpm-smc:uart", i, &r[0], 3);
++
++		if (IS_ERR(cpm_uart_dev)) {
++			ret = PTR_ERR(cpm_uart_dev);
++			goto err;
++		}
++
++		model = of_get_property(np, "model", NULL);
++		strcpy(cpm_uart_data.fs_type, model);
++
++		id = of_get_property(np, "device-id", NULL);
++		cpm_uart_data.fs_no = *id;
++		cpm_uart_data.uart_clk = ppc_proc_freq;
++
++		cpm_uart_data.tx_num_fifo = 4;
++		cpm_uart_data.tx_buf_size = 32;
++		cpm_uart_data.rx_num_fifo = 4;
++		cpm_uart_data.rx_buf_size = 32;
++
++		ret =
++		    platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
++					     sizeof(struct
++						    fs_uart_platform_info));
++		if (ret)
++			goto unreg;
++	}
++
++	return 0;
++
++unreg:
++	platform_device_unregister(cpm_uart_dev);
++err:
++	return ret;
++}
++
++arch_initcall(cpm_smc_uart_of_init);
++
++#endif /* CONFIG_8xx */
++#endif /* CONFIG_PPC_CPM_NEW_BINDING */
++int __init fsl_spi_init(struct spi_board_info *board_infos,
++			unsigned int num_board_infos,
++			void (*activate_cs)(u8 cs, u8 polarity),
++			void (*deactivate_cs)(u8 cs, u8 polarity))
++{
++	struct device_node *np;
++	unsigned int i;
++	const u32 *sysclk;
++
++	/* SPI controller is either clocked from QE or SoC clock */
++	np = of_find_node_by_type(NULL, "qe");
++	if (!np)
++		np = of_find_node_by_type(NULL, "soc");
++
++	if (!np)
++		return -ENODEV;
++
++	sysclk = of_get_property(np, "bus-frequency", NULL);
++	if (!sysclk)
++		return -ENODEV;
++
++	for (np = NULL, i = 1;
++	     (np = of_find_compatible_node(np, "spi", "fsl_spi")) != NULL;
++	     i++) {
++		int ret = 0;
+ 		unsigned int j;
+ 		const void *prop;
+ 		struct resource res[2];
+@@ -435,17 +1274,13 @@
+ 
+ 		memset(res, 0, sizeof(res));
+ 
+-		pdata.sysclk = sysclk;
++		pdata.sysclk = *sysclk;
+ 
+ 		prop = of_get_property(np, "reg", NULL);
+ 		if (!prop)
+ 			goto err;
+ 		pdata.bus_num = *(u32 *)prop;
+ 
+-		prop = of_get_property(np, "cell-index", NULL);
+-		if (prop)
+-			i = *(u32 *)prop;
+-
+ 		prop = of_get_property(np, "mode", NULL);
+ 		if (prop && !strcmp(prop, "cpu-qe"))
+ 			pdata.qe_mode = 1;
+@@ -456,7 +1291,7 @@
+ 		}
+ 
+ 		if (!pdata.max_chipselect)
+-			continue;
++			goto err;
+ 
+ 		ret = of_address_to_resource(np, 0, &res[0]);
+ 		if (ret)
+@@ -479,46 +1314,17 @@
+ 		if (ret)
+ 			goto unreg;
+ 
+-		ret = platform_device_add(pdev);
++		ret = platform_device_register(pdev);
+ 		if (ret)
+ 			goto unreg;
+ 
+-		goto next;
++		continue;
+ unreg:
+ 		platform_device_del(pdev);
+ err:
+-		pr_err("%s: registration failed\n", np->full_name);
+-next:
+-		i++;
+-	}
+-
+-	return i;
+-}
+-
+-int __init fsl_spi_init(struct spi_board_info *board_infos,
+-			unsigned int num_board_infos,
+-			void (*activate_cs)(u8 cs, u8 polarity),
+-			void (*deactivate_cs)(u8 cs, u8 polarity))
+-{
+-	u32 sysclk = -1;
+-	int ret;
+-
+-#ifdef CONFIG_QUICC_ENGINE
+-	/* SPI controller is either clocked from QE or SoC clock */
+-	sysclk = get_brgfreq();
+-#endif
+-	if (sysclk == -1) {
+-		sysclk = fsl_get_sys_freq();
+-		if (sysclk == -1)
+-			return -ENODEV;
++		continue;
+ 	}
+ 
+-	ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
+-			       num_board_infos, activate_cs, deactivate_cs);
+-	if (!ret)
+-		of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos,
+-				 num_board_infos, activate_cs, deactivate_cs);
+-
+ 	return spi_register_board_info(board_infos, num_board_infos);
+ }
+ 
+@@ -560,7 +1366,41 @@
+ }
+ #endif
+ 
+-#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+-struct platform_diu_data_ops diu_ops;
+-EXPORT_SYMBOL(diu_ops);
+-#endif
++#ifdef CONFIG_PPC_MPC5121
++static int __init mpc512x_mbx_of_init(void)
++{
++	struct device_node *np;
++	struct platform_device *mbx_dev;
++	int ret;
++
++	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-mbx");
++	if (np) {
++		struct resource r[2];
++		int irq;
++
++		memset(&r, 0, sizeof(r));
++
++		ret = of_address_to_resource(np, 0, &r[0]);
++		if (ret)
++			goto err;
++
++		irq = of_irq_to_resource(np, 0, &r[1]);
++		if (irq == NO_IRQ)
++			goto err;
++
++		printk(KERN_INFO "Reserved irq %d(0x%x) for MBX\n", irq, irq);
++
++		mbx_dev = platform_device_register_simple("mpc5121-mbx",
++				0, r, 2);
++		if (IS_ERR(mbx_dev)) {
++			ret = PTR_ERR(mbx_dev);
++			goto err;
++		}
++	}
++	return 0;
++err:
++	return ret;
++}
++
++arch_initcall(mpc512x_mbx_of_init);
++#endif /* CONFIG_PPC_512x */
+diff -Naur linux-2.6.29/arch/powerpc/sysdev/ipic.c linux-2.6.29-v2010041601/arch/powerpc/sysdev/ipic.c
+--- linux-2.6.29/arch/powerpc/sysdev/ipic.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/arch/powerpc/sysdev/ipic.c	2010-04-13 20:23:26.000000000 +0200
+@@ -902,7 +902,7 @@
+ 	u32 sermr;
+ 	u32 sercr;
+ } ipic_saved_state;
+-
++extern int fsl_deep_sleep(void);
+ static int ipic_suspend(struct sys_device *sdev, pm_message_t state)
+ {
+ 	struct ipic *ipic = primary_ipic;
+diff -Naur linux-2.6.29/drivers/dma/fsldma.c linux-2.6.29-v2010041601/drivers/dma/fsldma.c
+--- linux-2.6.29/drivers/dma/fsldma.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/dma/fsldma.c	2010-04-13 20:23:26.000000000 +0200
+@@ -1,22 +1,29 @@
+ /*
+- * Freescale MPC85xx, MPC83xx DMA Engine support
+- *
+- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+- *
+- * Author:
+- *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
+- *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
+- *
+- * Description:
+- *   DMA engine driver for Freescale MPC8540 DMA controller, which is
+- *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
+- *   The support for MPC8349 DMA contorller is also added.
+- *
+- * This is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
++ * Hongjun Chen <hong-jun.chen@freescale.com>
++ *chen_yunsong <chen_yunsong@mtcera.com>
++ * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the Free
++ * Software Foundation; either version 2 of the License, or (at your option)
++ * any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc., 59
++ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+  *
++ * The full GNU General Public License is included in this distribution in the
++ * file called COPYING.
++ */
++
++/*
++ * This driver supports an MPC5121 DMA engine, which does asynchronous
++ * copy operations.
+  */
+ 
+ #include <linux/init.h>
+@@ -26,996 +33,754 @@
+ #include <linux/dmaengine.h>
+ #include <linux/delay.h>
+ #include <linux/dma-mapping.h>
+-#include <linux/dmapool.h>
++#include <linux/io.h>
++#include <linux/of.h>
+ #include <linux/of_platform.h>
+ 
+-#include "fsldma.h"
+ 
+-static void dma_init(struct fsl_dma_chan *fsl_chan)
+-{
+-	/* Reset the channel */
+-	DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32);
+ 
+-	switch (fsl_chan->feature & FSL_DMA_IP_MASK) {
+-	case FSL_DMA_IP_85XX:
+-		/* Set the channel to below modes:
+-		 * EIE - Error interrupt enable
+-		 * EOSIE - End of segments interrupt enable (basic mode)
+-		 * EOLNIE - End of links interrupt enable
+-		 */
+-		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE
+-				| FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
+-		break;
+-	case FSL_DMA_IP_83XX:
+-		/* Set the channel to below modes:
+-		 * EOTIE - End-of-transfer interrupt enable
+-		 */
+-		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE,
+-				32);
+-		break;
+-	}
++#include <asm/fsldma.h>
++#include <asm/fsldma_reg.h>
+ 
+-}
+ 
+-static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val)
+-{
+-	DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32);
+-}
+ 
+-static u32 get_sr(struct fsl_dma_chan *fsl_chan)
+-{
+-	return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32);
+-}
++#undef DEBUG
+ 
+-static void set_desc_cnt(struct fsl_dma_chan *fsl_chan,
+-				struct fsl_dma_ld_hw *hw, u32 count)
+-{
+-	hw->count = CPU_TO_DMA(fsl_chan, count, 32);
+-}
+-
+-static void set_desc_src(struct fsl_dma_chan *fsl_chan,
+-				struct fsl_dma_ld_hw *hw, dma_addr_t src)
+-{
+-	u64 snoop_bits;
+-
+-	snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
+-		? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
+-	hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64);
+-}
++#ifdef DEBUG
++#define DPRINTK(fmt, args...) \
++    printk(KERN_DEBUG "%s: " fmt, __FUNCTION__, ## args)
++#else
++#define DPRINTK(fmt, args...)
++#endif
+ 
+-static void set_desc_dest(struct fsl_dma_chan *fsl_chan,
+-				struct fsl_dma_ld_hw *hw, dma_addr_t dest)
+-{
+-	u64 snoop_bits;
++static struct fsl_device *g_device;
++static struct fsl_dma_chan *g_fchan;
+ 
+-	snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
+-		? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
+-	hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64);
+-}
++/* internal functions */
++static int __devinit fsl_init(void);
++static void __devexit fsl_remove(void);
++static void fsl_dma_memcpy_cleanup(struct fsl_dma_chan *fsl_chan);
+ 
+-static void set_desc_next(struct fsl_dma_chan *fsl_chan,
+-				struct fsl_dma_ld_hw *hw, dma_addr_t next)
++static int alloc_dma_channels(struct fsl_device *device)
+ {
+-	u64 snoop_bits;
++	struct fsl_dma_chan *fsl_chan;
+ 
+-	snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
+-		? FSL_DMA_SNEN : 0;
+-	hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64);
+-}
++	device->common.chancnt = FSL_DMA_CH_NUM;
++	fsl_chan = kzalloc(sizeof(*fsl_chan) * device->common.chancnt,
++			   GFP_KERNEL);
++	if (!fsl_chan) {
++		printk("Err: there is not enough memory"
++		       " for channel structures!");
++		return -ENOMEM;
++	}
++	g_fchan = fsl_chan;
+ 
+-static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
+-{
+-	DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64);
++	return device->common.chancnt;
+ }
+ 
+-static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan)
++/* Called for DMA engine initialization */
++int fsl_dma_cfg_arbit_mode(int mode)
+ {
+-	return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN;
+-}
++	fsl_dma_reg *reg;
++	int i;
++	u32 temp;
+ 
+-static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
+-{
+-	DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64);
+-}
++	if (g_device) {
++		spin_lock_bh(&g_device->ch_lock);
++		for (i = 0; i < FSL_DMA_CH_NUM; i++) {
++			if (g_device->ch_stat[i]) {
++				spin_unlock_bh(&g_device->ch_lock);
++				return -EBUSY;
++			}
++		}
++		spin_unlock_bh(&g_device->ch_lock);
+ 
+-static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan)
+-{
+-	return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64);
+-}
++		reg = g_device->reg;
+ 
+-static u32 get_bcr(struct fsl_dma_chan *fsl_chan)
+-{
+-	return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32);
+-}
++		g_device->arbit_mode = mode;
+ 
+-static int dma_is_idle(struct fsl_dma_chan *fsl_chan)
+-{
+-	u32 sr = get_sr(fsl_chan);
+-	return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
+-}
++		if (mode & FSL_DMA_GROUP_FIX) {	/* Group fixed arbitration */
++			out_be32(&reg->dmacr,
++				 FSL_DMA_GPR3PRI(3) | FSL_DMA_GPR2PRI(2)
++				 | FSL_DMA_GPR1PRI(1) | FSL_DMA_GPR0PRI(0));
++		} else {	/* Group round robin arbitration */
++			out_be32(&reg->dmacr, FSL_DMA_DMACR_ERGA_RR);
++		}
+ 
+-static void dma_start(struct fsl_dma_chan *fsl_chan)
+-{
+-	u32 mr_set = 0;;
++		/* Channel round robin arbitration */
++		if (!(mode & FSL_DMA_CH_FIX)) {
++			temp = in_be32(&reg->dmacr);
++			out_be32(&reg->dmacr, temp | FSL_DMA_DMACR_ERCA_RR);
++		}
+ 
+-	if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
+-		DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
+-		mr_set |= FSL_DMA_MR_EMP_EN;
++		return 0;
+ 	} else
+-		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
+-			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
+-				& ~FSL_DMA_MR_EMP_EN, 32);
+-
+-	if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
+-		mr_set |= FSL_DMA_MR_EMS_EN;
+-	else
+-		mr_set |= FSL_DMA_MR_CS;
+-
+-	DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
+-			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
+-			| mr_set, 32);
++		return -EFAULT;
+ }
+ 
+-static void dma_halt(struct fsl_dma_chan *fsl_chan)
++static void free_chan(int channel_num)
+ {
+-	int i;
+-
+-	DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
+-		DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA,
+-		32);
+-	DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
+-		DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS
+-		| FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32);
+-
+-	for (i = 0; i < 100; i++) {
+-		if (dma_is_idle(fsl_chan))
+-			break;
+-		udelay(10);
+-	}
+-	if (i >= 100 && !dma_is_idle(fsl_chan))
+-		dev_err(fsl_chan->dev, "DMA halt timeout!\n");
++	spin_lock_bh(&g_device->ch_lock);
++	g_device->ch_stat[channel_num] = 0;
++	spin_unlock_bh(&g_device->ch_lock);
+ }
+ 
+-static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
+-			struct fsl_desc_sw *desc)
++int fsl_dma_status(int channel_num)
+ {
+-	desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
+-		DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64)	| FSL_DMA_EOL,
+-		64);
+-}
++	fsl_dma_reg *reg;
++	u8 ch;
++	u32 status;
+ 
+-static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
+-		struct fsl_desc_sw *new_desc)
+-{
+-	struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev);
++	if (!g_device) {
++		printk("Err: DMA driver has not been initialized yet!\n");
++		return -1;
++	}
+ 
+-	if (list_empty(&fsl_chan->ld_queue))
+-		return;
++	reg = g_device->reg;
+ 
+-	/* Link to the new descriptor physical address and
+-	 * Enable End-of-segment interrupt for
+-	 * the last link descriptor.
+-	 * (the previous node's next link descriptor)
+-	 *
+-	 * For FSL_DMA_IP_83xx, the snoop enable bit need be set.
+-	 */
+-	queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
+-			new_desc->async_tx.phys | FSL_DMA_EOSIE |
+-			(((fsl_chan->feature & FSL_DMA_IP_MASK)
+-				== FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64);
+-}
++	status = in_be32(&reg->dmaes);
++	if (!(status & FSL_DMA_DMAES_VLD))
++		return 0;
+ 
+-/**
+- * fsl_chan_set_src_loop_size - Set source address hold transfer size
+- * @fsl_chan : Freescale DMA channel
+- * @size     : Address loop size, 0 for disable loop
+- *
+- * The set source address hold transfer size. The source
+- * address hold or loop transfer size is when the DMA transfer
+- * data from source address (SA), if the loop size is 4, the DMA will
+- * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
+- * SA + 1 ... and so on.
+- */
+-static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
+-{
+-	switch (size) {
+-	case 0:
+-		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
+-			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
+-			(~FSL_DMA_MR_SAHE), 32);
+-		break;
+-	case 1:
+-	case 2:
+-	case 4:
+-	case 8:
+-		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
+-			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
+-			FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
+-			32);
+-		break;
+-	}
+-}
++	ch = FSL_DMA_DMAES_ERRCHN(status);
++	printk(KERN_ERR "FSL channel config error: ch%d: ", ch);
+ 
+-/**
+- * fsl_chan_set_dest_loop_size - Set destination address hold transfer size
+- * @fsl_chan : Freescale DMA channel
+- * @size     : Address loop size, 0 for disable loop
+- *
+- * The set destination address hold transfer size. The destination
+- * address hold or loop transfer size is when the DMA transfer
+- * data to destination address (TA), if the loop size is 4, the DMA will
+- * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
+- * TA + 1 ... and so on.
++	if (status & FSL_DMA_DMAES_GPE)
++		printk(KERN_INFO "GPE\n");
++	if (status & FSL_DMA_DMAES_CPE)
++		printk(KERN_INFO "CPE\n");
++	if (status & FSL_DMA_DMAES_SAE)
++		printk(KERN_INFO "SAE\n");
++	if (status & FSL_DMA_DMAES_SOE)
++		printk(KERN_INFO "SOE\n");
++	if (status & FSL_DMA_DMAES_DAE)
++		printk(KERN_INFO "DAE\n");
++	if (status & FSL_DMA_DMAES_DOE)
++		printk(KERN_INFO "DOE\n");
++	if (status & FSL_DMA_DMAES_NCE)
++		printk(KERN_INFO "NCE\n");
++	if (status & FSL_DMA_DMAES_SGE)
++		printk(KERN_INFO "SGE\n");
++	if (status & FSL_DMA_DMAES_SBE)
++		printk(KERN_INFO "SBE\n");
++	if (status & FSL_DMA_DMAES_DBE)
++		printk(KERN_INFO "DBE\n");
++
++	if (ch == channel_num)
++		out_8(&reg->dmacerr, channel_num);
++
++	return (ch + 1);
++}
++
++/* This function is generally called by the driver at open time.
++ * The DMA driver would do any initialization steps that is required
++ * to get the channel ready for data transfer.
++ *
++ * @param channel_id   a pre-defined id. The peripheral driver would specify
++ *                     the id associated with its peripheral. This would be
++ *                     used by the DMA driver to identify the peripheral
++ *                     requesting DMA and do the necessary setup on the
++ *                     channel associated with the particular peripheral.
++ *                     The DMA driver could use static or dynamic DMA channel
++ *                     allocation.
++ * @return returns a negative number on error if request for a DMA channel
++ *                     did not succeed, returns the channel number to be used
++ *                     on success.
+  */
+-static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
++int fsl_dma_chan_request(int channel_id)
+ {
+-	switch (size) {
+-	case 0:
+-		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
+-			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
+-			(~FSL_DMA_MR_DAHE), 32);
+-		break;
+-	case 1:
+-	case 2:
+-	case 4:
+-	case 8:
+-		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
+-			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
+-			FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
+-			32);
+-		break;
++	struct fsl_device *device = g_device;
++	struct fsl_dma_chan *fsl_chan;
++
++	if (!device) {
++		fsl_init();
++		if (!g_device)
++			return -EINVAL;
++		device = g_device;
+ 	}
+-}
+ 
+-/**
+- * fsl_chan_toggle_ext_pause - Toggle channel external pause status
+- * @fsl_chan : Freescale DMA channel
+- * @size     : Pause control size, 0 for disable external pause control.
+- *             The maximum is 1024.
+- *
+- * The Freescale DMA channel can be controlled by the external
+- * signal DREQ#. The pause control size is how many bytes are allowed
+- * to transfer before pausing the channel, after which a new assertion
+- * of DREQ# resumes channel operation.
+- */
+-static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size)
+-{
+-	if (size > 1024)
+-		return;
++	if (channel_id < 0 || channel_id >= FSL_DMA_CH_NUM)
++		return -EINVAL;
+ 
+-	if (size) {
+-		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
+-			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
+-				| ((__ilog2(size) << 24) & 0x0f000000),
+-			32);
+-		fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
+-	} else
+-		fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
+-}
++	fsl_chan = g_fchan + channel_id;
++	spin_lock_bh(&device->ch_lock);
++	if (device->ch_stat[channel_id] == 0) {
++		device->ch_stat[channel_id] = 1;
++		spin_unlock_bh(&device->ch_lock);
++		sema_init(&fsl_chan->sem_lock, 1);
++		return channel_id;
++	}
++	spin_unlock_bh(&device->ch_lock);
+ 
+-/**
+- * fsl_chan_toggle_ext_start - Toggle channel external start status
+- * @fsl_chan : Freescale DMA channel
+- * @enable   : 0 is disabled, 1 is enabled.
+- *
+- * If enable the external start, the channel can be started by an
+- * external DMA start pin. So the dma_start() does not start the
+- * transfer immediately. The DMA channel will wait for the
+- * control pin asserted.
+- */
+-static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
+-{
+-	if (enable)
+-		fsl_chan->feature |= FSL_DMA_CHAN_START_EXT;
+-	else
+-		fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
++	return -EBUSY;
+ }
++EXPORT_SYMBOL(fsl_dma_chan_request);
+ 
+-static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
++void fsl_dma_free_chan(int channel_num)
+ {
+-	struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
+-	struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
+-	unsigned long flags;
+-	dma_cookie_t cookie;
++	struct fsl_dma_chan *fsl_chan = g_fchan + channel_num;
++	fsl_dma_reg *reg = g_device->reg;
+ 
+-	/* cookie increment and adding to ld_queue must be atomic */
+-	spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+-
+-	cookie = fsl_chan->common.cookie;
+-	cookie++;
+-	if (cookie < 0)
+-		cookie = 1;
+-	desc->async_tx.cookie = cookie;
+-	fsl_chan->common.cookie = desc->async_tx.cookie;
+-
+-	append_ld_queue(fsl_chan, desc);
+-	list_splice_init(&desc->async_tx.tx_list, fsl_chan->ld_queue.prev);
++	if (channel_num < 0 || channel_num >= FSL_DMA_CH_NUM)
++		return;
+ 
+-	spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
++	DPRINTK("free channel: %d\n", channel_num);
+ 
+-	return cookie;
+-}
++	free_chan(channel_num);
+ 
+-/**
+- * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
+- * @fsl_chan : Freescale DMA channel
+- *
+- * Return - The descriptor allocated. NULL for failed.
+- */
+-static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
+-					struct fsl_dma_chan *fsl_chan)
+-{
+-	dma_addr_t pdesc;
+-	struct fsl_desc_sw *desc_sw;
++	fsl_dma_memcpy_cleanup(fsl_chan);
+ 
+-	desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc);
+-	if (desc_sw) {
+-		memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
+-		dma_async_tx_descriptor_init(&desc_sw->async_tx,
+-						&fsl_chan->common);
+-		desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
+-		INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
+-		desc_sw->async_tx.phys = pdesc;
+-	}
++	/* Clear enable request */
++	out_8(&reg->dmacerq, channel_num);
+ 
+-	return desc_sw;
++	/* Clear interrupt, error interrupt and error etc. */
++	out_8(&reg->dmaceei, channel_num);
++	out_8(&reg->dmacerr, channel_num);
++	out_8(&reg->dmacint, channel_num);
+ }
++EXPORT_SYMBOL(fsl_dma_free_chan);
+ 
+-
+-/**
+- * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
+- * @fsl_chan : Freescale DMA channel
+- *
+- * This function will create a dma pool for descriptor allocation.
+- *
+- * Return - The number of descriptors allocated.
+- */
+-static int fsl_dma_alloc_chan_resources(struct dma_chan *chan)
++void fsl_dma_enable(int channel_num)
+ {
+-	struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
++	fsl_dma_reg *reg = g_device->reg;
++	u32 *ltcd, *mtcd;
++	int j;
+ 
+-	/* Has this channel already been allocated? */
+-	if (fsl_chan->desc_pool)
+-		return 1;
++	if (channel_num < 0 || channel_num >= FSL_DMA_CH_NUM)
++		return;
+ 
+-	/* We need the descriptor to be aligned to 32bytes
+-	 * for meeting FSL DMA specification requirement.
+-	 */
+-	fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
+-			fsl_chan->dev, sizeof(struct fsl_desc_sw),
+-			32, 0);
+-	if (!fsl_chan->desc_pool) {
+-		dev_err(fsl_chan->dev, "No memory for channel %d "
+-			"descriptor dma pool.\n", fsl_chan->id);
+-		return 0;
+-	}
++	/* Get the address of TCD in local CPU memory space */
++	ltcd = (u32 *) (g_device->tcd + channel_num);
++	mtcd = (u32 *) (g_device->mtcd.addr_va
++			+ channel_num * MAX_TCD_NUM_PER_CH);
+ 
+-	return 1;
+-}
++	/* Clear the local TCD area */
++	memset(ltcd, 0, sizeof(TCD));
+ 
+-/**
+- * fsl_dma_free_chan_resources - Free all resources of the channel.
+- * @fsl_chan : Freescale DMA channel
+- */
+-static void fsl_dma_free_chan_resources(struct dma_chan *chan)
+-{
+-	struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
+-	struct fsl_desc_sw *desc, *_desc;
+-	unsigned long flags;
+-
+-	dev_dbg(fsl_chan->dev, "Free all channel resources.\n");
+-	spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+-	list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
+-#ifdef FSL_DMA_LD_DEBUG
+-		dev_dbg(fsl_chan->dev,
+-				"LD %p will be released.\n", desc);
+-#endif
+-		list_del(&desc->node);
+-		/* free link descriptor */
+-		dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
++	for (j = 0; j < (sizeof(TCD) / 4); j++) {
++		out_be32(ltcd, *mtcd);
++		ltcd++;
++		mtcd++;
+ 	}
+-	spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+-	dma_pool_destroy(fsl_chan->desc_pool);
+ 
+-	fsl_chan->desc_pool = NULL;
++	/* Enable request */
++	out_8(&reg->dmaserq, channel_num);
++	return;
+ }
++EXPORT_SYMBOL(fsl_dma_enable);
+ 
+-static struct dma_async_tx_descriptor *
+-fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
++void fsl_dma_disable(int channel_num)
+ {
+-	struct fsl_dma_chan *fsl_chan;
+-	struct fsl_desc_sw *new;
+-
+-	if (!chan)
+-		return NULL;
+-
+-	fsl_chan = to_fsl_chan(chan);
+-
+-	new = fsl_dma_alloc_descriptor(fsl_chan);
+-	if (!new) {
+-		dev_err(fsl_chan->dev, "No free memory for link descriptor\n");
+-		return NULL;
+-	}
+-
+-	new->async_tx.cookie = -EBUSY;
+-	new->async_tx.flags = flags;
+-
+-	/* Insert the link descriptor to the LD ring */
+-	list_add_tail(&new->node, &new->async_tx.tx_list);
++	fsl_dma_reg *reg = g_device->reg;
++	if (channel_num < 0 || channel_num >= FSL_DMA_CH_NUM)
++		return;
+ 
+-	/* Set End-of-link to the last link descriptor of new list*/
+-	set_ld_eol(fsl_chan, new);
++	/* Clear enable request */
++	out_8(&reg->dmacerq, channel_num);
+ 
+-	return &new->async_tx;
++	return;
+ }
+ 
+-static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
+-	struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
+-	size_t len, unsigned long flags)
++static int off_to_size(size_t off)
+ {
+-	struct fsl_dma_chan *fsl_chan;
+-	struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
+-	size_t copy;
+-	LIST_HEAD(link_chain);
+-
+-	if (!chan)
+-		return NULL;
+-
+-	if (!len)
+-		return NULL;
+-
+-	fsl_chan = to_fsl_chan(chan);
+-
+-	do {
+-
+-		/* Allocate the link descriptor from DMA pool */
+-		new = fsl_dma_alloc_descriptor(fsl_chan);
+-		if (!new) {
+-			dev_err(fsl_chan->dev,
+-					"No free memory for link descriptor\n");
+-			return NULL;
+-		}
+-#ifdef FSL_DMA_LD_DEBUG
+-		dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
+-#endif
++	int i, temp;
+ 
+-		copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
++	/* For PSC FIFO DMA operation
++	 * Destination/source address is fixed as the address
++	 * of FIFO data register, so no address offset is needed
++	 * for this operation, bus size is default 32bit.
++	 */
++	if (!off)
++		return 2;
+ 
+-		set_desc_cnt(fsl_chan, &new->hw, copy);
+-		set_desc_src(fsl_chan, &new->hw, dma_src);
+-		set_desc_dest(fsl_chan, &new->hw, dma_dest);
++	temp = off;
++	for (i = 0; ; i++) {
++		temp = (int)(temp / 2);
++		if (!temp)
++			return i;
++	}
++}
++
++/**
++ * fsl_dma_config - function that initiates a FSL DMA transaction buffers
++ * @channel_num	FSL DMA channel number
++ * @dma_buf 	an array of physical addresses to the user defined
++ *              buffers. The caller must guarantee the dma_buf is
++ *              available until the transfer is completed.
++ * @num_buf     number of buffers in the array
++ * @mode        specifies whether this is READ or WRITE operation
++ * @return 	This function returns a negative number on error if buffer
++ *              could not be added with DMA for transfer. On Success, it
++ *              returns 0
++ */
++int fsl_dma_config(int channel_num, struct fsl_dma_requestbuf *dma_buf,
++		   int num_buf)
++{
++	struct fsl_dma_chan *fsl_chan = g_fchan + channel_num;
++	LIST_HEAD(new_chain);
++	fsl_dma_reg *reg = g_device->reg;
++	int ch = channel_num, i, nbytes, iter;
++	TCD *tcd;
++	dma_addr_t tcd_dma;
++
++	if (channel_num < 0 || channel_num >= FSL_DMA_CH_NUM
++	    || num_buf <= 0 || num_buf > MAX_TCD_NUM_PER_CH)
++		return -EINVAL;
++
++	if (fsl_dma_status(channel_num) != DMA_SUCCESS && fsl_chan->num_buf)
++		return -EBUSY;
++
++	if (down_trylock(&fsl_chan->sem_lock))
++		return -EBUSY;
++	tcd = (TCD *) (g_device->tcd + channel_num);
++
++	/* Use so much descriptor for this transmission */
++	fsl_chan->num_buf = num_buf;
++	fsl_chan->ch_index = channel_num;
++
++	/* Enable error interrupt */
++	out_8(&reg->dmaseei, ch);
++
++	tcd = g_device->mtcd.addr_va + ch * MAX_TCD_NUM_PER_CH;
++	tcd_dma = g_device->mtcd.addr_pa +
++	    ch * MAX_TCD_NUM_PER_CH * sizeof(TCD);
++
++	memset(tcd, 0, sizeof(TCD));
++
++	for (i = 0; i < num_buf; i++) {
++		tcd->saddr = dma_buf[i].src;
++		tcd->daddr = dma_buf[i].dest;
++		tcd->soff = dma_buf[i].soff;
++		tcd->doff = dma_buf[i].doff;
++		tcd->ssize = off_to_size(dma_buf[i].soff);
++		tcd->dsize = off_to_size(dma_buf[i].doff);
++		DPRINTK("doff: %d, soff: %d, dsize: %d, ssize: %d\n",
++			tcd->doff, tcd->soff, tcd->dsize, tcd->ssize);
+ 
+-		if (!first)
+-			first = new;
++		if (dma_buf[i].soff >= dma_buf[i].doff)
++			nbytes = dma_buf[i].minor_loop * dma_buf[i].soff;
+ 		else
+-			set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
+-
+-		new->async_tx.cookie = 0;
+-		async_tx_ack(&new->async_tx);
++			nbytes = dma_buf[i].minor_loop * dma_buf[i].doff;
+ 
+-		prev = new;
+-		len -= copy;
+-		dma_src += copy;
+-		dma_dest += copy;
+-
+-		/* Insert the link descriptor to the LD ring */
+-		list_add_tail(&new->node, &first->async_tx.tx_list);
+-	} while (len);
+-
+-	new->async_tx.flags = flags; /* client is in control of this ack */
+-	new->async_tx.cookie = -EBUSY;
+-
+-	/* Set End-of-link to the last link descriptor of new list*/
+-	set_ld_eol(fsl_chan, new);
+-
+-	return first ? &first->async_tx : NULL;
+-}
+-
+-/**
+- * fsl_dma_update_completed_cookie - Update the completed cookie.
+- * @fsl_chan : Freescale DMA channel
+- */
+-static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan)
+-{
+-	struct fsl_desc_sw *cur_desc, *desc;
+-	dma_addr_t ld_phy;
+-
+-	ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK;
+-
+-	if (ld_phy) {
+-		cur_desc = NULL;
+-		list_for_each_entry(desc, &fsl_chan->ld_queue, node)
+-			if (desc->async_tx.phys == ld_phy) {
+-				cur_desc = desc;
+-				break;
+-			}
+-
+-		if (cur_desc && cur_desc->async_tx.cookie) {
+-			if (dma_is_idle(fsl_chan))
+-				fsl_chan->completed_cookie =
+-					cur_desc->async_tx.cookie;
+-			else
+-				fsl_chan->completed_cookie =
+-					cur_desc->async_tx.cookie - 1;
++		tcd->nbytes = nbytes;
++		tcd->slast = 0;
++		tcd->dlast_sga = 0;
++
++		iter = dma_buf[i].len / nbytes;
++
++		if (tcd->soff && tcd->doff) {
++			tcd->citer_elink = 1;
++			tcd->biter_elink = 1;
++			tcd->citer_linkch = channel_num;
++			if (iter > 0x1ff)
++				panic("iterations won't fit in field");
++			tcd->citer = iter;
++			tcd->biter = iter;
++			tcd->start = 1;
++		} else {
++			/* citer_linkch contains the high bits of iter */
++			tcd->citer_linkch = iter >> 9;
++			tcd->biter_linkch = iter >> 9;
++			tcd->citer = iter & 0x1ff;
++			tcd->biter = iter & 0x1ff;
++			if (i == (num_buf - 1))
++				tcd->d_req = 1;
+ 		}
+-	}
+-}
+ 
+-/**
+- * fsl_chan_ld_cleanup - Clean up link descriptors
+- * @fsl_chan : Freescale DMA channel
+- *
+- * This function clean up the ld_queue of DMA channel.
+- * If 'in_intr' is set, the function will move the link descriptor to
+- * the recycle list. Otherwise, free it directly.
+- */
+-static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan)
+-{
+-	struct fsl_desc_sw *desc, *_desc;
+-	unsigned long flags;
++		tcd->e_sg = 0;
+ 
+-	spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+-
+-	dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n",
+-			fsl_chan->completed_cookie);
+-	list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
+-		dma_async_tx_callback callback;
+-		void *callback_param;
+-
+-		if (dma_async_is_complete(desc->async_tx.cookie,
+-			    fsl_chan->completed_cookie, fsl_chan->common.cookie)
+-				== DMA_IN_PROGRESS)
+-			break;
+-
+-		callback = desc->async_tx.callback;
+-		callback_param = desc->async_tx.callback_param;
+-
+-		/* Remove from ld_queue list */
+-		list_del(&desc->node);
+-
+-		dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n",
+-				desc);
+-		dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
+-
+-		/* Run the link descriptor callback function */
+-		if (callback) {
+-			spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+-			dev_dbg(fsl_chan->dev, "link descriptor %p callback\n",
+-					desc);
+-			callback(callback_param);
+-			spin_lock_irqsave(&fsl_chan->desc_lock, flags);
++		/* For chain mode */
++		if (i != (num_buf - 1)) {
++			tcd->dlast_sga = tcd_dma + (i + 1) * sizeof(TCD);
++			tcd->e_sg = 1;
++		} else {
++			tcd->int_maj = 1;
+ 		}
++
++		DPRINTK("TCD dlast_sga: 0x%08x\n", tcd->dlast_sga);
++		tcd++;
++		memset(tcd, 0, sizeof(TCD));
+ 	}
+-	spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
++	return 0;
+ }
++EXPORT_SYMBOL(fsl_dma_config);
+ 
+-/**
+- * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue.
+- * @fsl_chan : Freescale DMA channel
++/* This function is called only when the channel occurs error
++ * or has completed transaction.
+  */
+-static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
++static void fsl_dma_memcpy_cleanup(struct fsl_dma_chan *chan)
+ {
+-	struct list_head *ld_node;
+-	dma_addr_t next_dest_addr;
+-	unsigned long flags;
+-
+-	if (!dma_is_idle(fsl_chan))
+-		return;
++	int ch;
+ 
+-	dma_halt(fsl_chan);
++	chan->status = g_device->reg->dmaes;
+ 
+-	/* If there are some link descriptors
+-	 * not transfered in queue. We need to start it.
+-	 */
+-	spin_lock_irqsave(&fsl_chan->desc_lock, flags);
++	ch = fsl_dma_status(chan->ch_index);
++	if (ch)
++		ch = ch - 1;
+ 
+-	/* Find the first un-transfer desciptor */
+-	for (ld_node = fsl_chan->ld_queue.next;
+-		(ld_node != &fsl_chan->ld_queue)
+-			&& (dma_async_is_complete(
+-				to_fsl_desc(ld_node)->async_tx.cookie,
+-				fsl_chan->completed_cookie,
+-				fsl_chan->common.cookie) == DMA_SUCCESS);
+-		ld_node = ld_node->next);
+-
+-	spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+-
+-	if (ld_node != &fsl_chan->ld_queue) {
+-		/* Get the ld start address from ld_queue */
+-		next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
+-		dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n",
+-				(void *)next_dest_addr);
+-		set_cdar(fsl_chan, next_dest_addr);
+-		dma_start(fsl_chan);
+-	} else {
+-		set_cdar(fsl_chan, 0);
+-		set_ndar(fsl_chan, 0);
++	if (ch == chan->ch_index) {
++		DPRINTK("Channel %d halted, chanerr = %x\n", ch, chan->status);
+ 	}
+ }
+ 
+-/**
+- * fsl_dma_memcpy_issue_pending - Issue the DMA start command
+- * @fsl_chan : Freescale DMA channel
+- */
+-static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan)
++static void fsl_dma_isr_bh(u32 intst, u32 err, u32 high)
+ {
+-	struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
+-
+-#ifdef FSL_DMA_LD_DEBUG
+-	struct fsl_desc_sw *ld;
+-	unsigned long flags;
+-
+-	spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+-	if (list_empty(&fsl_chan->ld_queue)) {
+-		spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+-		return;
+-	}
+-
+-	dev_dbg(fsl_chan->dev, "--memcpy issue--\n");
+-	list_for_each_entry(ld, &fsl_chan->ld_queue, node) {
+-		int i;
+-		dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n",
+-				fsl_chan->id, ld->async_tx.phys);
+-		for (i = 0; i < 8; i++)
+-			dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n",
+-					i, *(((u32 *)&ld->hw) + i));
++	struct fsl_device *device = g_device;
++	struct fsl_dma_chan *fsl_chan;
++	fsl_dma_reg *reg;
++	u32 i, ch_base = 0, ch;
++	u32 error;
++
++	reg = device->reg;
++	if (high)
++		ch_base = 32;
++
++	for (i = 0; i < 32; i++) {
++		error = 0;
++		if (intst & (1 << i)) {
++			if (err & (1 << i))
++				error = in_be32(&reg->dmaes);
++			ch = i + ch_base;
++			fsl_chan = g_fchan + ch;
++			DPRINTK("channel %d occurs an interrupt\n", ch);
++
++			/* Clear interrupt request */
++			out_8(&reg->dmacint, ch);
++
++			/* Clear enable error interrupt */
++			out_8(&reg->dmaceei, ch);
++
++			up(&fsl_chan->sem_lock);
++			if (fsl_chan->cb_fn)
++				fsl_chan->cb_fn(fsl_chan->cb_args, error);
++		}
+ 	}
+-	dev_dbg(fsl_chan->dev, "----------------\n");
+-	spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+-#endif
+-
+-	fsl_chan_xfer_ld_queue(fsl_chan);
++	return;
+ }
+-
+-/**
+- * fsl_dma_is_complete - Determine the DMA status
+- * @fsl_chan : Freescale DMA channel
+- */
+-static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
+-					dma_cookie_t cookie,
+-					dma_cookie_t *done,
+-					dma_cookie_t *used)
++/*
++cys add 
++the function used for recorved lost dma irq.
++*/
++int fsl_dma_up_semaphore(unsigned int channel)
+ {
+-	struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
+-	dma_cookie_t last_used;
+-	dma_cookie_t last_complete;
+-
+-	fsl_chan_ld_cleanup(fsl_chan);
+-
+-	last_used = chan->cookie;
+-	last_complete = fsl_chan->completed_cookie;
+-
+-	if (done)
+-		*done = last_complete;
+-
+-	if (used)
+-		*used = last_used;
+-
+-	return dma_async_is_complete(cookie, last_complete, last_used);
++	struct fsl_device *device = g_device;
++	struct fsl_dma_chan *fsl_chan;
++	fsl_chan = g_fchan + channel;
++	up(&fsl_chan->sem_lock);
++	return 0;
+ }
+-
+-static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
++EXPORT_SYMBOL(fsl_dma_up_semaphore);
++static irqreturn_t fsl_do_interrupt(int irq, void *data)
+ {
+-	struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
+-	u32 stat;
+-	int update_cookie = 0;
+-	int xfer_ld_q = 0;
+-
+-	stat = get_sr(fsl_chan);
+-	dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n",
+-						fsl_chan->id, stat);
+-	set_sr(fsl_chan, stat);		/* Clear the event register */
+-
+-	stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
+-	if (!stat)
+-		return IRQ_NONE;
+-
+-	if (stat & FSL_DMA_SR_TE)
+-		dev_err(fsl_chan->dev, "Transfer Error!\n");
+-
+-	/* Programming Error
+-	 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
+-	 * triger a PE interrupt.
+-	 */
+-	if (stat & FSL_DMA_SR_PE) {
+-		dev_dbg(fsl_chan->dev, "event: Programming Error INT\n");
+-		if (get_bcr(fsl_chan) == 0) {
+-			/* BCR register is 0, this is a DMA_INTERRUPT async_tx.
+-			 * Now, update the completed cookie, and continue the
+-			 * next uncompleted transfer.
+-			 */
+-			update_cookie = 1;
+-			xfer_ld_q = 1;
+-		}
+-		stat &= ~FSL_DMA_SR_PE;
+-	}
++	struct fsl_device *device = g_device;
++	fsl_dma_reg *reg;
++	u32 inth, intl, eeih, eeil;
++	u32 errh, errl;
++
++	DPRINTK("receive one interrupt!\n");
++	if (!device)
++	    return NO_IRQ;
++	reg = device->reg;
++	inth = in_be32(&reg->dmainth);
++	intl = in_be32(&reg->dmaintl);
++	eeih = in_be32(&reg->dmaeeih);
++	eeil = in_be32(&reg->dmaeeil);
++
++	errh = in_be32(&reg->dmaerrh);
++	errl = in_be32(&reg->dmaerrl);
++
++	inth &= eeih;
++	intl &= eeil;
+ 
+-	/* If the link descriptor segment transfer finishes,
+-	 * we will recycle the used descriptor.
+-	 */
+-	if (stat & FSL_DMA_SR_EOSI) {
+-		dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
+-		dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n",
+-			(void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan));
+-		stat &= ~FSL_DMA_SR_EOSI;
+-		update_cookie = 1;
+-	}
++	DPRINTK("es:0x%08x\n", in_be32(&reg->dmaes));
+ 
+-	/* For MPC8349, EOCDI event need to update cookie
+-	 * and start the next transfer if it exist.
+-	 */
+-	if (stat & FSL_DMA_SR_EOCDI) {
+-		dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n");
+-		stat &= ~FSL_DMA_SR_EOCDI;
+-		update_cookie = 1;
+-		xfer_ld_q = 1;
+-	}
++	/* Clear all interrupt request */
++	out_8(&reg->dmacint, 0x7f);
+ 
+-	/* If it current transfer is the end-of-transfer,
+-	 * we should clear the Channel Start bit for
+-	 * prepare next transfer.
+-	 */
+-	if (stat & FSL_DMA_SR_EOLNI) {
+-		dev_dbg(fsl_chan->dev, "event: End-of-link INT\n");
+-		stat &= ~FSL_DMA_SR_EOLNI;
+-		xfer_ld_q = 1;
+-	}
++	if (!(inth & eeih) && !(intl & eeil))
++		return IRQ_NONE;
+ 
+-	if (update_cookie)
+-		fsl_dma_update_completed_cookie(fsl_chan);
+-	if (xfer_ld_q)
+-		fsl_chan_xfer_ld_queue(fsl_chan);
+-	if (stat)
+-		dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n",
+-					stat);
++	fsl_dma_isr_bh(inth, errh, 1);
++	fsl_dma_isr_bh(intl, errl, 0);
+ 
+-	dev_dbg(fsl_chan->dev, "event: Exit\n");
+-	tasklet_schedule(&fsl_chan->tasklet);
+ 	return IRQ_HANDLED;
+ }
+ 
+-static irqreturn_t fsl_dma_do_interrupt(int irq, void *data)
++int fsl_dma_callback_set(int channel_num, fsl_dma_callback_t callback,
++			 void *arg)
+ {
+-	struct fsl_dma_device *fdev = (struct fsl_dma_device *)data;
+-	u32 gsr;
+-	int ch_nr;
++	struct fsl_dma_chan *fsl_chan = g_fchan + channel_num;
+ 
+-	gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base)
+-			: in_le32(fdev->reg_base);
+-	ch_nr = (32 - ffs(gsr)) / 8;
++	if (channel_num < 0 || channel_num >= FSL_DMA_CH_NUM)
++		return -EINVAL;
+ 
+-	return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq,
+-			fdev->chan[ch_nr]) : IRQ_NONE;
+-}
++	if (fsl_dma_status(channel_num) == DMA_IN_PROGRESS)
++		return -EBUSY;
+ 
+-static void dma_do_tasklet(unsigned long data)
+-{
+-	struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
+-	fsl_chan_ld_cleanup(fsl_chan);
++	fsl_chan->cb_fn = callback;
++	fsl_chan->cb_args = arg;
++
++	return 0;
+ }
++EXPORT_SYMBOL(fsl_dma_callback_set);
+ 
+-static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev,
+-	struct device_node *node, u32 feature, const char *compatible)
++/*
++ * Perform a FSL transaction to verify the HW works.
++ */
++#define FSL_TEST_SIZE 0x200
++
++static int fsl_self_test(struct fsl_device *device)
+ {
+-	struct fsl_dma_chan *new_fsl_chan;
+-	int err;
++	struct fsl_dma_requestbuf buf[3];
++	u8 *src0, *dest0;
++	u8 *src1, *dest1;
++	u8 *src2, *dest2;
++	dma_addr_t sphyaddr0, dphyaddr0;
++	dma_addr_t sphyaddr1, dphyaddr1;
++	dma_addr_t sphyaddr2, dphyaddr2;
++	int ch;
++	dma_cookie_t cookie;
++	int i, err = 0;
+ 
+-	/* alloc channel */
+-	new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL);
+-	if (!new_fsl_chan) {
+-		dev_err(fdev->dev, "No free memory for allocating "
+-				"dma channels!\n");
++	src0 = dma_alloc_coherent(NULL, sizeof(u8) * FSL_TEST_SIZE,
++				  &sphyaddr0, GFP_KERNEL);
++	src1 = dma_alloc_coherent(NULL, sizeof(u8) * FSL_TEST_SIZE,
++				  &sphyaddr1, GFP_KERNEL);
++	src2 = dma_alloc_coherent(NULL, sizeof(u8) * FSL_TEST_SIZE,
++				  &sphyaddr2, GFP_KERNEL);
++	if (!src0 || !src1 || !src2)
+ 		return -ENOMEM;
+-	}
+-
+-	/* get dma channel register base */
+-	err = of_address_to_resource(node, 0, &new_fsl_chan->reg);
+-	if (err) {
+-		dev_err(fdev->dev, "Can't get %s property 'reg'\n",
+-				node->full_name);
+-		goto err_no_reg;
+-	}
+-
+-	new_fsl_chan->feature = feature;
+-
+-	if (!fdev->feature)
+-		fdev->feature = new_fsl_chan->feature;
+-
+-	/* If the DMA device's feature is different than its channels',
+-	 * report the bug.
+-	 */
+-	WARN_ON(fdev->feature != new_fsl_chan->feature);
+ 
+-	new_fsl_chan->dev = fdev->dev;
+-	new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
+-			new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
+-
+-	new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
+-	if (new_fsl_chan->id > FSL_DMA_MAX_CHANS_PER_DEVICE) {
+-		dev_err(fdev->dev, "There is no %d channel!\n",
+-				new_fsl_chan->id);
+-		err = -EINVAL;
+-		goto err_no_chan;
+-	}
+-	fdev->chan[new_fsl_chan->id] = new_fsl_chan;
+-	tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet,
+-			(unsigned long)new_fsl_chan);
+-
+-	/* Init the channel */
+-	dma_init(new_fsl_chan);
+-
+-	/* Clear cdar registers */
+-	set_cdar(new_fsl_chan, 0);
+-
+-	switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) {
+-	case FSL_DMA_IP_85XX:
+-		new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start;
+-		new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
+-	case FSL_DMA_IP_83XX:
+-		new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size;
+-		new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size;
++	dest0 = dma_alloc_coherent(NULL, sizeof(u8) * FSL_TEST_SIZE,
++				   &dphyaddr0, GFP_KERNEL);
++	dest1 = dma_alloc_coherent(NULL, sizeof(u8) * FSL_TEST_SIZE,
++				   &dphyaddr1, GFP_KERNEL);
++	dest2 = dma_alloc_coherent(NULL, sizeof(u8) * FSL_TEST_SIZE,
++				   &dphyaddr2, GFP_KERNEL);
++	if (!dest0 || !dest1 || !dest2) {
++		dma_free_coherent(NULL, sizeof(u8) * FSL_TEST_SIZE, src0,
++				  sphyaddr0);
++		dma_free_coherent(NULL, sizeof(u8) * FSL_TEST_SIZE, src1,
++				  sphyaddr1);
++		return -ENOMEM;
+ 	}
+ 
+-	spin_lock_init(&new_fsl_chan->desc_lock);
+-	INIT_LIST_HEAD(&new_fsl_chan->ld_queue);
+-
+-	new_fsl_chan->common.device = &fdev->common;
+-
+-	/* Add the channel to DMA device channel list */
+-	list_add_tail(&new_fsl_chan->common.device_node,
+-			&fdev->common.channels);
+-	fdev->common.chancnt++;
+-
+-	new_fsl_chan->irq = irq_of_parse_and_map(node, 0);
+-	if (new_fsl_chan->irq != NO_IRQ) {
+-		err = request_irq(new_fsl_chan->irq,
+-					&fsl_dma_chan_do_interrupt, IRQF_SHARED,
+-					"fsldma-channel", new_fsl_chan);
+-		if (err) {
+-			dev_err(fdev->dev, "DMA channel %s request_irq error "
+-				"with return %d\n", node->full_name, err);
+-			goto err_no_irq;
+-		}
++	memset(dest0, 0, FSL_TEST_SIZE);
++	memset(dest1, 0, FSL_TEST_SIZE);
++	memset(dest2, 0, FSL_TEST_SIZE);
++
++	/* Fill in src buffer */
++	for (i = 0; i < FSL_TEST_SIZE; i++) {
++		src0[i] = (u8) i;
++		src1[i] = (u8) i;
++		src2[i] = (u8) i;
++	}
++
++	/* Set arbitration mode chj */
++	fsl_dma_cfg_arbit_mode(FSL_DMA_GROUP_FIX | FSL_DMA_CH_FIX);
++
++	/* Search for one available dma channel */
++	ch = fsl_dma_chan_request(32);
++	if (ch < 0) {
++		err = -ENODEV;
++		goto out;
++	}
++
++	/* Both source and destination port size: 32 bits */
++	buf[0].src = sphyaddr0;
++	buf[0].dest = dphyaddr0;
++	buf[0].soff = 4;
++	buf[0].doff = 1;
++	buf[0].len = FSL_TEST_SIZE;
++	buf[0].minor_loop = 8;	/* Minor bytes: 32 */
++
++	buf[1].src = sphyaddr1;
++	buf[1].dest = dphyaddr1;
++	buf[1].soff = 4;
++	buf[1].doff = 1;
++	buf[1].len = FSL_TEST_SIZE;
++	buf[1].minor_loop = 8;	/* Minor bytes: 32 */
++
++	buf[2].src = sphyaddr2;
++	buf[2].dest = dphyaddr2;
++	buf[2].soff = 4;
++	buf[2].doff = 1;
++	buf[2].len = FSL_TEST_SIZE;
++	buf[2].minor_loop = 8;	/* Minor bytes: 32 */
++
++	cookie = fsl_dma_config(ch, &buf[0], 3);
++	fsl_dma_enable(ch);
++	msleep(100);
++
++	if (fsl_dma_status(ch) != DMA_SUCCESS) {
++		printk(KERN_ERR
++		       "fsldma: Self-test copy timed out, disabling\n");
++		err = -ENODEV;
++		goto free_resources;
++	}
++	if (memcmp(src0, dest0, FSL_TEST_SIZE) ||
++	    memcmp(src1, dest1, FSL_TEST_SIZE) ||
++	    memcmp(src2, dest2, FSL_TEST_SIZE)) {
++		printk(KERN_ERR
++		       "fsldma: Self-test copy failed compare, disabling\n");
++		err = -ENODEV;
++		fsl_dma_status(ch);
++		goto free_resources;
++	} else {
++		printk("fsldma: Self-test copy successfully\n");
+ 	}
+ 
+-	dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id,
+-		 compatible,
+-		 new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq);
+-
+-	return 0;
+-
+-err_no_irq:
+-	list_del(&new_fsl_chan->common.device_node);
+-err_no_chan:
+-	iounmap(new_fsl_chan->reg_base);
+-err_no_reg:
+-	kfree(new_fsl_chan);
++free_resources:
++	fsl_dma_free_chan(ch);
++out:
++	dma_free_coherent(NULL, FSL_TEST_SIZE, src0, sphyaddr0);
++	dma_free_coherent(NULL, FSL_TEST_SIZE, dest0, dphyaddr0);
++	dma_free_coherent(NULL, FSL_TEST_SIZE, src1, sphyaddr1);
++	dma_free_coherent(NULL, FSL_TEST_SIZE, dest1, dphyaddr1);
+ 	return err;
+ }
+ 
+-static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan)
+-{
+-	if (fchan->irq != NO_IRQ)
+-		free_irq(fchan->irq, fchan);
+-	list_del(&fchan->common.device_node);
+-	iounmap(fchan->reg_base);
+-	kfree(fchan);
+-}
+-
+-static int __devinit of_fsl_dma_probe(struct of_device *dev,
+-			const struct of_device_id *match)
++static int __devinit fsl_init(void)
+ {
+ 	int err;
+-	struct fsl_dma_device *fdev;
+-	struct device_node *child;
++	unsigned long base_addr;
++	fsl_dma_reg *reg;
++	TCD *tcd;
++	struct fsl_device *device;
++	struct device_node *np;
++	struct resource r;
++	u32 mask, offset;
+ 
+-	fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
+-	if (!fdev) {
+-		dev_err(&dev->dev, "No enough memory for 'priv'\n");
+-		return -ENOMEM;
+-	}
+-	fdev->dev = &dev->dev;
+-	INIT_LIST_HEAD(&fdev->common.channels);
+-
+-	/* get DMA controller register base */
+-	err = of_address_to_resource(dev->node, 0, &fdev->reg);
+-	if (err) {
+-		dev_err(&dev->dev, "Can't get %s property 'reg'\n",
+-				dev->node->full_name);
+-		goto err_no_reg;
+-	}
+-
+-	dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
+-			"controller at %p...\n",
+-			match->compatible, (void *)fdev->reg.start);
+-	fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
+-						- fdev->reg.start + 1);
+-
+-	dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
+-	dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
+-	fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
+-	fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
+-	fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
+-	fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
+-	fdev->common.device_is_tx_complete = fsl_dma_is_complete;
+-	fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
+-	fdev->common.dev = &dev->dev;
+-
+-	fdev->irq = irq_of_parse_and_map(dev->node, 0);
+-	if (fdev->irq != NO_IRQ) {
+-		err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED,
+-					"fsldma-device", fdev);
+-		if (err) {
+-			dev_err(&dev->dev, "DMA device request_irq error "
+-				"with return %d\n", err);
+-			goto err;
+-		}
+-	}
++	if (g_device)
++		return 0;
+ 
+-	dev_set_drvdata(&(dev->dev), fdev);
++	/* Map the virtual IRQ number from device tree */
++	np = of_find_compatible_node(NULL, NULL, "mpc512x-dma2");
++	if (!np) {
++		printk(KERN_ERR "Err: no 'mpc512x-dma2' in device tree!\n");
++		return -EINVAL;
++	}
++
++	/* DMA register space */
++	of_address_to_resource(np, 0, &r);
++	of_node_put(np);
++	DPRINTK("DMA engine register address: 0x%08x\n", r.start);
++	reg = (fsl_dma_reg *) ioremap(r.start, sizeof(fsl_dma_reg));
++	if (!reg) {
++		err = -ENOMEM;
++		goto err_regioremap;
++	}
++
++	/* DMA transfer control desciptor area */
++	base_addr = r.start + FSL_DMA_TCD_OFFSET;
++	DPRINTK("Local TCD start address: 0x%08x\n", (u32) base_addr);
++	tcd = (TCD *) ioremap(base_addr, sizeof(TCD) * FSL_DMA_CH_NUM);
++	if (!tcd) {
++		err = -ENOMEM;
++		goto err_tcdioremap;
++	}
++
++	device = kzalloc(sizeof(*device), GFP_KERNEL);
++	if (!device) {
++		err = -ENOMEM;
++		goto err_kzalloc;
++	}
++
++	device->irq = irq_of_parse_and_map(np, 0);
++	of_node_put(np);
++
++	err = request_irq(device->irq, &fsl_do_interrupt,
++			  IRQF_SHARED, "mpc5121dma", device);
++	if (err)
++		goto err_irq;
++
++	spin_lock_init(&device->ch_lock);
++	device->reg = reg;
++	device->tcd = tcd;
++	g_device = device;
++
++	/* Allocate buffer for TCDs in memory */
++	device->mtcd.size = (MAX_TCD_NUM_PER_CH * FSL_DMA_CH_NUM + 1)
++	    * sizeof(TCD);
++	device->mtcd.addr_v =
++	    (TCD *) dma_alloc_coherent(NULL, device->mtcd.size,
++				       &device->mtcd.addr_p, GFP_KERNEL);
++	mask = sizeof(TCD) - 1;
++	offset = device->mtcd.addr_p & mask;
++	device->mtcd.addr_va = device->mtcd.addr_v;
++	device->mtcd.addr_pa = device->mtcd.addr_p;
++	if (offset) {
++		offset = sizeof(TCD) - offset;
++		device->mtcd.addr_pa = device->mtcd.addr_p + offset;
++		device->mtcd.addr_va = (TCD *) ((u32) device->mtcd.addr_v
++						+ offset);
++		DPRINTK("Note: TCD buffer address is re-aligned:"
++			" offset: 0x%x\n", offset);
++	}
++	DPRINTK("tcd buf phy addr: 0x%08x\n", device->mtcd.addr_pa);
++
++	alloc_dma_channels(device);
++	printk(KERN_INFO "Freescale(R) MPC5121 DMA Engine found, %d channels\n",
++	       FSL_DMA_CH_NUM);
++
++	err = fsl_self_test(device);
++	if (err)
++		goto err_self_test;
+ 
+-	/* We cannot use of_platform_bus_probe() because there is no
+-	 * of_platform_bus_remove.  Instead, we manually instantiate every DMA
+-	 * channel object.
+-	 */
+-	for_each_child_of_node(dev->node, child) {
+-		if (of_device_is_compatible(child, "fsl,eloplus-dma-channel"))
+-			fsl_dma_chan_probe(fdev, child,
+-				FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
+-				"fsl,eloplus-dma-channel");
+-		if (of_device_is_compatible(child, "fsl,elo-dma-channel"))
+-			fsl_dma_chan_probe(fdev, child,
+-				FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
+-				"fsl,elo-dma-channel");
+-	}
+-
+-	dma_async_device_register(&fdev->common);
+ 	return 0;
+ 
+-err:
+-	iounmap(fdev->reg_base);
+-err_no_reg:
+-	kfree(fdev);
++err_irq:
++err_kzalloc:
++err_self_test:
++	kfree(device);
++	dma_free_coherent(NULL, device->mtcd.size,
++			  device->mtcd.addr_v, device->mtcd.addr_p);
++err_tcdioremap:
++	iounmap(tcd);
++err_regioremap:
++	iounmap(reg);
+ 	return err;
+ }
+ 
+-static int of_fsl_dma_remove(struct of_device *of_dev)
++static void __devexit fsl_remove(void)
+ {
+-	struct fsl_dma_device *fdev;
+-	unsigned int i;
+-
+-	fdev = dev_get_drvdata(&of_dev->dev);
+-
+-	dma_async_device_unregister(&fdev->common);
++	struct fsl_device *device;
+ 
+-	for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++)
+-		if (fdev->chan[i])
+-			fsl_dma_chan_remove(fdev->chan[i]);
+-
+-	if (fdev->irq != NO_IRQ)
+-		free_irq(fdev->irq, fdev);
+-
+-	iounmap(fdev->reg_base);
++	if (!g_device)
++		return;
++	device = g_device;
+ 
+-	kfree(fdev);
+-	dev_set_drvdata(&of_dev->dev, NULL);
++	free_irq(device->irq, device);
++	iounmap(device->reg);
++	iounmap(device->tcd);
++	dma_free_coherent(NULL, device->mtcd.size,
++			  device->mtcd.addr_v, device->mtcd.addr_p);
++	kfree(device);
++}
+ 
++static int __devinit of_fsl_dma_probe(struct of_device *op, const struct of_device_id *match)
++{
++	fsl_init();
+ 	return 0;
+ }
+ 
+-static struct of_device_id of_fsl_dma_ids[] = {
+-	{ .compatible = "fsl,eloplus-dma", },
+-	{ .compatible = "fsl,elo-dma", },
++static void of_fsl_dma_remove(struct of_device *op)
++{
++	fsl_remove();
++}
++
++
++static struct of_device_id of_fsl_dma_ids[] = {	
++	{ .compatible = "mpc512x-dma2", },
+ 	{}
+ };
+ 
+ static struct of_platform_driver of_fsl_dma_driver = {
+-	.name = "fsl-elo-dma",
++	.name = "fsl-mpc5121e-dma",
+ 	.match_table = of_fsl_dma_ids,
+ 	.probe = of_fsl_dma_probe,
+ 	.remove = of_fsl_dma_remove,
+ };
+-
+ static __init int of_fsl_dma_init(void)
+ {
+ 	int ret;
+diff -Naur linux-2.6.29/drivers/i2c/busses/i2c-mpc.c linux-2.6.29-v2010041601/drivers/i2c/busses/i2c-mpc.c
+--- linux-2.6.29/drivers/i2c/busses/i2c-mpc.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/i2c/busses/i2c-mpc.c	2010-04-13 20:23:26.000000000 +0200
+@@ -313,7 +313,12 @@
+ 	.algo = &mpc_algo,
+ 	.timeout = 1,
+ };
+-
++#if	CONFIG_MPC5121_ADS
++static u32 g_i2c_ioctrol[][2]={
++{0x8000a1d8,0x8000a1dc},
++{0x8000a1e0,0x8000a1e4},
++};
++#endif
+ static int __devinit fsl_i2c_probe(struct of_device *op, const struct of_device_id *match)
+ {
+ 	int result = 0;
+@@ -356,6 +361,27 @@
+ 	i2c->adap = mpc_ops;
+ 	i2c_set_adapdata(&i2c->adap, i2c);
+ 	i2c->adap.dev.parent = &op->dev;
++#if	CONFIG_MPC5121_ADS
++	{
++		unsigned int *val;
++		u32 __iomem *base;
++		val=of_get_property(op->node, "cell-index", NULL);		
++		if(*val<2)
++		{
++				
++				base=ioremap(g_i2c_ioctrol[*val][0], sizeof(u32));
++				*base=0x00;
++				iounmap(base);
++				base=ioremap(g_i2c_ioctrol[*val][1], sizeof(u32));
++				*base=0x00;
++				iounmap(base);
++				printk("Detected i2c host %d \n",*val);
++		}
++			
++		
++	
++	}
++#endif
+ 
+ 	result = i2c_add_adapter(&i2c->adap);
+ 	if (result < 0) {
+diff -Naur linux-2.6.29/drivers/ide/ide-dma.c linux-2.6.29-v2010041601/drivers/ide/ide-dma.c
+--- linux-2.6.29/drivers/ide/ide-dma.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/ide/ide-dma.c	2010-04-13 20:23:26.000000000 +0200
+@@ -254,10 +254,12 @@
+ 		/*
+ 		 * avoid false cable warning from eighty_ninty_three()
+ 		 */
++#ifndef CONFIG_PPC_MPC512x
+ 		if (req_mode > XFER_UDMA_2) {
+ 			if ((mask & 0x78) && (eighty_ninty_three(drive) == 0))
+ 				mask &= 0x07;
+ 		}
++#endif
+ 		break;
+ 	case XFER_MW_DMA_0:
+ 		if ((id[ATA_ID_FIELD_VALID] & 2) == 0)
+diff -Naur linux-2.6.29/drivers/ide/Kconfig linux-2.6.29-v2010041601/drivers/ide/Kconfig
+--- linux-2.6.29/drivers/ide/Kconfig	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/ide/Kconfig	2010-04-13 20:23:26.000000000 +0200
+@@ -278,6 +278,14 @@
+ 	  <file:Documentation/ide/ide.txt>. If you have a CMD640 IDE interface
+ 	  and your BIOS does not already do this for you, then say Y here.
+ 	  Otherwise say N.
++config BLK_DEV_MPC512x_IDE
++	tristate "MPC512x IDE support"
++	depends on PPC_MPC512x 
++	select BLK_DEV_IDEDMA_PCI
++	help
++	  This option provides support for IDE on Freescale MPC512x Systems.
++
++	  If unsure, say N.
+ 
+ config BLK_DEV_IDEPNP
+ 	tristate "PNP EIDE support"
+@@ -914,6 +922,6 @@
+ 
+ config BLK_DEV_IDEDMA
+ 	def_bool BLK_DEV_IDEDMA_SFF || \
+-		 BLK_DEV_IDEDMA_ICS || BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
++		 BLK_DEV_IDEDMA_ICS || BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA||BLK_DEV_MPC512x_IDE
+ 
+ endif # IDE
+diff -Naur linux-2.6.29/drivers/ide/Makefile linux-2.6.29-v2010041601/drivers/ide/Makefile
+--- linux-2.6.29/drivers/ide/Makefile	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/ide/Makefile	2010-04-13 20:23:26.000000000 +0200
+@@ -117,3 +117,4 @@
+ obj-$(CONFIG_BLK_DEV_IDE_TX4938)	+= tx4938ide.o
+ obj-$(CONFIG_BLK_DEV_IDE_TX4939)	+= tx4939ide.o
+ obj-$(CONFIG_BLK_DEV_IDE_AT91)		+= at91_ide.o
++obj-$(CONFIG_BLK_DEV_MPC512x_IDE)	+= ppc/
+diff -Naur linux-2.6.29/drivers/ide/ppc/Makefile linux-2.6.29-v2010041601/drivers/ide/ppc/Makefile
+--- linux-2.6.29/drivers/ide/ppc/Makefile	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/ide/ppc/Makefile	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,4 @@
++
++obj-$(CONFIG_BLK_DEV_MPC512x_IDE)		+= mpc512x_ide.o
++
++EXTRA_CFLAGS	:= -Idrivers/ide
+diff -Naur linux-2.6.29/drivers/ide/ppc/mpc512x.h linux-2.6.29-v2010041601/drivers/ide/ppc/mpc512x.h
+--- linux-2.6.29/drivers/ide/ppc/mpc512x.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/ide/ppc/mpc512x.h	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,185 @@
++/*
++ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef _FSL_ATA_H_
++#define _FSL_ATA_H_
++
++/*!
++ * @defgroup ATA ATA/IDE Driver
++ */
++
++/*!
++ * @file mpc512x_ide.h
++ *
++ * @brief MPC512X ATA/IDE hardware register and bit definitions.
++ *
++ * @ingroup ATA
++ */
++#include <asm/fsldma.h>
++#include <asm/fsldma_reg.h>
++
++
++#define HWIF(drive)		((ide_hwif_t *)((drive)->hwif))
++#define HWGROUP(drive)		((ide_hwgroup_t *)(HWIF(drive)->hwgroup))
++
++#define ATA_BASE_ADDR (priv->ata_regs)
++#define IO_ADDRESS(addr) (addr)
++
++#define FSL_ATA_IO   IO_ADDRESS((ATA_BASE_ADDR + 0xA0))
++#define FSL_ATA_CTL  IO_ADDRESS((ATA_BASE_ADDR + 0xD8))
++
++/*
++ * Interface control registers
++ */
++
++#define FSL_ATA_FIFO_DATA_32    IO_ADDRESS((ATA_BASE_ADDR + 0x18))
++#define FSL_ATA_FIFO_DATA_16    IO_ADDRESS((ATA_BASE_ADDR + 0x1C))
++#define FSL_ATA_FIFO_FILL       IO_ADDRESS((ATA_BASE_ADDR + 0x20))
++#define FSL_ATA_CONTROL		IO_ADDRESS((ATA_BASE_ADDR + 0x24))
++#define FSL_ATA_INTR_PENDING    IO_ADDRESS((ATA_BASE_ADDR + 0x28))
++#define FSL_ATA_INTR_ENABLE     IO_ADDRESS((ATA_BASE_ADDR + 0x2C))
++#define FSL_ATA_INTR_CLEAR      IO_ADDRESS((ATA_BASE_ADDR + 0x30))
++#define FSL_ATA_FIFO_ALARM      IO_ADDRESS((ATA_BASE_ADDR + 0x34))
++
++/*
++ * Control register bit definitions
++ */
++
++#define FSL_ATA_CTRL_FIFO_RST_B      0x80
++#define FSL_ATA_CTRL_ATA_RST_B       0x40
++#define FSL_ATA_CTRL_FIFO_TX_EN      0x20
++#define FSL_ATA_CTRL_FIFO_RCV_EN     0x10
++#define FSL_ATA_CTRL_DMA_PENDING     0x08
++#define FSL_ATA_CTRL_DMA_ULTRA       0x04
++#define FSL_ATA_CTRL_DMA_WRITE       0x02
++#define FSL_ATA_CTRL_IORDY_EN        0x01
++
++/*
++ * Interrupt registers bit definitions
++ */
++
++#define FSL_ATA_INTR_ATA_INTRQ1      0x80
++#define FSL_ATA_INTR_FIFO_UNDERFLOW  0x40
++#define FSL_ATA_INTR_FIFO_OVERFLOW   0x20
++#define FSL_ATA_INTR_CTRL_IDLE       0x10
++#define FSL_ATA_INTR_ATA_INTRQ2      0x08
++
++/*
++ * timing registers
++ */
++
++#define FSL_ATA_TIME_OFF        IO_ADDRESS((ATA_BASE_ADDR + 0x00))
++#define FSL_ATA_TIME_ON         IO_ADDRESS((ATA_BASE_ADDR + 0x01))
++#define FSL_ATA_TIME_1          IO_ADDRESS((ATA_BASE_ADDR + 0x02))
++#define FSL_ATA_TIME_2w         IO_ADDRESS((ATA_BASE_ADDR + 0x03))
++
++#define FSL_ATA_TIME_2r         IO_ADDRESS((ATA_BASE_ADDR + 0x04))
++#define FSL_ATA_TIME_AX         IO_ADDRESS((ATA_BASE_ADDR + 0x05))
++#define FSL_ATA_TIME_PIO_RDX    IO_ADDRESS((ATA_BASE_ADDR + 0x06))
++#define FSL_ATA_TIME_4          IO_ADDRESS((ATA_BASE_ADDR + 0x07))
++
++#define FSL_ATA_TIME_9          IO_ADDRESS((ATA_BASE_ADDR + 0x08))
++#define FSL_ATA_TIME_M          IO_ADDRESS((ATA_BASE_ADDR + 0x09))
++#define FSL_ATA_TIME_JN         IO_ADDRESS((ATA_BASE_ADDR + 0x0A))
++#define FSL_ATA_TIME_D          IO_ADDRESS((ATA_BASE_ADDR + 0x0B))
++
++#define FSL_ATA_TIME_K          IO_ADDRESS((ATA_BASE_ADDR + 0x0C))
++#define FSL_ATA_TIME_ACK        IO_ADDRESS((ATA_BASE_ADDR + 0x0D))
++#define FSL_ATA_TIME_ENV        IO_ADDRESS((ATA_BASE_ADDR + 0x0E))
++#define FSL_ATA_TIME_RPX        IO_ADDRESS((ATA_BASE_ADDR + 0x0F))
++
++#define FSL_ATA_TIME_ZAH        IO_ADDRESS((ATA_BASE_ADDR + 0x10))
++#define FSL_ATA_TIME_MLIX       IO_ADDRESS((ATA_BASE_ADDR + 0x11))
++#define FSL_ATA_TIME_DVH        IO_ADDRESS((ATA_BASE_ADDR + 0x12))
++#define FSL_ATA_TIME_DZFS       IO_ADDRESS((ATA_BASE_ADDR + 0x13))
++
++#define FSL_ATA_TIME_DVS        IO_ADDRESS((ATA_BASE_ADDR + 0x14))
++#define FSL_ATA_TIME_CVH        IO_ADDRESS((ATA_BASE_ADDR + 0x15))
++#define FSL_ATA_TIME_SS         IO_ADDRESS((ATA_BASE_ADDR + 0x16))
++#define FSL_ATA_TIME_CYC        IO_ADDRESS((ATA_BASE_ADDR + 0x17))
++
++/*
++ * other facts
++ */
++#define FSL_ATA_DMA_WATERMARK		32	/* XXX fixme */
++#if (FSL_ATA_DMA_WATERMARK<=32)
++#define	FSL_ATA_DMA_MEM_XFER_SIZE	4
++#else
++#define	FSL_ATA_DMA_MEM_XFER_SIZE	32
++#endif
++
++#define MPC512X_DMA_ATA_RX		27	/* XXX fixme */
++#define MPC512X_DMA_ATA_TX		28	/* XXX fixme */
++
++#define FSL_DMA_DONE			0	/* XXX fixme */
++#define FSL_DMA_REQUEST_TIMEOUT		1	/* XXX fixme */
++#define FSL_DMA_TRANSFER_ERROR		2	/* XXX fixme */
++
++#define FSL_DMA_MODE_READ		0	/* XXX fixme */
++#define FSL_DMA_MODE_WRITE		1	/* XXX fixme */
++
++#define FSL_ATA_DMA_BD_SIZE_MAX 0xFC00	/* max size of scatterlist segment */
++
++/*! Private data for the drive structure. */
++struct fsl_ata_priv {
++	struct device *dev;	/*!< The device */
++	int dma_read_chan;	/*!< DMA channel sdma api gave us for reads */
++	int dma_write_chan;	/*!< DMA channel sdma api gave us for writes */
++	int ultra;		/*!< Remember when we're in ultra mode */
++	int dma_stat;		/*!< the state of DMA request */
++	u8 enable;		/*!< Current hardware interrupt mask */
++	void *ata_regs;		/*!< Base of ata registers */
++	dma_addr_t dma_addr;	/* physical address for dma rd/wr */
++
++	int ata_irq;		/*!< ATA irq number */
++
++	struct fsl_dma_requestbuf
++	 dma_reqbufs[MAX_TCD_NUM_PER_CH];
++	 
++	struct clk *ata_clk;	/*!< rate/pm clk */
++	struct ide_host *host;	
++	unsigned int iswrite;
++	spinlock_t lock;
++	/*struct device hw_dev;*/
++};
++
++/*! ATA transfer mode for set_ata_bus_timing() */
++enum ata_mode {
++	PIO,			/*!< Specifies PIO mode */
++	MDMA,			/*!< Specifies MDMA mode */
++	UDMA			/*!< Specifies UDMA mode */
++};
++
++#define	INTRQ_MCU 0		/* Enable ATA_INTRQ on the CPU */
++#define INTRQ_DMA 1		/* Enable ATA_INTRQ on the DMA engine */
++
++/*!
++ *  This structure defines the bits in the ATA TIME_CONFIGx
++ */
++union fsl_ata_time_cfg {
++	unsigned long config;
++	struct {
++		unsigned char field4;
++		unsigned char field3;
++		unsigned char field2;
++		unsigned char field1;
++	} bytes;
++};
++
++/*!defines the macro for accessing the register */
++#define ATA_RAW_WRITE(v, addr)	writel(v, addr)
++#define ATA_RAW_READ(addr)	readl(addr)
++/*! Get the configuration of TIME_CONFIG0 */
++#define GET_TIME_CFG(t, base) ((t)->config = ATA_RAW_READ(base))
++
++/*! Set the configuration of TIME_CONFIG0.
++ * And mask is ignored. base is the start address of this configuration.
++ */
++#define SET_TIME_CFG(t, mask, base) (ATA_RAW_WRITE((t)->config, base))
++#endif /* !_FSL_ATA_H_ */
+diff -Naur linux-2.6.29/drivers/input/evdev.c linux-2.6.29-v2010041601/drivers/input/evdev.c
+--- linux-2.6.29/drivers/input/evdev.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/input/evdev.c	2010-04-13 20:23:26.000000000 +0200
+@@ -792,10 +792,24 @@
+ 	int minor;
+ 	int error;
+ 
++	
+ 	for (minor = 0; minor < EVDEV_MINORS; minor++)
++	{
++		if(!minor)
++		{
++			if(test_bit(EV_ABS,dev->evbit)&&test_bit(ABS_PRESSURE,dev->absbit))
++			{
++				break;
++			}
++			else
++			{
++				continue;
++			}
++		}
++			
+ 		if (!evdev_table[minor])
+ 			break;
+-
++	}
+ 	if (minor == EVDEV_MINORS) {
+ 		printk(KERN_ERR "evdev: no more free evdev devices\n");
+ 		return -ENFILE;
+diff -Naur linux-2.6.29/drivers/input/keyboard/Kconfig linux-2.6.29-v2010041601/drivers/input/keyboard/Kconfig
+--- linux-2.6.29/drivers/input/keyboard/Kconfig	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/input/keyboard/Kconfig	2010-04-13 20:23:26.000000000 +0200
+@@ -277,6 +277,12 @@
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called pxa930_rotary.
+ 
++config KEYBOARD_PIEBOX
++	tristate "piebox  keyboard"	
++	default n
++	help
++	  Say Y here to enable the keyboard on piebox board.
++	  
+ config KEYBOARD_AAED2000
+ 	tristate "AAED-2000 keyboard"
+ 	depends on MACH_AAED2000
+diff -Naur linux-2.6.29/drivers/input/keyboard/Makefile linux-2.6.29-v2010041601/drivers/input/keyboard/Makefile
+--- linux-2.6.29/drivers/input/keyboard/Makefile	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/input/keyboard/Makefile	2010-04-13 20:23:26.000000000 +0200
+@@ -28,3 +28,4 @@
+ obj-$(CONFIG_KEYBOARD_MAPLE)		+= maple_keyb.o
+ obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
+ obj-$(CONFIG_KEYBOARD_SH_KEYSC)		+= sh_keysc.o
++obj-$(CONFIG_KEYBOARD_PIEBOX)		+=piebox-keyboard.o
+\ Kein Zeilenumbruch am Dateiende.
+diff -Naur linux-2.6.29/drivers/input/keyboard/piebox-keyboard.c linux-2.6.29-v2010041601/drivers/input/keyboard/piebox-keyboard.c
+--- linux-2.6.29/drivers/input/keyboard/piebox-keyboard.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/input/keyboard/piebox-keyboard.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,329 @@
++/*******************************
++*********************************/
++#include <linux/module.h>
++
++#include <linux/init.h>
++#include <linux/fs.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/sched.h>
++#include <linux/pm.h>
++#include <linux/sysctl.h>
++#include <linux/proc_fs.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/input.h>
++#include <asm/mpc5121_struct.h>
++
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++
++#define	DRV_NAME	"piebox-keyboard"
++struct mpc5121_gpio_struct  *get_mpc5121_gpio(void);
++
++enum{
++	GPIO_INTERRUPT_ANY_CHANGED=0,
++	GPIO_INTERRUPT_LOW_TO_HIGHT,
++	GPIO_INTERRUPT_HIGHT_TO_LOW,
++	GPIO_INTERRUPT_PULSE2
++	
++};
++#define	GPIO_INTERRUPT_MASK	3
++static  unsigned char  gpio_number[]={GPIO_KEY_VOL,GPIO_KEY_MENU,GPIO_KEY_LCD,GPIO_SYSTEM_START_NORFLASH};
++#define	PIE_BOX_KEY_NUMBES	sizeof(gpio_number)/sizeof(gpio_number[0])
++
++#define	PIE_BOX_KEY_MASK		(GPIO_BIT_OFFSET(GPIO_KEY_VOL)|GPIO_BIT_OFFSET(GPIO_KEY_MENU)|GPIO_BIT_OFFSET(GPIO_KEY_LCD)|GPIO_BIT_OFFSET(GPIO_SYSTEM_START_NORFLASH))
++
++
++/*
++struct mpc5121_gpio_struct{
++	u32	gpdir;
++	u32	gpodr;
++	u32	gpdat;
++	u32	gpier;
++	u32	gpier;
++	u32	gpimr;
++	u32	gpicr1;
++	u32	gpicr2;
++};
++*/
++struct piebox_keyboard_struct{	
++	unsigned char 	*gpio_number;	
++	char name[128];
++	char phys[64];
++	struct input_dev *dev;
++	struct mpc5121_gpio_struct *gpio;
++	u32	irq;
++	u32	keymap[32];
++	u32	keystatus;
++	struct timer_list	keydetect_timer;
++	
++};
++
++static irqreturn_t piebox_keyboard_int_server(int irq, void *dev_id)
++{
++
++	struct piebox_keyboard_struct *keyboard=dev_id;
++	u32	iostatus,index,flags=0,ievent,ievent_dsable;
++	iostatus=keyboard->gpio->gpdat;
++	ievent=keyboard->gpio->gpier;
++	ievent_dsable=0;
++	/*printk("%s() line:%d keystatus=0x%08x\n",__FUNCTION__,__LINE__,iostatus);*/
++	for(index=0;index<PIE_BOX_KEY_NUMBES;index++)
++	{
++		if(ievent&GPIO_BIT_OFFSET(keyboard->gpio_number[index]))
++		{
++			flags=1;
++			break;
++		}
++	}
++	if(!flags)
++	{
++		return IRQ_NONE;
++	}
++	for(index=0;index<PIE_BOX_KEY_NUMBES;index++)
++	{	
++		ievent_dsable|=GPIO_BIT_OFFSET(keyboard->gpio_number[index]);
++	}
++	keyboard->gpio->gpier=ievent_dsable;	
++	mod_timer(&keyboard->keydetect_timer, jiffies + HZ/20);
++	return IRQ_HANDLED;
++}
++static int piebox_keybaord_map_init(struct piebox_keyboard_struct *piebox_keyboard)
++{
++	int i;
++	if(PIE_BOX_KEY_NUMBES>4)
++	{
++		printk(KERN_ERR"too many keys unmaped\n");
++		return -1;
++	}
++	piebox_keyboard->keymap[GPIO_KEY_MENU]=KEY_F3;/* home */
++	piebox_keyboard->keymap[GPIO_KEY_LCD]=KEY_F4;/* backlight */
++	piebox_keyboard->keymap[GPIO_KEY_VOL]=KEY_F5;/* vol */
++	piebox_keyboard->keymap[GPIO_SYSTEM_START_NORFLASH]=KEY_F6;/* recovery */
++	for(i=0;i<32;i++)
++	{
++		if(piebox_keyboard->keymap[i])
++		{
++			set_bit(piebox_keyboard->keymap[i], piebox_keyboard->dev->keybit);
++		}
++	}
++	return 0;
++}
++static void piebox_keyboard_int_config_enable(struct piebox_keyboard_struct *piebox_keyboard)
++{
++	struct mpc5121_gpio_struct *gpio=piebox_keyboard->gpio;
++	unsigned char 	*gpios=piebox_keyboard->gpio_number;
++	int index,number,icr1,icr2,imask;
++	
++	icr1=gpio->gpicr1;
++	icr2=gpio->gpicr2;
++	imask=gpio->gpimr;
++	
++	for(index=0;index<PIE_BOX_KEY_NUMBES;index++)
++	{
++		number=gpios[index];
++		if(number<16)
++		{
++			icr1&=~(GPIO_INTERRUPT_MASK<<(30-number*2));
++			 icr1|=(GPIO_INTERRUPT_HIGHT_TO_LOW<<(30-number*2));
++		}
++		else
++		{
++			icr2&=~(GPIO_INTERRUPT_MASK<<(30-(number-16)*2));
++			icr2|=(GPIO_INTERRUPT_HIGHT_TO_LOW<<(30-(number-16)*2));
++		}
++		imask|=GPIO_BIT_OFFSET(number);		
++	}
++	gpio->gpicr1=icr1;
++	gpio->gpicr2=icr2;
++	gpio->gpimr=imask;
++
++	
++	
++}
++static void key_detect_timer(unsigned long data)
++{
++	struct piebox_keyboard_struct *keyboard= (struct esdhc_host *)data;	
++	u32	iostatus,index;
++	iostatus=keyboard->gpio->gpdat;	
++	iostatus&=PIE_BOX_KEY_MASK;
++	/*printk("iostatus:%08x\n",iostatus);*/
++	if(iostatus!=keyboard->keystatus)
++	{
++		for(index=0;index<PIE_BOX_KEY_NUMBES;index++)
++		{
++		
++			if(iostatus&GPIO_BIT_OFFSET(keyboard->gpio_number[index]))
++			{
++				input_report_key(keyboard->dev, keyboard->keymap[keyboard->gpio_number[index]],   0x00);
++			}
++			else
++			{
++				input_report_key(keyboard->dev, keyboard->keymap[keyboard->gpio_number[index]],   0x01);
++			
++			}	
++		
++		}
++		input_sync(keyboard->dev);
++		keyboard->keystatus=iostatus;
++	}
++	if((PIE_BOX_KEY_MASK&iostatus)!=PIE_BOX_KEY_MASK)
++		mod_timer(&keyboard->keydetect_timer, jiffies + HZ/10);
++	
++}
++static int piebox_keyboard_probe(struct of_device *op, const struct of_device_id *match)
++{
++	/*struct platform_device *pdev = to_platform_device(dev);*/
++	
++	
++	int err=-1;
++	
++	struct piebox_keyboard_struct *piebox_keyboard;
++	struct input_dev *inputdev;
++
++	piebox_keyboard=kzalloc(sizeof(struct piebox_keyboard_struct), GFP_KERNEL);
++	if(!piebox_keyboard)
++	{
++		printk(KERN_ERR"alloc memory failed.\n");
++		return -ENOMEM;
++	}
++
++	piebox_keyboard->irq=irq_of_parse_and_map(op->node, 0);
++	if(NO_IRQ==piebox_keyboard->irq)
++	{
++		printk(KERN_ERR"no irq.\n");
++		return -ENOMEM;
++	}
++	printk("piebox-keyboard irq:%d\n",piebox_keyboard->irq);
++
++	piebox_keyboard->gpio=get_mpc5121_gpio();/*ioremap(GENERAL_GPIO_BASE+MPC5121_CFG_IMMR,sizeof(struct mpc5121_gpio_struct));*/
++	if(!piebox_keyboard->gpio)
++	{
++		printk(KERN_ERR"Unmaped gpio memory.\n");
++		return -1;
++	}
++	
++	strcpy(piebox_keyboard->name,"piebox-keyboard");
++	strcpy(piebox_keyboard->phys,"keyboard/input0");
++
++
++
++	piebox_keyboard->dev=input_allocate_device();
++	
++	if(!piebox_keyboard->dev)
++	{
++		printk(KERN_ERR"alloc memory failed.\n");
++		err= -ENOMEM;
++		goto failed1;
++	}
++	piebox_keyboard->gpio_number=gpio_number;
++	
++	inputdev=piebox_keyboard->dev;
++	inputdev->name=piebox_keyboard->name;
++	inputdev->phys=piebox_keyboard->phys;
++	inputdev->dev.parent = &op->dev;
++	inputdev->evbit[0] =BIT_MASK(EV_KEY) | BIT_MASK(EV_REL);
++	set_bit(EV_MSC, inputdev->evbit);
++	set_bit(MSC_SCAN, inputdev->mscbit);
++	inputdev->id.bustype=BUS_HOST;
++	inputdev->id.vendor=0x001;
++	inputdev->id.product=0x002;
++	inputdev->id.version=0x0100;
++	input_set_drvdata(inputdev, piebox_keyboard);
++	if(piebox_keybaord_map_init(piebox_keyboard))
++	{
++		err= -1;
++		printk(KERN_ERR"keymap failed.\n");
++		goto failed2;
++	}	
++
++	err = input_register_device(inputdev);
++	if (err)
++	{
++			printk(KERN_ERR"input register failed.\n");
++			goto failed2;
++	}	
++	
++	
++	err = request_irq(piebox_keyboard->irq, piebox_keyboard_int_server,
++			  IRQF_SHARED|IRQF_DISABLED,
++			 "piebox-keybaord", piebox_keyboard);
++		if(err)
++		{
++			printk(KERN_ERR"Request irq:%d failed.\n",piebox_keyboard->irq);
++			goto failed3;
++		}
++	init_timer(&piebox_keyboard->keydetect_timer);
++	piebox_keyboard->keydetect_timer.data = (unsigned long)piebox_keyboard;
++	piebox_keyboard->keydetect_timer.function =key_detect_timer;
++	piebox_keyboard->keydetect_timer.expires = jiffies + HZ/20;
++	add_timer(&piebox_keyboard->keydetect_timer);	
++	dev_set_drvdata(&op->dev, (void *)piebox_keyboard);
++	piebox_keyboard_int_config_enable(piebox_keyboard);
++	return 0;
++failed3:	
++failed2:
++	input_free_device(piebox_keyboard->dev);
++ failed1:
++ 	iounmap(piebox_keyboard->gpio);
++ 	kfree(piebox_keyboard);
++ 	return err;
++}
++
++static int piebox_keyboard_remove(struct of_device *op)
++{
++	
++	struct piebox_keyboard_struct *piebox_keyboard = dev_get_drvdata(&op->dev);
++	
++	free_irq(piebox_keyboard->irq,piebox_keyboard);
++	del_timer(&piebox_keyboard->keydetect_timer);
++	input_free_device(piebox_keyboard->dev);
++	/*iounmap(piebox_keyboard->gpio);*/
++	kfree(piebox_keyboard);
++	return 0;
++}
++
++
++static struct of_device_id mpc512x_keybaord_of_match[] = {
++	{	 .compatible = "piebox-keyboard",	 },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mpc512x_keybaord_of_match);
++
++static struct of_platform_driver piebox_keyboard_of_platform_driver = {
++	.owner = THIS_MODULE,
++	.name =DRV_NAME ,
++	.match_table = mpc512x_keybaord_of_match,
++	.probe = piebox_keyboard_probe,
++	.remove = piebox_keyboard_remove,
++	.driver = {		   
++	.name = DRV_NAME,
++	.owner = THIS_MODULE,
++	},
++};
++
++static int __init piebox_keyboard_init(void)
++{
++	 return of_register_platform_driver(&piebox_keyboard_of_platform_driver);
++}
++
++static void __exit piebox_keybaord_exit(void)
++{
++	of_unregister_platform_driver(&piebox_keyboard_of_platform_driver);
++}
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("piebox keyboard driver");
++
++module_init(piebox_keyboard_init);
++module_exit(piebox_keybaord_exit);
++
++
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Cloudy chen<chen_yunsong@mtcera.com>");
++MODULE_DESCRIPTION("Keyboard driver for CPU GPIOs");
++MODULE_ALIAS("platform:gpio-keys");
++
+diff -Naur linux-2.6.29/drivers/input/touchscreen/chacha_mt4.c linux-2.6.29-v2010041601/drivers/input/touchscreen/chacha_mt4.c
+--- linux-2.6.29/drivers/input/touchscreen/chacha_mt4.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/input/touchscreen/chacha_mt4.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,348 @@
++/*
++ * drivers/input/touchscreen/chacha_mt4.c
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/hrtimer.h>
++#include <linux/slab.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/i2c.h>
++#include <linux/i2c/chacha_mt4.h>
++#include <linux/delay.h>
++
++#define REG_LENGTH 11
++
++__u8 mt4_data[REG_LENGTH];
++
++// buffer map
++#define REG_TOUCH_STATUS 	0x0
++#define REG_X1_LOW 		0x1
++#define REG_X1_HIGH 		0x2
++#define REG_Y1_LOW 		0x3
++#define REG_Y1_HIGH 		0x4
++#define REG_X2_LOW		0x5
++#define REG_X2_HIGH 		0x6
++#define REG_Y2_LOW 		0x7
++#define REG_Y2_HIGH 		0x8
++#define REG_STRENGTH_LOW 	0x9
++#define REG_STRENGTH_HIGH	0xa
++#define REG_RESERVE_1		0xb
++#define REG_FIRMWARE_ID		0xc
++#define REG_X_SENSITIVITY 	0xd
++#define REG_Y_SENSITIVITY 	0xe
++#define REG_RESERVE_2		0xf
++#define REG_RESERVE_3		0x10
++#define REG_RESERVE_4		0x11
++#define REG_RESERVE_5		0x12
++#define REG_OFFSET 		0x13
++#define REG_POWER_MODE 		0x14
++#define REG_EEPROM_WRITE 	0x15
++
++enum chacha_mt4_mode {
++	watch_mode = 0,
++	watch_mode_e = 0x0e,
++	active_mode = 0x10,
++	fast_scan_mode = 0x20,
++	freeze_mode = 0x90
++};
++
++struct mt4 {
++	struct input_dev	*input;
++	char			phys[32];
++	struct i2c_client	*client;
++
++	spinlock_t		lock;
++
++	u16			model;
++
++	unsigned		pendown;
++	int			irq;
++
++	int			(*get_pendown_state)(void);
++	void			(*clear_penirq)(void);
++	int			(*if_penirq)(void);
++	void			(*enable_irq)(int);
++
++	struct delayed_work work;
++};
++
++#define EVENT_PENDOWN 1
++#define EVENT_REPEAT  2
++#define EVENT_PENUP   3
++
++static void chacha_mt4_ts_poscheck(struct work_struct *work)
++{
++	int event, fingers, x1, y1, x2, y2;
++	struct mt4 *ts = container_of(work, struct mt4, work.work);
++	struct i2c_adapter *adapter = to_i2c_adapter(ts->client->dev.parent);
++
++	struct i2c_msg msg = {
++		.addr = ts->client->addr,
++		.flags = I2C_M_RD,
++		.buf = mt4_data,
++		.len = sizeof(mt4_data)
++	};
++
++	memset(&mt4_data, 0, sizeof(mt4_data));
++
++	if (i2c_transfer(adapter, &msg, 1) != 1) {
++		dev_err(&ts->client->dev, "Unable to transfer i2c request.\n");
++		goto out;
++	}
++
++	fingers = mt4_data[REG_TOUCH_STATUS] & 0x03;
++	if (fingers == 3)
++		fingers--;
++
++	x1 = mt4_data[REG_X1_LOW] | mt4_data[REG_X1_HIGH] << 8;
++	y1 = mt4_data[REG_Y1_LOW] | mt4_data[REG_Y1_HIGH] << 8;
++	x2 = mt4_data[REG_X2_LOW] | mt4_data[REG_X2_HIGH] << 8;
++	y2 = mt4_data[REG_Y2_LOW] | mt4_data[REG_Y2_HIGH] << 8;
++
++	event = (fingers == 0) ? EVENT_PENUP : EVENT_PENDOWN;
++
++#if 0
++	printk("mode: %02d, ", (mt4_data[REG_TOUCH_STATUS] & 0x30) >> 4);
++
++	if (fingers == 0)
++		printk("%s ", "PENUP");
++	if (fingers > 0)
++		printk("%04d,%04d ", x1, y1);
++	if (fingers >= 2)
++		printk("%04d,%04d ", x2, y2);
++	printk("\n");
++#endif
++
++	if (event == EVENT_PENDOWN) {
++//		input_report_key(ts->input, BTN_TOOL_FINGER, fingers == 1);
++//		input_report_key(ts->input, BTN_TOOL_DOUBLETAP, fingers == 2);
++//		input_report_key(ts->input, BTN_TOOL_TRIPLETAP, fingers > 2);
++
++		input_report_key(ts->input, BTN_TOUCH, fingers > 0);
++		input_report_abs(ts->input, ABS_X, x1);
++		input_report_abs(ts->input, ABS_Y, y1);
++		input_report_abs(ts->input, ABS_PRESSURE, 1);
++
++		if (fingers == 2) {
++			input_report_abs(ts->input, ABS_X, x2);
++			input_report_abs(ts->input, ABS_Y, y2);
++		}
++
++		input_sync(ts->input);
++
++	} else if (event == EVENT_PENUP) {
++		input_report_key(ts->input, BTN_TOUCH, 0);
++		input_report_abs(ts->input, ABS_PRESSURE, 0);
++		input_sync(ts->input);
++	}
++ out:
++	ts->enable_irq(1);
++}
++
++static irqreturn_t chacha_mt4_irq(int irq, void *handle)
++{
++	struct mt4 *ts = handle;
++
++	if (ts->if_penirq && !ts->if_penirq())
++		return IRQ_NONE;
++
++	/* the touch screen controller chip is hooked up to the cpu
++	 * using i2c and a single interrupt line. the interrupt line
++	 * is pulled low whenever someone taps the screen. to deassert
++	 * the interrupt line we need to acknowledge the interrupt by
++	 * communicating with the controller over the slow i2c bus.
++	 *
++	 * we can't acknowledge from interrupt context since the i2c
++	 * bus controller may sleep, so we just disable the interrupt
++	 * here and handle the acknowledge using delayed work.
++	 */
++
++	if (ts->enable_irq)
++		ts->enable_irq(0);
++	if (ts->clear_penirq)
++		ts->clear_penirq();
++
++	schedule_delayed_work(&ts->work, 0);
++
++	return IRQ_HANDLED;
++}
++
++static int chacha_mt4_calibration(struct mt4 *ts)
++{
++	struct i2c_adapter *adapter = to_i2c_adapter(ts->client->dev.parent);
++
++	u8 cmd[]= {0x14, 0x40, 0xf3};
++
++	struct i2c_msg msg = {
++		.addr = ts->client->addr,
++		.flags = 0,
++		.buf = cmd,
++		.len = sizeof(cmd)
++	};
++
++	if (i2c_transfer(adapter, &msg, 1) != 1) {
++		dev_err(&ts->client->dev, "Unable to transfer i2c request.\n");
++		return -EIO;
++	}
++
++	return 0;
++}
++
++#define MODE_SELECT_BYTE 0x14
++
++static inline int chacha_mt4_mode_select(struct mt4 *tsc, enum chacha_mt4_mode mode)
++{
++	return i2c_smbus_write_byte_data(tsc->client, MODE_SELECT_BYTE, (u8)mode);
++}
++
++static int chacha_mt4_ts_open(struct input_dev *dev)
++{
++	return 0;
++}
++
++static void chacha_mt4_ts_close(struct input_dev *dev)
++{
++}
++
++extern struct chacha_mt4_platform_data ts_chacha_mt4_data;
++
++static int chacha_mt4_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct input_dev *input_dev;
++	struct mt4 *ts;
++	int err;
++
++	if (!i2c_check_functionality(client->adapter,
++				     I2C_FUNC_SMBUS_READ_WORD_DATA))
++		return -EIO;
++
++	client->dev.platform_data = &ts_chacha_mt4_data;
++
++	ts = kzalloc(sizeof(struct mt4), GFP_KERNEL);
++	input_dev = input_allocate_device();
++	if (!ts || !input_dev) {
++		err = -ENOMEM;
++		goto err_free_mem;
++	}
++
++	i2c_set_clientdata(client, ts);
++
++	ts->client 			= client;
++	ts->input			= input_dev;
++	ts->get_pendown_state 	= ts_chacha_mt4_data.get_pendown_state;
++	ts->clear_penirq      	= ts_chacha_mt4_data.clear_penirq;
++	ts->if_penirq	   	= ts_chacha_mt4_data.if_penirq;
++	ts->enable_irq	   	= ts_chacha_mt4_data.enable_irq;
++	ts->irq 			= client->irq;
++	INIT_DELAYED_WORK(&ts->work, chacha_mt4_ts_poscheck);
++
++	snprintf(ts->phys, sizeof(ts->phys), "%s/input0",
++		dev_name(&client->dev));
++
++	input_dev->name = "TOPSTD ChaCha M-T4 Touchscreen";
++	input_dev->phys = ts->phys;
++	input_dev->id.bustype = BUS_I2C;
++	input_dev->open = chacha_mt4_ts_open;
++	input_dev->close = chacha_mt4_ts_close;
++
++	input_dev->evbit[0] = BIT(EV_SYN) | BIT(EV_KEY) | BIT(EV_ABS);
++	input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
++
++	set_bit(EV_ABS, input_dev->evbit);
++	set_bit(ABS_X, input_dev->absbit);
++	set_bit(ABS_Y, input_dev->absbit);
++	set_bit(ABS_PRESSURE, input_dev->absbit);
++
++	input_set_abs_params(input_dev, ABS_X, 0, 10240, 0, 0);
++	input_set_abs_params(input_dev, ABS_Y, 0, 5632, 0, 0);
++	input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0, 0);
++
++#if 1
++	ts_chacha_mt4_data.gpio_attb(0);
++	udelay(30);
++	chacha_mt4_calibration(ts);
++	msleep_interruptible(500);
++	udelay(50);
++	chacha_mt4_mode_select(ts, fast_scan_mode);
++	ts_chacha_mt4_data.gpio_attb(1);
++#endif
++
++	ts_chacha_mt4_data.init_platform_hw();
++
++	err = request_irq(ts->irq, chacha_mt4_irq, IRQF_SHARED,
++			client->dev.driver->name, ts);
++	if (err < 0) {
++		dev_err(&client->dev, "Unable to request touchscreen IRQ.\n");
++		goto err_free_mem;
++	}
++
++	err = input_register_device(input_dev);
++	if (err)
++		goto err_free_irq;
++
++	dev_info(&client->dev, "registered with irq (%d)\n", ts->irq);
++	return 0;
++
++ err_free_irq:
++	free_irq(ts->irq, ts);
++ err_free_mem:
++	input_free_device(input_dev);
++	kfree(ts);
++
++	return err;
++}
++
++static int chacha_mt4_remove(struct i2c_client *client)
++{
++	struct mt4	*ts = i2c_get_clientdata(client);
++	struct chacha_mt4_platform_data *pdata;
++
++	pdata = client->dev.platform_data;
++	pdata->exit_platform_hw();
++
++	free_irq(ts->irq, ts);
++	input_unregister_device(ts->input);
++	kfree(ts);
++
++	return 0;
++}
++
++static struct i2c_device_id chacha_mt4_idtable[] = {
++	{ "chacha_mt4", 0 },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(i2c, chacha_mt4_idtable);
++
++static struct i2c_driver mt4_driver = {
++	.driver = {
++		.owner	= THIS_MODULE,
++		.name	= "chacha_mt4"
++	},
++	.id_table	= chacha_mt4_idtable,
++	.probe		= chacha_mt4_probe,
++	.remove	= chacha_mt4_remove,
++};
++
++static int __init chacha_mt4_init(void)
++{
++	return i2c_add_driver(&mt4_driver);
++}
++
++static void __exit chacha_mt4_exit(void)
++{
++	i2c_del_driver(&mt4_driver);
++}
++
++module_init(chacha_mt4_init);
++module_exit(chacha_mt4_exit);
++
++MODULE_AUTHOR("Wang Yang <wang_yang@mtcera.com>");
++MODULE_DESCRIPTION("ChaCha M-T4 TouchScreen Driver");
++MODULE_LICENSE("GPL");
+diff -Naur linux-2.6.29/drivers/input/touchscreen/Kconfig linux-2.6.29-v2010041601/drivers/input/touchscreen/Kconfig
+--- linux-2.6.29/drivers/input/touchscreen/Kconfig	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/input/touchscreen/Kconfig	2010-04-13 20:23:26.000000000 +0200
+@@ -408,4 +408,25 @@
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called tsc2007.
+ 
++config TOUCHSCREEN_CHACHA_MT4
++	tristate "ChaCha M-T4 based touchscreens"
++	depends on I2C
++	help
++	  Say Y here if you have a ChaCha M-T4 based touchscreen.
++
++	  If unsure, say N.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called ChaCha-M-T4.
++
++config TOUCHSCREEN_MA17P0X
++	tristate "MA17P0X touchscreens"
++	depends on I2C
++	help
++	  Say Y here if you have a MA17P0X touchscreen.
++
++	  If unsure, say N.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called MA17P0X.
+ endif
+diff -Naur linux-2.6.29/drivers/input/touchscreen/ma17p0x.c linux-2.6.29-v2010041601/drivers/input/touchscreen/ma17p0x.c
+--- linux-2.6.29/drivers/input/touchscreen/ma17p0x.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/input/touchscreen/ma17p0x.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,332 @@
++/*
++ * drivers/input/touchscreen/ma17p0x.c
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/hrtimer.h>
++#include <linux/slab.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/i2c.h>
++#include <linux/i2c/ma17p0x.h>
++#include <linux/delay.h>
++
++__u8 ma17p0x[19];
++
++// buffer map
++#define REG_TOTAL_DATA_LEN 	0x0
++#define REG_RESERVED_0		0x1
++#define REG_NUM_OF_FINGER	0x2
++#define REG_X1_HIGH_BYTE		0x3
++#define REG_X1_LOW_BYTE		0x4
++#define REG_Y1_HIGH_BYTE		0x5
++#define REG_Y1_LOW_BYTE		0x6
++#define REG_X2_HIGH_BYTE		0x7
++#define REG_X2_LOW_BYTE		0x8
++#define REG_Y2_HIGH_BYTE		0x9
++#define REG_Y2_LOW_BYTE		0xa
++#define REG_X3_HIGH_BYTE		0xb
++#define REG_X3_LOW_BYTE		0xc
++#define REG_Y3_HIGH_BYTE		0xd
++#define REG_Y3_LOW_BYTE		0xe
++#define REG_X4_HIGH_BYTE		0xf
++#define REG_X4_LOW_BYTE		0x10
++#define REG_Y4_HIGH_BYTE		0x11
++#define REG_Y4_LOW_BYTE		0x12
++
++enum ma17p0x_mode {
++	watch_mode = 0,
++	watch_mode_e = 0x0e,
++	active_mode = 0x10,
++	fast_scan_mode = 0x20,
++	freeze_mode = 0x90
++};
++
++struct mt4 {
++	struct input_dev	*input;
++	char			phys[32];
++	struct i2c_client	*client;
++
++	spinlock_t		lock;
++
++	u16			model;
++
++	unsigned		pendown;
++	int			irq;
++
++	int			(*get_pendown_state)(void);
++	void			(*clear_penirq)(void);
++	int			(*if_penirq)(void);
++	void			(*enable_irq)(int);
++
++	struct delayed_work work;
++};
++
++struct ts_point {
++	int x;
++	int y;
++};
++
++#define EVENT_PENDOWN 1
++#define EVENT_REPEAT  2
++#define EVENT_PENUP   3
++
++#define get_val(_high, _low) (_high << 4 | _low >> 4)
++
++static void ma17p0x_ts_poscheck(struct work_struct *work)
++{
++	struct mt4 *ts = container_of(work, struct mt4, work.work);
++	struct i2c_adapter *adapter = to_i2c_adapter(ts->client->dev.parent);
++	struct ts_point pt[4];
++	int i, fingers = 0;
++	u8 data_length;
++	int event = EVENT_PENUP;
++
++	struct i2c_msg msg[] = {
++		{
++			.addr = ts->client->addr,
++			.flags = I2C_M_RD,
++			.buf = &data_length,
++			.len = 1
++		},
++		{
++			.addr = ts->client->addr,
++			.flags = I2C_M_RD,
++			.buf = ma17p0x,
++			.len = sizeof(ma17p0x)
++		}
++	};
++
++	if ((i2c_transfer(adapter, &msg[0], 1) != 1)) {
++		if (ts->get_pendown_state() == 0)
++			goto pen_up;
++		goto out;
++	}
++
++	msg[1].len = data_length + 1;
++	if (i2c_transfer(adapter, &msg[1], 1) != 1) {
++		if (ts->get_pendown_state() == 0)
++			goto pen_up;
++		goto out;
++	}
++
++	fingers = ma17p0x[REG_NUM_OF_FINGER];
++	if (fingers <= 0 || fingers > 4)
++		goto out;
++
++	event = EVENT_PENDOWN;
++	for (i = 0; i < fingers; i++) {
++		pt[i].x = get_val(ma17p0x[REG_X1_HIGH_BYTE + 4 * i],
++				ma17p0x[REG_X1_LOW_BYTE + 4 * i]);
++		pt[i].y = get_val(ma17p0x[REG_Y1_HIGH_BYTE + 4 * i],
++				ma17p0x[REG_Y1_LOW_BYTE + 4 * i]);
++	}
++
++pen_up:
++
++#if 0
++	if (event == EVENT_PENUP)
++		printk("%s\n", "PENUP");
++	if (event == EVENT_PENDOWN) {
++		for (i = 0; i < fingers; i++)
++			printk("%04d,%04d ", pt[i].x, pt[i].y);
++		printk("\n");
++	}
++#endif
++
++	if (event == EVENT_PENDOWN) {
++
++		input_report_key(ts->input, BTN_TOUCH, 1);
++
++		for (i = 0; i < fingers; i++) {
++			input_report_abs(ts->input, ABS_X, pt[i].x);
++			input_report_abs(ts->input, ABS_Y, pt[i].y);
++		}
++
++		input_report_abs(ts->input, ABS_PRESSURE, 1);
++		input_sync(ts->input);
++
++	} else if (event == EVENT_PENUP) {
++		input_report_key(ts->input, BTN_TOUCH, 0);
++		input_report_abs(ts->input, ABS_PRESSURE, 0);
++		input_sync(ts->input);
++	}
++out:
++	ts->enable_irq(1);
++}
++
++static irqreturn_t ma17p0x_irq(int irq, void *handle)
++{
++	struct mt4 *ts = handle;
++
++	if (ts->if_penirq && !ts->if_penirq())
++		return IRQ_NONE;
++
++	/* the touch screen controller chip is hooked up to the cpu
++	 * using i2c and a single interrupt line. the interrupt line
++	 * is pulled low whenever someone taps the screen. to deassert
++	 * the interrupt line we need to acknowledge the interrupt by
++	 * communicating with the controller over the slow i2c bus.
++	 *
++	 * we can't acknowledge from interrupt context since the i2c
++	 * bus controller may sleep, so we just disable the interrupt
++	 * here and handle the acknowledge using delayed work.
++	 */
++
++	if (ts->enable_irq)
++		ts->enable_irq(0);
++	if (ts->clear_penirq)
++		ts->clear_penirq();
++
++	schedule_delayed_work(&ts->work, 0);
++
++	return IRQ_HANDLED;
++}
++
++#define MODE_SELECT_BYTE 0x14
++
++static inline int ma17p0x_mode_select(struct mt4 *tsc, enum ma17p0x_mode mode)
++{
++	return i2c_smbus_write_byte_data(tsc->client, MODE_SELECT_BYTE, (u8)mode);
++}
++
++static int ma17p0x_ts_open(struct input_dev *dev)
++{
++	return 0;
++}
++
++static void ma17p0x_ts_close(struct input_dev *dev)
++{
++}
++
++extern struct ma17p0x_platform_data ts_ma17p0x_data;
++
++static int ma17p0x_probe(struct i2c_client *client,
++			const struct i2c_device_id *id)
++{
++	struct input_dev *input_dev;
++	struct mt4 *ts;
++	int err;
++
++	if (!i2c_check_functionality(client->adapter,
++				     I2C_FUNC_SMBUS_READ_WORD_DATA))
++		return -EIO;
++
++	client->dev.platform_data = &ts_ma17p0x_data;
++
++	ts = kzalloc(sizeof(struct mt4), GFP_KERNEL);
++	input_dev = input_allocate_device();
++	if (!ts || !input_dev) {
++		err = -ENOMEM;
++		goto err_free_mem;
++	}
++
++	i2c_set_clientdata(client, ts);
++
++	ts->client 			= client;
++	ts->input			= input_dev;
++	ts->get_pendown_state 	= ts_ma17p0x_data.get_pendown_state;
++	ts->clear_penirq      	= ts_ma17p0x_data.clear_penirq;
++	ts->if_penirq	   	= ts_ma17p0x_data.if_penirq;
++	ts->enable_irq	   	= ts_ma17p0x_data.enable_irq;
++	ts->irq 			= client->irq;
++	INIT_DELAYED_WORK(&ts->work, ma17p0x_ts_poscheck);
++
++	snprintf(ts->phys, sizeof(ts->phys), "%s/input0",
++		dev_name(&client->dev));
++
++	input_dev->name = "MA17P0X Touchscreen";
++	input_dev->phys = ts->phys;
++	input_dev->id.bustype = BUS_I2C;
++	input_dev->open = ma17p0x_ts_open;
++	input_dev->close = ma17p0x_ts_close;
++
++	input_dev->evbit[0] = BIT(EV_SYN) | BIT(EV_KEY) | BIT(EV_ABS);
++	input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
++
++	set_bit(EV_ABS, input_dev->evbit);
++	set_bit(ABS_X, input_dev->absbit);
++	set_bit(ABS_Y, input_dev->absbit);
++	set_bit(ABS_PRESSURE, input_dev->absbit);
++
++	input_set_abs_params(input_dev, ABS_X, 0, 4096, 0, 0);
++	input_set_abs_params(input_dev, ABS_Y, 0, 4096, 0, 0);
++	input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0, 0);
++
++	ts_ma17p0x_data.init_platform_hw();
++
++	err = request_irq(ts->irq, ma17p0x_irq, IRQF_SHARED,
++			client->dev.driver->name, ts);
++	if (err < 0) {
++		dev_err(&client->dev, "Unable to request touchscreen IRQ.\n");
++		goto err_free_mem;
++	}
++
++	err = input_register_device(input_dev);
++	if (err)
++		goto err_free_irq;
++
++	dev_info(&client->dev, "registered with irq (%d)\n", ts->irq);
++	return 0;
++
++ err_free_irq:
++	free_irq(ts->irq, ts);
++ err_free_mem:
++	input_free_device(input_dev);
++	kfree(ts);
++
++	return err;
++}
++
++static int ma17p0x_remove(struct i2c_client *client)
++{
++	struct mt4	*ts = i2c_get_clientdata(client);
++	struct ma17p0x_platform_data *pdata;
++
++	pdata = client->dev.platform_data;
++	pdata->exit_platform_hw();
++
++	free_irq(ts->irq, ts);
++	input_unregister_device(ts->input);
++	kfree(ts);
++
++	return 0;
++}
++
++static struct i2c_device_id ma17p0x_idtable[] = {
++	{ "ma17p0x", 0 },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(i2c, ma17p0x_idtable);
++
++static struct i2c_driver ma17p0x_driver = {
++	.driver = {
++		.owner	= THIS_MODULE,
++		.name	= "ma17p0x"
++	},
++	.id_table	= ma17p0x_idtable,
++	.probe		= ma17p0x_probe,
++	.remove	= ma17p0x_remove,
++};
++
++static int __init ma17p0x_init(void)
++{
++	return i2c_add_driver(&ma17p0x_driver);
++}
++
++static void __exit ma17p0x_exit(void)
++{
++	i2c_del_driver(&ma17p0x_driver);
++}
++
++module_init(ma17p0x_init);
++module_exit(ma17p0x_exit);
++
++MODULE_AUTHOR("Wang Yang <wang_yang@mtcera.com>");
++MODULE_DESCRIPTION("MA17P0X TouchScreen Driver");
++MODULE_LICENSE("GPL");
+diff -Naur linux-2.6.29/drivers/input/touchscreen/Makefile linux-2.6.29-v2010041601/drivers/input/touchscreen/Makefile
+--- linux-2.6.29/drivers/input/touchscreen/Makefile	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/input/touchscreen/Makefile	2010-04-13 20:23:26.000000000 +0200
+@@ -26,6 +26,8 @@
+ obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT)	+= touchright.o
+ obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN)	+= touchwin.o
+ obj-$(CONFIG_TOUCHSCREEN_TSC2007)	+= tsc2007.o
++obj-$(CONFIG_TOUCHSCREEN_CHACHA_MT4)	+= chacha_mt4.o
++obj-$(CONFIG_TOUCHSCREEN_MA17P0X)	+= ma17p0x.o
+ obj-$(CONFIG_TOUCHSCREEN_UCB1400)	+= ucb1400_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_WACOM_W8001)	+= wacom_w8001.o
+ obj-$(CONFIG_TOUCHSCREEN_WM97XX)	+= wm97xx-ts.o
+diff -Naur linux-2.6.29/drivers/input/touchscreen/wm97xx-core.c linux-2.6.29-v2010041601/drivers/input/touchscreen/wm97xx-core.c
+--- linux-2.6.29/drivers/input/touchscreen/wm97xx-core.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/input/touchscreen/wm97xx-core.c	2010-04-13 20:23:26.000000000 +0200
+@@ -69,7 +69,7 @@
+  * Documentation/input/input-programming.txt for more details.
+  */
+ 
+-static int abs_x[3] = {350, 3900, 5};
++static int abs_x[3] = {350, 3900, 15};
+ module_param_array(abs_x, int, NULL, 0);
+ MODULE_PARM_DESC(abs_x, "Touchscreen absolute X min, max, fuzz");
+ 
+diff -Naur linux-2.6.29/drivers/mmc/host/Kconfig linux-2.6.29-v2010041601/drivers/mmc/host/Kconfig
+--- linux-2.6.29/drivers/mmc/host/Kconfig	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/mmc/host/Kconfig	2010-04-13 20:23:26.000000000 +0200
+@@ -65,6 +65,31 @@
+ 
+ 	  If unsure, say Y.
+ 
++config MMC_MPC5121
++	tristate "Freescale MPC5121 Secure Digital Host Controller Interface support"
++	depends on PPC_MPC512x
++	default n
++	help
++	  This selects the SD Host Controller Interface on the MPC5121.
++	  If you have a MPC5121 Platform with SD slot, say Y or M here.
++
++config MMC_MPC5121_USE_DMA
++	bool "Use DMA in MPC5121 SDHC driver" if MMC_MPC5121
++	default y
++	help
++	  This enables DMA in the MPC5121 SD Host Controller driver.
++
++	  If unsure, say Y.
++
++config MMC_MPC5121_USE_CARD_INSERTION_INT
++	bool "Use card insertion interrupt in MPC5121 SDHC driver" if MMC_MPC5121
++	default n
++	help
++	  This enables use of card insertion interrupt in the MPC5121 SD Host Controller driver.
++	  This option will not work on ADS5121.
++
++	  If unsure, say N.
++
+ config MMC_OMAP
+ 	tristate "TI OMAP Multimedia Card Interface support"
+ 	depends on ARCH_OMAP
+diff -Naur linux-2.6.29/drivers/mmc/host/Makefile linux-2.6.29-v2010041601/drivers/mmc/host/Makefile
+--- linux-2.6.29/drivers/mmc/host/Makefile	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/mmc/host/Makefile	2010-04-13 20:23:26.000000000 +0200
+@@ -27,4 +27,4 @@
+ obj-$(CONFIG_MMC_S3C)   	+= s3cmci.o
+ obj-$(CONFIG_MMC_SDRICOH_CS)	+= sdricoh_cs.o
+ obj-$(CONFIG_MMC_TMIO)		+= tmio_mmc.o
+-
++obj-$(CONFIG_MMC_MPC5121)	+= mpc5121_sdhc.o
+diff -Naur linux-2.6.29/drivers/mmc/host/mpc5121_sdhc.c linux-2.6.29-v2010041601/drivers/mmc/host/mpc5121_sdhc.c
+--- linux-2.6.29/drivers/mmc/host/mpc5121_sdhc.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/mmc/host/mpc5121_sdhc.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,1301 @@
++/*
++ * drivers/mmc/host/mpc5121_sdhc.c
++ *
++ * Copyright (C) 2008 Freescale Semicondutor, Inc. All rights reserved.
++ *
++ * Author: <allgosystems.com>
++ *
++ * derived from sdhci.c by Pierre Ossman
++ *
++ * Description:
++ * Freescale MPC5121 Secure Digital Host Controller driver.
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/ioport.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/highmem.h>
++#include <linux/dma-mapping.h>
++#include <linux/scatterlist.h>
++#include <linux/uaccess.h>
++#include <linux/irq.h>
++#include <linux/hardirq.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/sd.h>
++#include <linux/mmc/host.h>
++#include <linux/module.h>
++#include <asm/io.h>
++#include <linux/ioport.h>
++#include <linux/time.h>
++
++#include <asm/of_platform.h>
++#include <asm/dma.h>
++#include <asm/page.h>
++#include <asm/reg.h>
++#include <sysdev/fsl_soc.h>
++
++#include "mpc5121_sdhc.h"
++#include <asm/fsldma.h>
++#include <linux/wait.h>
++#include <linux/sched.h>
++
++#include <asm-powerpc/fsldma.h>
++
++#define DATA_SKEW_RATE_STD_4 0x00000003
++
++#define DRIVER_NAME "sdhc"
++
++#define MPC512X_DMA_SDHC	30
++#define RSP_TYPE(x)	((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
++
++#ifdef DEBUG
++#define DBG(fmt, args...)	printk(KERN_DEBUG "[%s]  " fmt "\n", \
++			__FUNCTION__, ## args)
++#else
++#define DBG(fmt, args...)	do {} while (0)
++#endif
++
++#define J1_SDHC_CLK 0X00000080
++#define K5_SDHC_CMD 0X00000080
++#define J2_SDHC_D0 0X00000080
++#define J3_SDHC_D1_IRQ 0X00000080
++#define J4_SDHC_D2 0X00000080
++#define H2_SDHC_D3_CD 0X00000080
++#define CLK_LINE 0X0C4
++#define CMD_LINE 0X0C8
++#define D0_LINE 0X0CC
++#define D1_LINE 0X0D0
++#define D2_LINE 0X0D4
++#define D3_CD_LINE 0X0D8
++
++
++#define PU_ENABLE 0x00000018
++#define PD_ENABLE 0x00000008
++#define DATA_SKEW_RATE_STD_4 0x00000003
++#define PU_ENABLE_PULL_DOWN 0x00000008
++
++static u32 *write_buf;
++static dma_addr_t sphyaddr;
++static void  dma_correction(unsigned long *, unsigned long *, int len);
++
++#ifdef CONFIG_MMC_DEBUG
++static void dump_cmd(struct mmc_command *cmd)
++{
++	printk(KERN_INFO "%s: CMD: opcode: %d ", DRIVER_NAME, cmd->opcode);
++	printk(KERN_INFO "arg: 0x%08x ", cmd->arg);
++	printk(KERN_INFO "flags: 0x%08x\n", cmd->flags);
++}
++
++static void dump_status(const char *func, int sts)
++{
++	unsigned int bitset;
++	printk(KERN_INFO "%s:status: ", func);
++	while (sts) {
++		/* Find the next bit set */
++		bitset = sts & ~(sts - 1);
++		switch (bitset) {
++		case STATUS_CARD_INSERTION:
++			printk(KERN_INFO "CARD_INSERTION|");
++			break;
++		case STATUS_CARD_REMOVAL:
++			printk(KERN_INFO "CARD_REMOVAL |");
++			break;
++		case STATUS_YBUF_EMPTY:
++			printk(KERN_INFO "YBUF_EMPTY |");
++			break;
++		case STATUS_XBUF_EMPTY:
++			printk(KERN_INFO "XBUF_EMPTY |");
++			break;
++		case STATUS_YBUF_FULL:
++			printk(KERN_INFO "YBUF_FULL |");
++			break;
++		case STATUS_XBUF_FULL:
++			printk(KERN_INFO "XBUF_FULL |");
++			break;
++		case STATUS_BUF_UND_RUN:
++			printk(KERN_INFO "BUF_UND_RUN |");
++			break;
++		case STATUS_BUF_OVFL:
++			printk(KERN_INFO "BUF_OVFL |");
++			break;
++		case STATUS_READ_OP_DONE:
++			printk(KERN_INFO "READ_OP_DONE |");
++			break;
++		case STATUS_WR_CRC_ERROR_CODE_MASK:
++			printk(KERN_INFO "WR_CRC_ERROR_CODE |");
++			break;
++		case STATUS_READ_CRC_ERR:
++			printk(KERN_INFO "READ_CRC_ERR |");
++			break;
++		case STATUS_WRITE_CRC_ERR:
++			printk(KERN_INFO "WRITE_CRC_ERR |");
++			break;
++		case STATUS_SDIO_INT_ACTIVE:
++			printk(KERN_INFO "SDIO_INT_ACTIVE |");
++			break;
++		case STATUS_END_CMD_RESP:
++			printk(KERN_INFO "END_CMD_RESP |");
++			break;
++		case STATUS_WRITE_OP_DONE:
++			printk(KERN_INFO "WRITE_OP_DONE |");
++			break;
++		case STATUS_CARD_BUS_CLK_RUN:
++			printk(KERN_INFO "CARD_BUS_CLK_RUN |");
++			break;
++		case STATUS_BUF_READ_RDY:
++			printk(KERN_INFO "BUF_READ_RDY |");
++			break;
++		case STATUS_BUF_WRITE_RDY:
++			printk(KERN_INFO "BUF_WRITE_RDY |");
++			break;
++		case STATUS_RESP_CRC_ERR:
++			printk(KERN_INFO "RESP_CRC_ERR |");
++			break;
++		case STATUS_TIME_OUT_RESP:
++			printk(KERN_INFO "TIME_OUT_RESP |");
++			break;
++		case STATUS_TIME_OUT_READ:
++			printk(KERN_INFO "TIME_OUT_READ |");
++			break;
++		default:
++			printk(KERN_INFO "Invalid Status Register value0x%x\n",
++			bitset);
++			break;
++		}
++		sts &= ~bitset;
++	}
++	printk(KERN_INFO "\n");
++}
++static void sdhc_dumpregs(struct sdhc_host *host)
++{
++	printk(KERN_DEBUG DRIVER_NAME ": ========= REGISTER DUMP ==========\n");
++	printk(KERN_DEBUG DRIVER_NAME ": Clock Control Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_STR_STP_CLK));
++	printk(KERN_DEBUG DRIVER_NAME ": Status Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_STATUS));
++	printk(KERN_DEBUG DRIVER_NAME ": Clock Rate Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_CLK_RATE));
++	printk(KERN_DEBUG DRIVER_NAME
++			": Command and data Control Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_CMD_DAT_CONT));
++	printk(KERN_DEBUG DRIVER_NAME
++			": Response and Timeout Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_RES_TO));
++	printk(KERN_DEBUG DRIVER_NAME ": Read Timeout Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_READ_TO));
++	printk(KERN_DEBUG DRIVER_NAME ": Block Length Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_BLK_LEN));
++	printk(KERN_DEBUG DRIVER_NAME ": Number of Blocks Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_NOB));
++	printk(KERN_DEBUG DRIVER_NAME ": Revision Number Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_REV_NO));
++	printk(KERN_DEBUG DRIVER_NAME ": Interrupt Control Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_INT_CNTR));
++	printk(KERN_DEBUG DRIVER_NAME ": Command Number Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_CMD));
++	printk(KERN_DEBUG DRIVER_NAME ": Command Argument Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_ARG));
++	printk(KERN_DEBUG DRIVER_NAME ": Command Response Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_RES_FIFO));
++	printk(KERN_DEBUG DRIVER_NAME
++			": Data Buffer Access Register : 0x%08x\n",
++		fsl_readl(host->ioaddr + MMC_BUFFER_ACCESS));
++}
++#endif
++
++
++static int sdhc_data_done(struct sdhc_host *host, unsigned int stat);
++
++static void fsl_writel(u32 val, unsigned __iomem *addr)
++{
++	out_be32(addr, val);
++}
++
++static inline u32 fsl_readl(unsigned __iomem *addr)
++{
++	return in_be32(addr);
++}
++static void mpc5121_sdhc_io_pullup_d3_cd(void)
++{
++	struct device_node *np;
++	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ioctl");
++	if (np) {
++		void __iomem *ioctl = of_iomap(np, 0);
++		fsl_writel(H2_SDHC_D3_CD | DATA_SKEW_RATE_STD_4 | PU_ENABLE,
++				ioctl + D3_CD_LINE);
++		iounmap(ioctl);
++	}
++}
++
++
++static void mpc5121_sdhc_io_pulldown_d3_cd(void)
++{
++	struct device_node *np;
++	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ioctl");
++	if (np) {
++		void __iomem *ioctl = of_iomap(np, 0);
++		fsl_writel(H2_SDHC_D3_CD | DATA_SKEW_RATE_STD_4 | PD_ENABLE,
++				ioctl + D3_CD_LINE);
++		iounmap(ioctl);
++	}
++}
++
++/*!
++ *This function resets the SDHC host.
++ *
++ * @param host  Pointer to MMC/SD  host structure
++ */
++static void sdhc_softreset(struct sdhc_host *host)
++{
++	/* reset sequence */
++
++	fsl_writel(0x8, host->ioaddr + MMC_STR_STP_CLK);
++	fsl_writel(0x9, host->ioaddr + MMC_STR_STP_CLK);
++	fsl_writel(0x1, host->ioaddr + MMC_STR_STP_CLK);
++	fsl_writel(0x1, host->ioaddr + MMC_STR_STP_CLK);
++	fsl_writel(0x1, host->ioaddr + MMC_STR_STP_CLK);
++	fsl_writel(0x1, host->ioaddr + MMC_STR_STP_CLK);
++	fsl_writel(0x1, host->ioaddr + MMC_STR_STP_CLK);
++	fsl_writel(0x1, host->ioaddr + MMC_STR_STP_CLK);
++	fsl_writel(0x1, host->ioaddr + MMC_STR_STP_CLK);
++	fsl_writel(0x1, host->ioaddr + MMC_STR_STP_CLK);
++	fsl_writel(0x3f, host->ioaddr + MMC_CLK_RATE);
++
++	fsl_writel(0xff, host->ioaddr + MMC_RES_TO);
++	fsl_writel(512, host->ioaddr + MMC_BLK_LEN);
++	fsl_writel(1, host->ioaddr + MMC_NOB);
++#ifndef CONFIG_MMC_MPC5121_USE_CARD_INSERTION_INT
++	mpc5121_sdhc_io_pullup_d3_cd();
++#endif
++
++}
++#ifdef CONFIG_MMC_MPC5121_USE_DMA
++/*!
++ * After DMA completion during read operation this gets called in the DMA isr.
++ * @param host pointer to host data structure
++ */
++static int dma_read_over(struct sdhc_host *host)
++{
++		unsigned int status = 0;
++	struct mmc_data *data = host->data;
++
++	status = fsl_readl(host->ioaddr + MMC_STATUS);
++	if (status & STATUS_TIME_OUT_READ) {
++		pr_debug("%s: Read time out occurred\n", DRIVER_NAME);
++		data->error = -ETIMEDOUT;
++		fsl_writel(STATUS_TIME_OUT_READ,
++				host->ioaddr + MMC_STATUS);
++	} else if (status & STATUS_READ_CRC_ERR) {
++		pr_debug("%s: Read CRC error occurred\n", DRIVER_NAME);
++		data->error = -EILSEQ;
++		fsl_writel(STATUS_READ_CRC_ERR,
++				host->ioaddr + MMC_STATUS);
++	}
++	fsl_writel(STATUS_READ_OP_DONE, host->ioaddr + MMC_STATUS);
++
++	sdhc_data_done(host, status);
++	return 1 ;
++
++}
++
++/*!
++ * After DMA completion during write operation this gets called in the DMA isr.
++ * @param host pointer to host data structure
++ */
++static int dma_write_over(struct sdhc_host *host)
++{
++	unsigned int count, status = 0;
++	struct mmc_data *data = host->data;
++	count = 0;
++
++	while (!(fsl_readl(host->ioaddr + MMC_STATUS)
++		    & STATUS_WRITE_OP_DONE)) {
++		count++;
++		if (count > 100000) {
++			printk(KERN_ERR "%s: "
++				"failed to get WRITE_OP_DONE\n",
++				DRIVER_NAME);
++			break;
++		}
++	}
++
++		;
++
++	/* check for CRC errors */
++	status = fsl_readl(host->ioaddr + MMC_STATUS);
++	if (status & STATUS_WRITE_CRC_ERR) {
++		pr_debug("%s: Write CRC error occurred\n", DRIVER_NAME);
++
++		data->error = -EILSEQ;
++		fsl_writel(STATUS_WRITE_CRC_ERR,
++		host->ioaddr + MMC_STATUS);
++	}
++	fsl_writel(STATUS_WRITE_OP_DONE, host->ioaddr + MMC_STATUS);
++	/* complete the data transfer request */
++	sdhc_data_done(host, status);
++	return 1;
++}
++
++/*!
++ * DMA completion callback routine, this gets called in the DMA isr, when
++ * DMA is over the sleeping process is woken up.
++ * @param error_status error info of DMA transfer
++ */
++static  void fsl_dma_sdhc_callback(void *arg, int error_status)
++{
++	struct sdhc_host *host = (struct sdhc_host *)arg;
++	struct mmc_data *data = host->data;
++
++
++	unsigned long *buf;
++	buf = (unsigned long *)((u32)page_address((void *)data->sg->page_link)
++			+ (u32) data->sg->offset);
++
++	if (!error_status) {
++		if ((data->flags&MMC_DATA_READ)) {
++			dma_correction((unsigned long *)write_buf,
++				buf, host->dma_size);
++			dma_read_over(host);
++			return ;
++		} /* This is MMC_DATA_WRITE operation */
++		else {
++			dma_write_over(host);
++			return;
++		}
++	} else  /* There was an error during DMA operation */
++		printk(KERN_ERR "DMA error on SDHC channel\n");
++}
++
++
++/*!
++ * Allocate buffer memory for DMA transfer
++ * Request for DMA channel
++ * and initialize the wait queue
++ * @param host pointer to MMC/SD host structure
++ */
++static int fsl_sdhc_dma_init(struct sdhc_host *host)
++{
++	/*
++	 * Allocate and setup the DMA channels
++	 */
++	int dma_chan;
++	dma_chan = fsl_dma_chan_request(MPC512X_DMA_SDHC);
++	if (dma_chan < 0) {
++		printk(KERN_ERR "couldn't get SDHC  DMA channel\n");
++		host->dma_available = 0;
++		return -ENOMEM;
++	}
++	fsl_dma_callback_set(dma_chan, fsl_dma_sdhc_callback, host);
++
++	write_buf = dma_alloc_coherent(NULL, sizeof(u32) * 1024,
++			&sphyaddr, GFP_KERNEL);
++	if (!write_buf)
++		return -ENOMEM;
++	return 0;
++}
++
++/*!
++ * config information for DMA. The DMA transfer is between SDHC FIFO
++ * and the DMA coherent buffer initialized in the beginning.
++ * @param host pointer to MMC/SD host data structure
++ * @param data pointer to MMC Data structure
++ * @param MMC_OP operation - to or from SD FIFO
++ * @param len data transfer length
++ */
++static int fsl_dma_priv_config(struct sdhc_host *host, struct mmc_data *data,
++			int MMC_OP, int len)
++{
++	static struct fsl_dma_requestbuf	dma_priv;
++	/* DMA_FROM_DEVICE = read the card by host*/
++	if (MMC_OP == DMA_TO_DEVICE) {
++		dma_priv.src = (dma_addr_t)(sphyaddr);
++		dma_priv.soff = 4;
++		dma_priv.dest = (dma_addr_t)host->addr + MMC_BUFFER_ACCESS;
++		dma_priv.doff = 0;
++		dma_priv.minor_loop = 16;
++	} else {
++		dma_priv.src = (dma_addr_t) host->addr + MMC_BUFFER_ACCESS;
++		dma_priv.soff = 0;
++		dma_priv.dest = (dma_addr_t)(sphyaddr) ;
++		dma_priv.doff = 4;
++		dma_priv.minor_loop = 16;
++	}
++	host->dma = &dma_priv;
++	return 1;
++}
++
++/*!
++ * function to enable byte swap operation whenever data is written or
++ * read from FIFO so this fuction is called before DMA write and after
++ * DMA read operation.
++ * @params pointers to the two buffers
++ * @param len the length of data in bytes
++ */
++static void  dma_correction(unsigned long *buf, unsigned long *temp_buf,
++		int len)
++{
++	int i;
++	unsigned long temp_data;
++
++	for (i = 0; i < ((len+3)/4); i++) {
++		temp_data = *(buf+i);
++		temp_data = cpu_to_le32(temp_data);
++		*(temp_buf+i) = temp_data;
++	}
++}
++
++#endif
++
++/* Wait count to start the clock */
++#define CMD_WAIT_CNT 1000
++
++/*!
++ * This function sets the SDHC register to stop the clock and waits for the
++ * clock stop indication.
++ *
++ * @param host Pointer to MMC/SD host structure
++ * @param wait Boolean value to indicate whether to wait
++ * 	for the clock to start or come out instantly
++ */
++static void sdhc_stop_clock(struct sdhc_host *host, bool wait)
++{
++	int wait_cnt = 0;
++	while (1) {
++		fsl_writel(STR_STP_CLK_STOP_CLK,
++				host->ioaddr + MMC_STR_STP_CLK);
++
++
++		if (!wait)
++			break;
++
++		wait_cnt = CMD_WAIT_CNT;
++
++		while (wait_cnt--) {
++			if (!(fsl_readl(host->ioaddr + MMC_STATUS) &
++						STATUS_CARD_BUS_CLK_RUN))
++				break;
++		}
++		if (!(fsl_readl(host->ioaddr + MMC_STATUS) &
++					STATUS_CARD_BUS_CLK_RUN))
++			break;
++	}
++}
++
++/*!
++ * This function sets the SDHC register to start the clock and waits for the
++ * clock start indication. When the clock starts SDHC module starts processing
++ * the command in CMD Register with arguments in ARG Register.
++ *
++ * @param host Pointer to MMC/SD host structure
++ * @param wait Boolean value to indicate whether to wait for the
++ * 	clock to start or come out instantly
++ */
++static void sdhc_start_clock(struct sdhc_host *host, bool wait)
++{
++	int wait_cnt;
++	if (fsl_readl(host->ioaddr + MMC_STATUS) & STATUS_CARD_BUS_CLK_RUN)
++		return;
++
++	while (1) {
++		setbits32(host->ioaddr + MMC_STR_STP_CLK,
++				STR_STP_CLK_START_CLK);
++		if (!wait)
++			break;
++
++		wait_cnt = CMD_WAIT_CNT;
++		while (wait_cnt--) {
++			if (!(fsl_readl(host->ioaddr + MMC_STATUS) &
++				STATUS_CARD_BUS_CLK_RUN))
++				setbits32(host->ioaddr + MMC_STR_STP_CLK,
++						STR_STP_CLK_START_CLK);
++
++		}
++		if (fsl_readl(host->ioaddr + MMC_STATUS) &
++			STATUS_CARD_BUS_CLK_RUN)
++			break;
++	}
++}
++
++/*!
++ * This function is called to setup SDHC register for data transfer.
++ * The function allocates DMA buffers, configures the DMA channel.
++ * Start the DMA channel to transfer data. When DMA is not enabled this
++ * function set ups only Number of Block and Block Length registers.
++ *
++ * @param host  Pointer to MMC/SD host structure
++ * @param data  Pointer to MMC/SD data structure
++ */
++static void sdhc_setup_data(struct sdhc_host *host, struct mmc_data *data)
++{
++	unsigned int nob = data->blocks;
++
++	if (data->flags & MMC_DATA_STREAM)
++		nob = 0xffff;
++
++	host->data = data;
++
++	fsl_writel(nob, host->ioaddr + MMC_NOB);
++	fsl_writel(data->blksz, host->ioaddr + MMC_BLK_LEN);
++
++	host->dma_size = data->blocks * data->blksz;
++	pr_debug("%s:Request bytes to transfer:%d\n", DRIVER_NAME,
++		 host->dma_size);
++}
++
++/*!
++ * This function is called by \b fslmci_request() function to setup the SDHC
++ * register to issue command. This function disables the card insertion and
++ * removal detection interrupt.
++ *
++ * @param host  Pointer to MMC/SD host structure
++ * @param cmd   Pointer to MMC/SD command structure
++ * @param cmdat Value to store in Command and Data Control Register
++ */
++static void sdhc_start_cmd(struct sdhc_host *host, struct mmc_command *cmd,
++		unsigned int cmdat)
++{
++	WARN_ON(host->cmd != NULL);
++	fsl_writel(INT_CNTR_END_CMD_RES, host->ioaddr + MMC_INT_CNTR);
++
++	host->cmd = cmd;
++
++	switch (RSP_TYPE(mmc_resp_type(cmd))) {
++	case RSP_TYPE(MMC_RSP_R1):	/* r1, r1b, r6 */
++		cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
++		break;
++	case RSP_TYPE(MMC_RSP_R3):
++		cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
++		break;
++	case RSP_TYPE(MMC_RSP_R2):
++		cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
++		break;
++	default:
++		/* No Response required */
++		break;
++	}
++
++	if (cmd->opcode == MMC_GO_IDLE_STATE)
++		cmdat |= CMD_DAT_CONT_INIT;	/* This command needs init */
++
++	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
++		cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
++	fsl_writel(cmd->opcode, host->ioaddr + MMC_CMD);
++	fsl_writel(cmd->arg, host->ioaddr + MMC_ARG);
++
++	fsl_writel(cmdat, host->ioaddr + MMC_CMD_DAT_CONT);
++	sdhc_start_clock(host, true);
++}
++
++/*!
++ * This function is called to complete the command request.
++ * This function enables insertion or removal interrupt.
++ *
++ * @param host Pointer to MMC/SD host structure
++ * @param req  Pointer to MMC/SD command request structure
++ */
++static void sdhc_finish_request(struct sdhc_host *host,
++				struct mmc_request *req)
++{
++	u32 intr_enable;
++	host->mrq = NULL;
++	host->cmd = NULL;
++	host->data = NULL;
++
++
++	mmc_request_done(host->mmc, req);
++	intr_enable = (INT_CNTR_END_CMD_RES | INT_CNTR_CARD_INSERTION_EN
++	| INT_CNTR_CARD_REMOVAL_EN);
++	fsl_writel(intr_enable, host->ioaddr + MMC_INT_CNTR);
++}
++
++/*!
++ * This function is called when the requested command is completed.
++ * This function reads the response from the card and data if the command
++ * is for data transfer. This function checks for CRC error in response FIFO or
++ * data FIFO.
++ *
++ * @param host  Pointer to MMC/SD host structure
++ * @param stat  Content of SDHC Status Register
++ *
++ * @return This function returns 0 if there is no pending command, otherwise 1
++ * always.
++ */
++static int sdhc_cmd_done(struct sdhc_host *host, unsigned int stat)
++{
++	struct mmc_command *cmd = host->cmd;
++	struct mmc_data *data = host->data;
++	struct scatterlist *sg;
++	int i, count;
++	u32 a, b, c;
++	u32 temp_data;
++	unsigned int status = 0;
++	unsigned long *buf;
++	int no_of_bytes;
++	int no_of_words;
++	int num_buf = 1;
++
++	if (!cmd) {
++		/* There is no command for completion */
++		return 0;
++	}
++
++	/* As this function finishes the command, initialize cmd to NULL */
++	host->cmd = NULL;
++
++	/* check for Time out errors */
++	if (stat & STATUS_TIME_OUT_RESP) {
++		fsl_writel(STATUS_TIME_OUT_RESP, host->ioaddr + MMC_STATUS);
++		pr_debug("%s: CMD TIMEOUT\n", DRIVER_NAME);
++		cmd->error = -ETIMEDOUT;
++	} else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
++		fsl_writel(STATUS_RESP_CRC_ERR, host->ioaddr + MMC_STATUS);
++		cmd->error = -EILSEQ;
++	}
++
++	/* Read response from the card */
++	switch (RSP_TYPE(mmc_resp_type(cmd))) {
++	case RSP_TYPE(MMC_RSP_R1):	/* r1, r1b, r6 */
++		a = fsl_readl(host->ioaddr + MMC_RES_FIFO) & 0xffff;
++		b = fsl_readl(host->ioaddr + MMC_RES_FIFO) & 0xffff;
++		c = fsl_readl(host->ioaddr + MMC_RES_FIFO) & 0xffff;
++
++		cmd->resp[0] = a << 24 | b << 8 | c >> 8;
++		break;
++	case RSP_TYPE(MMC_RSP_R3):	/* r3, r4 */
++		a = fsl_readl(host->ioaddr + MMC_RES_FIFO) & 0xffff;
++		b = fsl_readl(host->ioaddr + MMC_RES_FIFO) & 0xffff;
++		c = fsl_readl(host->ioaddr + MMC_RES_FIFO) & 0xffff;
++		cmd->resp[0] = a << 24 | b << 8 | c >> 8;
++
++		break;
++	case RSP_TYPE(MMC_RSP_R2):
++		for (i = 0; i < 4; i++) {
++			a = fsl_readl(host->ioaddr + MMC_RES_FIFO) & 0xffff;
++			b = fsl_readl(host->ioaddr + MMC_RES_FIFO) & 0xffff;
++			cmd->resp[i] = a << 16 | b;
++
++		}
++		break;
++	default:
++		break;
++	}
++
++	pr_debug("%s: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", DRIVER_NAME,
++		 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
++
++	if (!host->data || cmd->error) {
++		/* complete the command */
++		sdhc_finish_request(host, host->mrq);
++#ifndef CONFIG_MMC_MPC5121_USE_CARD_INSERTION_INT
++		mmc_detect_change(host->mmc, msecs_to_jiffies(100));
++#endif
++		return 1;
++	}
++
++	/* The command has a data transfer */
++	no_of_bytes = data->blocks * data->blksz;
++	host->dma_size = no_of_bytes;
++	buf = (unsigned long *)((u32)page_address((void *)data->sg->page_link) +
++			(u32) data->sg->offset);
++	sg = data->sg ;
++
++	/* calculate the number of bytes requested for transfer */
++	no_of_words = (no_of_bytes + 3) / 4;
++	pr_debug("no_of_words=%d\n", no_of_words);
++
++
++#ifdef CONFIG_MMC_MPC5121_USE_DMA
++	if (host->dma_size < (16 << host->mmc->ios.bus_width))
++		goto pio;
++
++	if ((data->flags & MMC_DATA_READ)) {
++		fsl_dma_priv_config(host, data, DMA_FROM_DEVICE, no_of_bytes);
++		host->dma->len = no_of_bytes ;
++		fsl_dma_config(MPC512X_DMA_SDHC, (host->dma), num_buf);
++
++		fsl_dma_enable(MPC512X_DMA_SDHC);
++		return 1;
++	}
++	if (data->flags & MMC_DATA_WRITE) {
++		dma_correction(buf, (unsigned long *)write_buf, host->dma_size);
++		fsl_dma_priv_config(host, data, DMA_TO_DEVICE, no_of_bytes);
++		host->dma->len = no_of_bytes ;
++		fsl_dma_config(MPC512X_DMA_SDHC, (host->dma), num_buf);
++		fsl_dma_enable(MPC512X_DMA_SDHC);
++		return 1;
++	}
++pio:
++#endif
++	/* Use PIO tranfer of data */
++	if (data->flags & MMC_DATA_READ) {
++		for (i = 0; i < no_of_words; i++) {
++			/* wait for buffers to be ready for read */
++
++			count = 0;
++			while (!(fsl_readl(host->ioaddr + MMC_STATUS) &
++						(STATUS_BUF_READ_RDY |
++						 STATUS_READ_OP_DONE))) {
++			count++;
++				if (count > 100000) {
++					printk(KERN_ERR "%s: "
++						"failed to get READ_OP_DONE\n",
++						DRIVER_NAME);
++					break;
++				}
++			}
++
++				;
++
++			/* read 32 bit data */
++			temp_data = fsl_readl(host->ioaddr + MMC_BUFFER_ACCESS);
++			temp_data = cpu_to_le32(temp_data);
++			if (no_of_bytes >= 4) {
++				*buf++ = temp_data;
++				no_of_bytes -= 4;
++			}
++		}
++
++		count = 0;
++		/* wait for read operation completion bit */
++		while (!(fsl_readl(host->ioaddr + MMC_STATUS)
++					& STATUS_READ_OP_DONE)) {
++			count++;
++			if (count > 100000) {
++				printk(KERN_ERR "%s: "
++					"failed to get READ_OP_DONE\n",
++					DRIVER_NAME);
++				break;
++			}
++		}
++
++			;
++		/* check for time out and CRC errors */
++		status = fsl_readl(host->ioaddr + MMC_STATUS);
++		if (status & STATUS_TIME_OUT_READ) {
++			pr_debug("%s: Read time out occurred\n", DRIVER_NAME);
++			data->error = -ETIMEDOUT;
++			fsl_writel(STATUS_TIME_OUT_READ,
++			host->ioaddr + MMC_STATUS);
++		} else if (status & STATUS_READ_CRC_ERR) {
++			pr_debug("%s: Read CRC error occurred\n", DRIVER_NAME);
++			data->error = -EILSEQ;
++			fsl_writel(STATUS_READ_CRC_ERR,
++			host->ioaddr + MMC_STATUS);
++		}
++		fsl_writel(STATUS_READ_OP_DONE, host->ioaddr + MMC_STATUS);
++
++		pr_debug("%s: Read %u words\n", DRIVER_NAME, i);
++
++		sdhc_data_done(host, status);
++		return 1;
++	}
++	if (data->flags & MMC_DATA_WRITE) {
++		for (i = 0; i < no_of_words; i++) {
++
++			/* wait for buffers to be ready for write */
++			while (!(fsl_readl(host->ioaddr + MMC_STATUS) &
++						STATUS_BUF_WRITE_RDY)) ;
++
++			/* write 32 bit data */
++			/* ALLGO BUGFIX: MMC data is LE */
++			fsl_writel(cpu_to_le32(*buf++),
++					host->ioaddr + MMC_BUFFER_ACCESS);
++
++			if (fsl_readl(host->ioaddr + MMC_STATUS)
++					& STATUS_WRITE_OP_DONE)
++				break;
++		}
++
++		/* wait for write operation completion bit */
++		while (!(fsl_readl(host->ioaddr + MMC_STATUS) &
++					STATUS_WRITE_OP_DONE))
++			;
++
++		/* check for CRC errors */
++		status = fsl_readl(host->ioaddr + MMC_STATUS);
++		if (status & STATUS_WRITE_CRC_ERR) {
++			pr_debug("%s: Write CRC error occurred\n", DRIVER_NAME);
++
++			data->error = -EILSEQ;
++			fsl_writel(STATUS_WRITE_CRC_ERR,
++					host->ioaddr + MMC_STATUS);
++		}
++		fsl_writel(STATUS_WRITE_OP_DONE, host->ioaddr + MMC_STATUS);
++		pr_debug("%s: Written %u words\n", DRIVER_NAME, i);
++
++	}
++
++	/* complete the data transfer request */
++	sdhc_data_done(host, status);
++	return 1;
++}
++
++
++/*!
++ * This function is called when the data transfer is completed either by DMA
++ * or by core. This function is called to clean up the DMA buffer and to send
++ * STOP transmission command for commands to transfer data. This function
++ * completes request issued by the MMC/SD core driver.
++ *
++ * @param host   pointer to MMC/SD host structure.
++ * @param stat   content of SDHC Status Register
++ *
++ * @return This function returns 0 if no data transfer otherwise return 1
++ * always.
++ */
++static int sdhc_data_done(struct sdhc_host *host, unsigned int stat)
++{
++	struct mmc_data *data = host->data;
++
++	if (!data)
++		return 0;
++#ifdef CONFIG_MMC_MPC5121_USE_DMA
++	if (host->dma_size > (16 << host->mmc->ios.bus_width))
++	fsl_dma_disable(MPC512X_DMA_SDHC);
++
++#endif
++	if (fsl_readl(host->ioaddr + MMC_STATUS) & STATUS_ERR_MASK) {
++		pr_debug("%s: request failed. status: 0x%08x\n",
++			 DRIVER_NAME, fsl_readl(host->ioaddr + MMC_STATUS));
++	}
++
++	host->data = NULL;
++	data->bytes_xfered = host->dma_size;
++
++	if (host->mrq->stop && (data->error == 0)) {
++		sdhc_start_cmd(host, host->mrq->stop, 0);
++	} else {
++		sdhc_finish_request(host, host->mrq);
++	}
++
++	return 1;
++}
++
++
++static void sdhc_set_power(struct sdhc_host *host, unsigned short power)
++{
++
++	if (host->power == power)
++	return;
++
++	if (power == (unsigned short)-1)
++	host->power = power;
++}
++
++/*!
++ * This function is called by MMC/SD Bus Protocol driver to issue a MMC
++ * and SD commands to the SDHC.
++ *
++ * @param  mmc  Pointer to MMC/SD host structure
++ * @param  mrq  Pointer to MMC/SD command request structure
++ */
++static void sdhc_request(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++	struct sdhc_host *host = mmc_priv(mmc);
++	/* Holds the value of Command and Data Control Register */
++	unsigned long cmdat;
++
++	WARN_ON(host->mrq != NULL);
++
++	host->mrq = mrq;
++#ifdef CONFIG_MMC_DEBUG
++	dump_cmd(req->cmd);
++	dump_status(__FUNCTION__, __raw_readl(host->base + MMC_STATUS));
++#endif
++
++	cmdat = 0;
++	if (mrq->data) {
++	sdhc_setup_data(host, mrq->data);
++
++	cmdat |= CMD_DAT_CONT_DATA_ENABLE;
++
++	if (mrq->data->flags & MMC_DATA_WRITE)
++	cmdat |= CMD_DAT_CONT_WRITE;
++
++	if (mrq->data->flags & MMC_DATA_STREAM)
++	printk(KERN_ERR
++	"FSL MMC does not support stream mode\n");
++	}
++	sdhc_start_cmd(host, mrq->cmd, cmdat);
++}
++
++/*!
++ * This function is called by MMC/SD Bus Protocol driver to change the clock
++ * speed of MMC or SD card
++ *
++ * @param mmc Pointer to MMC/SD host structure
++ * @param ios Pointer to MMC/SD I/O type structure
++ */
++static void sdhc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
++{
++	struct sdhc_host *host = mmc_priv(mmc);
++	/*This variable holds the value of clock prescaler */
++	int prescaler;
++	int clk_rate = clk_get_rate(host->sdhc_clk);
++	if (ios->power_mode == MMC_POWER_OFF)
++	sdhc_set_power(host, -1);
++	else
++	sdhc_set_power(host, ios->vdd);
++
++	if (ios->clock) {
++		unsigned int clk_dev = 0;
++
++		if (ios->clock == mmc->f_min)
++			prescaler = 16;
++		else
++			prescaler = 0;
++
++		while (prescaler <= 0x800) {
++			for (clk_dev = 1; clk_dev <= 0xF; clk_dev++) {
++				int x;
++				if (prescaler != 0) {
++					x = (clk_rate / (clk_dev + 1)) /
++					 (prescaler * 2);
++				} else {
++					x = clk_rate / (clk_dev + 1);
++				}
++
++				pr_debug("x=%d, clock=%d %d\n", x, ios->clock,
++					 clk_dev);
++				if (x <= ios->clock)
++					break;
++			}
++			if (clk_dev < 0x10)
++				break;
++			if (prescaler == 0)
++				prescaler = 1;
++			else
++				prescaler <<= 1;
++		}
++
++		pr_debug("prescaler = 0x%x, divider = 0x%x\n", prescaler,
++			 clk_dev);
++		sdhc_stop_clock(host, true);
++
++		fsl_writel((prescaler << 4) | clk_dev,
++		host->ioaddr + MMC_CLK_RATE);
++		sdhc_start_clock(host, false);
++	} else {
++		sdhc_stop_clock(host, true);
++	}
++}
++
++/*!
++ * MMC/SD host operations structure.
++ * These functions are registered with MMC/SD Bus protocol driver.
++ */
++static const struct mmc_host_ops sdhc_ops = {
++	.request	= sdhc_request,
++	.set_ios	= sdhc_set_ios,
++};
++
++/*!
++ * Interrupt service routine registered to handle the SDHC interrupts.
++ * This interrupt routine handles end of command, card insertion and
++ * card removal interrupts. If the interrupt is card insertion or removal then
++ * inform the MMC/SD core driver to detect the change in physical connections.
++ * If the command is END_CMD_RESP read the Response FIFO.
++ *
++ * @param   irq    the interrupt number
++ * @param   devid  driver private data
++ * @param   regs   holds a snapshot of the processor's context before the
++ *                 processor entered the interrupt code
++ *
++ * @return  The function returns \b IRQ_RETVAL(1) if interrupt was handled,
++ *          returns \b IRQ_RETVAL(0) if the interrupt was not handled.
++ */
++static irqreturn_t sdhc_irq(int irq, void *dev_id)
++{
++	struct sdhc_host *host = dev_id;
++	irqreturn_t result = IRQ_HANDLED;
++	unsigned int status = 0;
++
++	status = fsl_readl(host->ioaddr + MMC_STATUS);
++	if (status & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)) {
++		if (status & STATUS_CARD_INSERTION)
++			fsl_writel(STATUS_CARD_INSERTION,
++					host->ioaddr + MMC_STATUS);
++		if (status & STATUS_CARD_REMOVAL)
++			fsl_writel(STATUS_CARD_REMOVAL,
++					host->ioaddr + MMC_STATUS);
++			mmc_detect_change(host->mmc, msecs_to_jiffies(100));
++
++	}
++
++	if (status & STATUS_END_CMD_RESP) {
++			setbits32(host->ioaddr + MMC_STATUS,
++					STATUS_END_CMD_RESP);
++		sdhc_cmd_done(host, status);
++
++	}
++	return result;
++}
++
++
++/*****************************************************************************\
++ *                                                                           *
++ * Device probing/removal                                                    *
++ *                                                                           *
++\*****************************************************************************/
++
++static void sdhc_remove_slot(struct of_device *ofdev, int slot)
++{
++	struct sdhc_chip *chip;
++	struct mmc_host *mmc;
++	struct sdhc_host *host;
++
++	chip = dev_get_drvdata(&(ofdev->dev));
++	host = chip->hosts[slot];
++	mmc = host->mmc;
++
++	chip->hosts[slot] = NULL;
++	mmc_remove_host(mmc);
++	sdhc_softreset(host);
++
++	free_irq(host->irq, host);
++
++	iounmap(host->ioaddr);
++
++	release_mem_region(host->addr, host->size);
++
++	mmc_free_host(mmc);
++}
++
++#if CONFIG_PPC_MPC5125
++#define SDHC1_IO_ADDR_BASE	(0x8000a000+0x6f)
++static sdhc_io_init(void)
++{
++	unsigned char *sdhc_io_reg;
++	unsigned int i=6;
++	sdhc_io_reg=ioremap(SDHC1_IO_ADDR_BASE, 0x6);
++	for(i=0;i<6;i++)
++	{
++		sdhc_io_reg[i]=0x1b;
++	}
++	iounmap(sdhc_io_reg);
++}
++#endif
++static int __devinit sdhc_probe_slot(struct of_device *ofdev, int slot)
++{
++	struct device_node *np = ofdev->node;
++	struct device_node *cpu;
++	int ret;
++	struct sdhc_chip *chip;
++	struct mmc_host *mmc;
++	struct sdhc_host *host;
++	struct resource res;
++	u32 intr_enable;
++
++	chip = dev_get_drvdata(&(ofdev->dev));
++	BUG_ON(!chip);
++
++	mmc = mmc_alloc_host(sizeof(struct sdhc_host), &(ofdev->dev));
++	if (!mmc)
++		return -ENOMEM;
++
++	host = mmc_priv(mmc);
++	host->mmc = mmc;
++
++	host->chip = chip;
++	chip->hosts[slot] = host;
++
++	ret = of_address_to_resource(np, 0, &res);
++	if (ret)
++		goto free;
++	host->addr = res.start;
++
++	host->size = res.end - res.start + 1;
++	host->irq = irq_of_parse_and_map(np, 0);
++	printk(KERN_DEBUG "slot %d at 0x%08lx, irq %d and size = %x\n",
++			slot, host->addr, host->irq, host->size);
++
++	snprintf(host->slot_descr, 20, "sdhc:slot%d", slot);
++
++	if (!request_mem_region(host->addr, host->size, DRIVER_NAME)) {
++		ret = -EBUSY;
++		goto release;
++	}
++#if CONFIG_PPC_MPC5125
++	sdhc_io_init();
++#endif
++	host->ioaddr = ioremap(host->addr, host->size);
++	if (!host->ioaddr) {
++		ret = -ENOMEM;
++		goto release;
++	}
++	host->sdhc_clk = clk_get(&ofdev->dev, "sdhc_clk");
++	clk_enable(host->sdhc_clk);
++	sdhc_softreset(host);
++#ifdef CONFIG_MMC_MPC5121_USE_DMA
++	fsl_sdhc_dma_init(host);
++#endif
++	fsl_writel(READ_TO_VALUE, host->ioaddr + MMC_READ_TO);
++	intr_enable = (INT_CNTR_END_CMD_RES | INT_CNTR_CARD_INSERTION_EN
++			| INT_CNTR_CARD_REMOVAL_EN);
++	fsl_writel(intr_enable, host->ioaddr + MMC_INT_CNTR);
++	cpu = of_find_node_by_type(NULL, "cpu");
++	if (cpu) {
++		unsigned int size;
++		const u32 *prop = of_get_property(cpu, "bus-frequency", &size);
++		host->max_clk = *prop;
++		of_node_put(cpu);
++	} else
++		host->max_clk = 396000000;
++	mmc->ops = &sdhc_ops;
++	mmc->f_min = 300000;
++	mmc->f_max = min((int)host->max_clk, 25000000);
++	mmc->caps = MMC_CAP_4_BIT_DATA;
++	mmc->ocr_avail = MMC_VDD_32_33 |
++			 MMC_VDD_33_34 |
++			 MMC_VDD_29_30 |
++			 MMC_VDD_30_31 |
++			 MMC_VDD_165_195;
++	spin_lock_init(&host->lock);
++	/*
++	 * Maximum number of segments. Hardware cannot do scatter lists.
++	 */
++
++#ifdef CONFIG_MMC_DEBUG
++	sdhc_dumpregs(host);
++#endif
++	ret = request_irq(host->irq, sdhc_irq, IRQF_SHARED,
++			host->slot_descr, host);
++	if (ret)
++		goto release;
++	mmiowb();
++	mmc_add_host(mmc);
++	printk(KERN_INFO "%s: SDHC at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
++			host->addr, host->irq,
++			(host->flags & SDHC_USE_DMA)?"DMA":"PIO");
++	return 0;
++release:
++	release_mem_region(host->addr, host->size);
++free:
++	mmc_remove_host(mmc);
++	return ret;
++}
++
++
++static int __devinit sdhc_probe(struct of_device *ofdev,
++	const struct of_device_id *match)
++{
++	int ret = 1, i;
++	u8 slots;
++	struct sdhc_chip *chip;
++	BUG_ON(ofdev == NULL);
++	BUG_ON(match == NULL);
++	slots = SDHC_SLOTS_NUMBER;
++	DBG("found %d slot(s)", slots);
++	if (slots == 0)
++		return -ENODEV;
++	chip = kmalloc(sizeof(struct sdhc_chip) +
++		sizeof(struct sdhc_host *) * slots, GFP_KERNEL);
++	if (!chip) {
++		ret = -ENOMEM;
++		goto err;
++	}
++	chip->ofdev = ofdev;
++	chip->num_slots = slots;
++	dev_set_drvdata(&(ofdev->dev), chip);
++	for (i = 0; i < slots; i++) {
++		ret = 0;
++		ret = sdhc_probe_slot(ofdev, i);
++		if (ret) {
++			for (i--; i >= 0; i--)
++				sdhc_remove_slot(ofdev, i);
++			goto free;
++		}
++	}
++	return 0;
++free:
++	dev_set_drvdata(&(ofdev->dev), NULL);
++	kfree(chip);
++err:
++	return ret;
++}
++
++static int __devexit sdhc_remove(struct of_device *ofdev)
++{
++	int i;
++	struct sdhc_chip *chip;
++	chip = dev_get_drvdata(&(ofdev->dev));
++	if (chip) {
++		for (i = 0; i < chip->num_slots; i++)
++			sdhc_remove_slot(ofdev, i);
++		dev_set_drvdata(&(ofdev->dev), NULL);
++		kfree(chip);
++		mpc5121_sdhc_io_pulldown_d3_cd();
++#ifdef CONFIG_MMC_MPC5121_USE_DMA
++		fsl_dma_free_chan(MPC512X_DMA_SDHC);
++		dma_free_coherent(NULL, sizeof(u32) * 1024, write_buf,
++								sphyaddr);
++#endif
++	}
++	return 0;
++}
++
++
++#define sdhc_suspend NULL
++#define sdhc_resume NULL
++
++/*-------------------------------------------------------------------------*/
++static struct of_device_id fsl_sdhc_match[] = {
++	{
++#if CONFIG_PPC_MPC5125
++		.compatible = "fsl,mpc5125-sdhc",
++#else
++		.compatible = "fsl,mpc5121-sdhc",
++#endif
++	},
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, fsl_sdhc_match);
++
++static struct of_platform_driver sdhc_driver = {
++	.owner = 	THIS_MODULE,
++	.name =		DRIVER_NAME,
++	.match_table =  fsl_sdhc_match,
++	.probe =	sdhc_probe,
++	.remove =	__devexit_p(sdhc_remove),
++	.suspend =	sdhc_suspend,
++	.resume =	sdhc_resume,
++};
++
++
++/*****************************************************************************\
++ *                                                                           *
++ * Driver init/exit                                                          *
++ *                                                                           *
++\*****************************************************************************/
++
++static int __init sdhc_drv_init(void)
++{
++	printk(KERN_INFO DRIVER_NAME
++		": Freescale Enhanced Secure Digital Host Controller driver\n");
++
++	return of_register_platform_driver(&sdhc_driver);
++}
++
++static void __exit sdhc_drv_exit(void)
++{
++	DBG("Exiting\n");
++	of_unregister_platform_driver(&sdhc_driver);
++}
++module_init(sdhc_drv_init);
++module_exit(sdhc_drv_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Enhanced Secure Digital Host Controller driver");
++MODULE_LICENSE("GPL");
+diff -Naur linux-2.6.29/drivers/mmc/host/mpc5121_sdhc.h linux-2.6.29-v2010041601/drivers/mmc/host/mpc5121_sdhc.h
+--- linux-2.6.29/drivers/mmc/host/mpc5121_sdhc.h	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/mmc/host/mpc5121_sdhc.h	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,164 @@
++/*
++ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef __MPC5121_SDHC_H__
++#define __MPC5121_SDHC_H__
++
++/*!
++ * @file mpc5121_sdhc.h
++ *
++ * @brief Driver for the Freescale Semiconductor SDHC module.
++ *
++ * This file defines offsets and bits of SDHC registers. SDHC is also
++ * referred as MMC/SD controller
++ *
++ * @ingroup MMC_SD
++ */
++
++
++
++/* Offsets of the SDHC registers */
++#define MMC_STR_STP_CLK                 0x00    /* Clock Control Reg */
++#define MMC_STATUS                      0x04    /* Status Reg */
++#define MMC_CLK_RATE                    0x08    /* Clock Rate Reg */
++#define MMC_CMD_DAT_CONT                0x0C    /* Command and Datacont reg */
++#define MMC_RES_TO                      0x10    /* Response Time-out Reg */
++#define MMC_READ_TO                     0x14    /* Read Time-out Reg */
++#define MMC_BLK_LEN                     0x18    /* Block Length Reg */
++#define MMC_NOB                         0x1C    /* Number of Blocks Reg */
++#define MMC_REV_NO                      0x20    /* Revision Number Reg */
++#define MMC_INT_CNTR                    0x24    /* Interrupt Control Reg */
++#define MMC_CMD                         0x28    /* Command Number Reg */
++#define MMC_ARG                         0x2C    /* Command Argument Reg */
++#define MMC_RES_FIFO                    0x34    /* Command Response Reg */
++#define MMC_BUFFER_ACCESS               0x38    /* Data Buffer Access Reg */
++
++/* Bit definitions for STR_STP_CLK */
++#define STR_STP_CLK_IPG_CLK_GATE_DIS    (1<<15)
++#define STR_STP_CLK_IPG_PERCLK_GATE_DIS (1<<14)
++#define STR_STP_CLK_RESET               (1<<3)
++#define STR_STP_CLK_START_CLK           (1<<1)
++#define STR_STP_CLK_STOP_CLK            (1<<0)
++
++/* Bit definitions for STATUS */
++#define STATUS_CARD_INSERTION           (1<<31)
++#define STATUS_CARD_REMOVAL             (1<<30)
++#define STATUS_YBUF_EMPTY               (1<<29)
++#define STATUS_XBUF_EMPTY               (1<<28)
++#define STATUS_YBUF_FULL                (1<<27)
++#define STATUS_XBUF_FULL                (1<<26)
++#define STATUS_BUF_UND_RUN              (1<<25)
++#define STATUS_BUF_OVFL                 (1<<24)
++#define STATUS_SDIO_INT_ACTIVE          (1<<14)
++#define STATUS_END_CMD_RESP             (1<<13)
++#define STATUS_WRITE_OP_DONE            (1<<12)
++#define STATUS_READ_OP_DONE             (1<<11)
++#define STATUS_WR_CRC_ERROR_CODE_MASK   (3<<10)
++#define STATUS_CARD_BUS_CLK_RUN         (1<<8)
++#define STATUS_BUF_READ_RDY             (1<<7)
++#define STATUS_BUF_WRITE_RDY            (1<<6)
++#define STATUS_RESP_CRC_ERR             (1<<5)
++#define STATUS_READ_CRC_ERR             (1<<3)
++#define STATUS_WRITE_CRC_ERR            (1<<2)
++#define STATUS_TIME_OUT_RESP            (1<<1)
++#define STATUS_TIME_OUT_READ            (1<<0)
++#define STATUS_ERR_MASK                 0x3f
++
++/* Clock rate definitions */
++#define CLK_RATE_PRESCALER(x)           ((x) & 0xF)
++#define CLK_RATE_CLK_DIVIDER(x)         (((x) & 0xF) << 4)
++
++/* Bit definitions for CMD_DAT_CONT */
++#define CMD_DAT_CONT_CMD_RESP_LONG_OFF  (1<<12)
++#define CMD_DAT_CONT_STOP_READWAIT      (1<<11)
++#define CMD_DAT_CONT_START_READWAIT     (1<<10)
++#define CMD_DAT_CONT_BUS_WIDTH_1        (0<<8)
++#define CMD_DAT_CONT_BUS_WIDTH_4        (2<<8)
++#define CMD_DAT_CONT_INIT               (1<<7)
++#define CMD_DAT_CONT_WRITE              (1<<4)
++#define CMD_DAT_CONT_DATA_ENABLE        (1<<3)
++#define CMD_DAT_CONT_RESPONSE_FORMAT_R1 (1)
++#define CMD_DAT_CONT_RESPONSE_FORMAT_R2 (2)
++#define CMD_DAT_CONT_RESPONSE_FORMAT_R3 (3)
++#define CMD_DAT_CONT_RESPONSE_FORMAT_R4 (4)
++#define CMD_DAT_CONT_RESPONSE_FORMAT_R5 (5)
++#define CMD_DAT_CONT_RESPONSE_FORMAT_R6 (6)
++
++/* Bit definitions for INT_CNTR */
++#define INT_CNTR_SDIO_INT_WKP_EN        (1<<18)
++#define INT_CNTR_CARD_INSERTION_WKP_EN  (1<<17)
++#define INT_CNTR_CARD_REMOVAL_WKP_EN    (1<<16)
++#define INT_CNTR_CARD_INSERTION_EN      (1<<15)
++#define INT_CNTR_CARD_REMOVAL_EN        (1<<14)
++#define INT_CNTR_SDIO_IRQ_EN            (1<<13)
++#define INT_CNTR_DAT0_EN                (1<<12)
++#define INT_CNTR_BUF_READ_EN            (1<<4)
++#define INT_CNTR_BUF_WRITE_EN           (1<<3)
++#define INT_CNTR_END_CMD_RES            (1<<2)
++#define INT_CNTR_WRITE_OP_DONE          (1<<1)
++#define INT_CNTR_READ_OP_DONE           (1<<0)
++#define INT_CNTR_NO_INTR           (0)
++
++#define SDHC_SLOTS_NUMBER      1
++#define READ_TO_VALUE                   0x2db4
++
++struct sdhc_chip;
++
++struct sdhc_host {
++       struct fsl_dma_requestbuf   *dma;
++
++       struct sdhc_chip       *chip;
++       struct mmc_host         *mmc;           /* MMC structure */
++
++       spinlock_t              lock;           /* Mutex */
++
++       int                     flags;          /* Host attributes */
++#define SDHC_USE_DMA          (1<<0)
++
++       unsigned int            max_clk;        /* Max possible freq (MHz) */
++       unsigned int            timeout_clk;    /* Timeout freq (KHz) */
++
++       unsigned int            clock;          /* Current clock (MHz) */
++       unsigned short          power;          /* Current voltage */
++       unsigned short          bus_width;      /* current bus width */
++
++       struct mmc_request      *mrq;           /* Current request */
++       struct mmc_command      *cmd;           /* Current command */
++       struct mmc_data         *data;          /* Current data request */
++       int                     irq;            /* Device IRQ */
++       unsigned long           addr;           /* Bus address */
++       unsigned int            size;           /* IO size */
++       void __iomem            *ioaddr;        /* Mapped address */
++
++       struct tasklet_struct   card_tasklet;   /* Tasklet structures */
++       struct tasklet_struct   finish_tasklet;
++
++
++       struct clk *sdhc_clk;
++       unsigned int dma_size;
++       int    dma_available ;
++
++       char                    slot_descr[20]; /* Name for reservations */
++
++
++} __attribute__ ((aligned(4)));
++
++struct sdhc_chip {
++       struct of_device        *ofdev;
++
++       unsigned long           quirks;
++
++       int                     num_slots;      /* Slots on controller */
++       struct sdhc_host       *hosts[0];      /* Pointers to hosts */
++};
++#endif /* __MPC5121_SDHC_H__ */
+diff -Naur linux-2.6.29/drivers/mtd/mtdpart.c linux-2.6.29-v2010041601/drivers/mtd/mtdpart.c
+--- linux-2.6.29/drivers/mtd/mtdpart.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/mtd/mtdpart.c	2010-04-13 20:23:26.000000000 +0200
+@@ -393,6 +393,8 @@
+ 
+ 	if (slave->offset == MTDPART_OFS_APPEND)
+ 		slave->offset = cur_offset;
++	if(slave->offset>=0xffffffff)
++		slave->offset = cur_offset;
+ 	if (slave->offset == MTDPART_OFS_NXTBLK) {
+ 		slave->offset = cur_offset;
+ 		if (mtd_mod_by_eb(cur_offset, master) != 0) {
+diff -Naur linux-2.6.29/drivers/mtd/nand/Kconfig linux-2.6.29-v2010041601/drivers/mtd/nand/Kconfig
+--- linux-2.6.29/drivers/mtd/nand/Kconfig	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/mtd/nand/Kconfig	2010-04-13 20:23:26.000000000 +0200
+@@ -138,6 +138,39 @@
+ 	help
+ 	  This enables the NAND flash driver on the PPChameleon EVB Board.
+ 
++config MTD_NAND_MPC5125_NFC
++	tristate "MPC5125 built-in NAND Flash Controller support"
++	depends on PPC_MPC512x && MPC5125_TWR
++	help
++	  This enables the driver for the NAND flash controller on the
++	  MPC5125 SoC.
++
++config MTD_NAND_FSL
++	tristate "NAND Flash controller for MPC512x"
++	depends on PPC_MPC512x && MTD_NAND_MPC5125_NFC
++	help
++	  This enables the NAND flash driver on the MPC512x SOC.
++
++config MTD_NAND_MPC5125_HARDWARE_ECC_CORRECTION
++	bool "hardware ECC support "
++	depends on MTD_NAND_FSL && MTD_NAND_MPC5125_NFC
++	help
++	  This enables the support for Software ECC handling. By
++	  default FSL NAND controller Hardware ECC is supported.
++
++config NFC_DMA_ENABLE
++	bool "Enable nand flash ctroller dma"
++	depends on MTD_NAND_FSL && MTD_NAND_MPC5125_NFC
++	help
++	  This enables the nfc dma support
++
++#config MTD_NAND_FSL_ECC_CORRECTION_OPTION2
++#	bool "ECC correction in S/W"
++#	depends on MTD_NAND_FSL && MTD_NAND_MPC5125_NFC
++#	help
++#	  This enables the Option2 NFC ECC correction in software. By
++#	  default Option 1 is selected. Enable if you need option2 ECC correction.
++
+ config MTD_NAND_S3C2410
+ 	tristate "NAND Flash support for S3C2410/S3C2440 SoC"
+ 	depends on ARCH_S3C2410
+diff -Naur linux-2.6.29/drivers/mtd/nand/Makefile linux-2.6.29-v2010041601/drivers/mtd/nand/Makefile
+--- linux-2.6.29/drivers/mtd/nand/Makefile	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/mtd/nand/Makefile	2010-04-13 20:23:26.000000000 +0200
+@@ -13,6 +13,7 @@
+ obj-$(CONFIG_MTD_NAND_AU1550)		+= au1550nd.o
+ obj-$(CONFIG_MTD_NAND_BF5XX)		+= bf5xx_nand.o
+ obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB)	+= ppchameleonevb.o
++obj-$(CONFIG_MTD_NAND_MPC5125_NFC)	+= mpc5125_nfc.o
+ obj-$(CONFIG_MTD_NAND_S3C2410)		+= s3c2410.o
+ obj-$(CONFIG_MTD_NAND_DISKONCHIP)	+= diskonchip.o
+ obj-$(CONFIG_MTD_NAND_H1900)		+= h1910.o
+diff -Naur linux-2.6.29/drivers/mtd/nand/mpc5125_nfc.c linux-2.6.29-v2010041601/drivers/mtd/nand/mpc5125_nfc.c
+--- linux-2.6.29/drivers/mtd/nand/mpc5125_nfc.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/mtd/nand/mpc5125_nfc.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,1295 @@
++/*
++ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
++ *
++ * Author: Shaohui Xie <b21989@freescale.com>
++ *
++ * Description:
++ * MPC5125 Nand driver.
++ *
++ * Based on original driver mpc5121_nfc.c.
++ *
++ * This is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++ /*
++ modyfied by Cloudy Chen <chen_yunsong@mtcera.com>
++ */
++
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/partitions.h>
++#include <linux/of_device.h>
++#include <linux/of_platform.h>
++
++#include <asm/mpc512x.h>
++#include <asm/mpc5125_nfc.h>
++#include <linux/dma-mapping.h>
++
++#define	DRV_NAME		"mpc5125_nfc"
++#define	DRV_VERSION		"0.5"
++#define	SPARE_BUFFER_MAX_SIZE	0x400
++#define	DATA_BUFFER_MAX_SIZE		0x2000
++/* Timeouts */
++#define NFC_RESET_TIMEOUT	1000		/* 1 ms */
++#define NFC_TIMEOUT		(HZ / 10)	/* 1/10 s */
++
++#ifdef CONFIG_NFC_DMA_ENABLE
++#define NFC_DMA_ENABLE		1
++#else
++#define NFC_DMA_ENABLE		0
++#endif
++struct mpc5125_nfc_prv {
++	struct mtd_info		mtd;
++	struct device *dev;
++	struct nand_chip	chip;
++#ifdef CONFIG_MTD_PARTITIONS
++	struct mtd_partition *parts;
++	int nr_parts;
++#endif
++	int			irq;
++	void __iomem		*regs;
++	struct clk		*clk;
++	wait_queue_head_t	irq_waitq;
++	uint			column;
++	int			spareonly;
++	u32		irq_stat;
++	u32		wait_timeout;
++	void __iomem		*csreg;
++	void  *data_buffers;
++       dma_addr_t      data_buffers_phyaddr;
++       void  *ops_buffer;
++       dma_addr_t      ops_buffer_phyaddr;
++       void *tmp_buf;
++	struct semaphore  int_sem;
++	 unsigned int sync_flags;
++};
++
++static int get_status;
++static int get_id;
++
++#define	NFC_IRQ_ENABLE	(IDLE_EN_MASK|WERR_EN_MASK)
++#define	NFC_IRQ_MASK		(IDLE_IRQ_MASK|WERR_IRQ_MASK)
++
++#ifdef CONFIG_MTD_NAND_MPC5125_HARDWARE_ECC_CORRECTION
++static int hardware_ecc = 1;
++#else
++static int hardware_ecc = 0;
++#endif
++#define	MPC5125_NFC_ECC_STATUS_ADD	(NFC_SPARE_AREA(0)+0xf0)
++#if 1
++/*for ecc_MODE=0x6 45bytes*2*/
++static struct nand_ecclayout nand_hw_eccoob_4k = {
++	.eccbytes = 90,	/* actually 72 but only room for 64 */
++	.eccpos = {
++		/* 9 bytes of ecc for each 512 bytes of data */
++		19,20,21,22,23,24,25,26,27,28,29,30,
++		31,32,33,34,35,36,37,38,39,40,
++		41, 42, 43, 44, 45, 46, 47,48,49,50,
++		51,52,53,54,55, 56, 57, 58, 59, 60,
++		61, 62, 63,
++		83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,
++		98,99,100,
++		101,102,103,104,105,106,107,108,109,110,
++		111,112,113,114,115,116,117,118,119,120,
++		121,122,123,124,125,126,127/* 120, 121, 122, 123, 124, 125, 126, 127, */
++	},
++	.oobavail = 30,
++	.oobfree = { {4, 15}, {68, 15}}
++};
++#else
++/*for ecc_MODE=0x5 30bytes*2*/
++static struct nand_ecclayout nand_hw_eccoob_4k = {
++	.eccbytes = 60,	/* actually 72 but only room for 64 */
++	.eccpos = {
++		/* 9 bytes of ecc for each 512 bytes of data */
++		34,35,36,37,38,39,40,
++		41, 42, 43, 44, 45, 46, 47,48,49,50,
++		51,52,53,54,55, 56, 57, 58, 59, 60,
++		61, 62, 63,
++		98,99,100,
++		101,102,103,104,105,106,107,108,109,110,
++		111,112,113,114,115,116,117,118,119,120,
++		121,122,123,124,125,126,127/* 120, 121, 122, 123, 124, 125, 126, 127, */
++	},
++	.oobavail = 48,
++	.oobfree = { {8, 24}, {68, 24}}
++};
++#endif
++
++#if NFC_DMA_ENABLE
++static void mpc5125_dma_config(struct mtd_info *mtd, struct nand_chip *chip,unsigned isRead);
++static void mpc5125_nand_dma_wait(struct mtd_info *mtd, struct nand_chip *chip);
++#endif
++
++static struct nand_ecclayout nand_hw_eccoob_4k_218_spare = {
++	.eccbytes = 64,	/* actually 144 but only room for 64 */
++	.eccpos = {
++		/* 18 bytes of ecc for each 512 bytes of data */
++		7, 8, 9, 10, 11, 12, 13, 14, 15,
++		    16, 17, 18, 19, 20, 21, 22, 23, 24,
++		33, 34, 35, 36, 37, 38, 39, 40, 41,
++		    42, 43, 44, 45, 46, 47, 48, 49, 50,
++		59, 60, 61, 62, 63, 64, 65, 66, 67,
++		    68, 69, 70, 71, 72, 73, 74, 75, 76,
++		85, 86, 87, 88, 89, 90, 91, 92, 93,
++		    94, /* 95, 96, 97, 98, 99, 100, 101, 102,
++		111, 112, 113, 114, 115, 116, 117, 118, 119,
++		    120, 121, 122, 123, 124, 125, 126, 127, 128,
++		137, 138, 139, 140, 141, 142, 143, 144, 145,
++		    146, 147, 148, 149, 150, 151, 152, 153, 154,
++		163, 164, 165, 166, 167, 168, 169, 170, 171,
++		    172, 173, 174, 175, 176, 177, 178, 179, 180,
++		189, 190, 191, 192, 193, 194, 195, 196, 197,
++		    198, 199, 200, 201, 202, 203, 204, 205, 206, */
++	},
++	.oobavail = 4,
++	.oobfree = {{0, 5}, {26, 8}, {52, 8}, {78, 8},
++		    {104, 8}, {130, 8}, {156, 8}, {182, 8}}
++};
++
++#ifdef CONFIG_MTD_PARTITIONS
++static const char *mpc5125_nfc_pprobes[] = { "cmdlinepart", NULL };
++#endif
++
++static inline u32 nfc_read(struct mtd_info *mtd, uint reg)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++
++	return in_be32(prv->regs + reg);
++}
++
++/* Write NFC register */
++static inline void nfc_write(struct mtd_info *mtd, uint reg, u32 val)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	out_be32(prv->regs + reg, val);
++}
++
++/* Set bits in NFC register */
++static inline void nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
++{
++	nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
++}
++
++/* Clear bits in NFC register */
++static inline void nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
++{
++	nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
++}
++
++
++static inline void
++nfc_set_field(struct mtd_info *mtd, u32 reg, u32 mask, u32 shift, u32 val)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++
++	out_be32(prv->regs + reg,
++			(in_be32(prv->regs + reg) & (~mask))
++			| val << shift);
++}
++
++static inline int
++nfc_get_field(struct mtd_info *mtd, u32 reg, u32 field_mask)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++
++	return in_be32(prv->regs + reg) & field_mask;
++}
++
++static inline u8 nfc_check_status(struct mtd_info *mtd)
++{
++	u8 fls_status = 0;
++	fls_status = nfc_get_field(mtd, NFC_FLASH_STATUS2, STATUS_BYTE1_MASK);
++	return fls_status;
++}
++
++/* clear cmd_done and cmd_idle falg for the coming command */
++static void mpc5125_nfc_clear(struct mtd_info *mtd)
++{
++	nfc_write(mtd, NFC_IRQ_STATUS, 1 << CMD_DONE_CLEAR_SHIFT);
++	nfc_write(mtd, NFC_IRQ_STATUS, 1 << IDLE_CLEAR_SHIFT);
++	nfc_write(mtd, NFC_IRQ_STATUS, 1 << WERR_CLEAR_SHIFT);
++}
++
++/* Wait for operation complete */
++static void mpc5125_nfc_done(struct mtd_info *mtd)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	int rv;
++	unsigned int wait_time=NFC_TIMEOUT;
++	mpc5125_nfc_clear(mtd);
++	nfc_set(mtd, NFC_IRQ_STATUS, NFC_IRQ_ENABLE);
++	prv->wait_timeout=0;
++	prv->sync_flags=0;
++	nfc_set_field(mtd, NFC_FLASH_CMD2, START_MASK,
++			START_SHIFT, 1);
++	{
++	if (!(nfc_read(mtd,NFC_IRQ_STATUS)&(NFC_IRQ_MASK))){
++		rv = wait_event_timeout(prv->irq_waitq,
++			(nfc_read(mtd,NFC_IRQ_STATUS)&NFC_IRQ_MASK),
++			wait_time);
++		if ((!rv))
++		{
++			prv->irq_stat=nfc_read(mtd,NFC_IRQ_STATUS);
++
++			if(!(prv->sync_flags))
++				printk(KERN_WARNING DRV_NAME
++				":Lost irq :%08x.\n");
++
++			printk(KERN_WARNING DRV_NAME
++				": Timeout while waiting for BUSY :%08x.\n",prv->irq_stat);
++			prv->wait_timeout=1;
++
++		}
++	}
++	}
++	mpc5125_nfc_clear(mtd);
++}
++
++static inline u8 mpc5125_nfc_get_id(struct mtd_info *mtd, int col)
++{
++	u32 flash_id1 = 0;
++	u8 *pid;
++
++	flash_id1 = nfc_read(mtd, NFC_FLASH_STATUS1);
++	pid = (u8 *)&flash_id1;
++
++	return *(pid + col);
++}
++
++static inline u8 mpc5125_nfc_get_status(struct mtd_info *mtd)
++{
++	u32 flash_status = 0;
++	u8 *pstatus;
++
++	flash_status = nfc_read(mtd, NFC_FLASH_STATUS2);
++	pstatus = (u8 *)&flash_status;
++
++	return *(pstatus + 3);
++}
++
++/* Invoke command cycle */
++static inline void
++mpc5125_nfc_send_cmd(struct mtd_info *mtd, u32 cmd_byte1,
++		u32 cmd_byte2, u32 cmd_code)
++{
++	mpc5125_nfc_clear(mtd);
++	nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
++			CMD_BYTE1_SHIFT, cmd_byte1);
++
++	nfc_set_field(mtd, NFC_FLASH_CMD1, CMD_BYTE2_MASK,
++			CMD_BYTE2_SHIFT, cmd_byte2);
++
++	nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
++			BUFNO_SHIFT, 0);
++
++	nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK,
++			CMD_CODE_SHIFT, cmd_code);
++
++	if (cmd_code == RANDOM_OUT_CMD_CODE)
++		nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
++			BUFNO_SHIFT, 1);
++}
++
++/* Receive ID and status from NAND flash */
++static inline void
++mpc5125_nfc_send_one_byte(struct mtd_info *mtd, u32 cmd_byte1, u32 cmd_code)
++{
++	mpc5125_nfc_clear(mtd);
++	nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
++			CMD_BYTE1_SHIFT, cmd_byte1);
++
++	nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
++			BUFNO_SHIFT, 0);
++
++	nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK,
++			CMD_CODE_SHIFT, cmd_code);
++}
++
++/* NFC interrupt handler */
++static irqreturn_t mpc5125_nfc_irq(int irq, void *data)
++{
++	struct mtd_info *mtd = data;
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	prv->irq_stat=nfc_read(mtd,NFC_IRQ_STATUS);
++	nfc_clear(mtd, NFC_IRQ_STATUS, NFC_IRQ_ENABLE);
++	wake_up(&prv->irq_waitq);
++	/*mpc5125_nfc_clear(mtd);*/
++	prv->sync_flags|=1;
++	return IRQ_HANDLED;
++}
++
++/* Do address cycle(s) */
++static void mpc5125_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
++{
++
++	if (column != -1) {
++		nfc_set_field(mtd, NFC_COL_ADDR,
++				COL_ADDR_MASK,
++				COL_ADDR_SHIFT, column);
++	}
++
++	if (page != -1) {
++		nfc_set_field(mtd, NFC_ROW_ADDR,
++				ROW_ADDR_MASK,
++				ROW_ADDR_SHIFT, page);
++	}
++	/* DMA Disable */
++#if (NFC_DMA_ENABLE<1)
++	nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_MASK);
++#endif
++	/* PAGE_CNT = 1 */
++	nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
++			CONFIG_PAGE_CNT_SHIFT, 0x2);
++}
++
++
++/* Control chips select signal on ADS5125 board */
++static void ads5125_select_chip(struct mtd_info *mtd, int chip)
++{
++
++	if ((chip < 0)||(chip>3)) {
++			nfc_set_field(mtd, NFC_ROW_ADDR,
++			ROW_ADDR_CHIP_SEL_RB_MASK,
++			ROW_ADDR_CHIP_SEL_RB_SHIFT, 0);
++
++			nfc_set_field(mtd, NFC_ROW_ADDR,
++			ROW_ADDR_CHIP_SEL_MASK,
++			ROW_ADDR_CHIP_SEL_SHIFT, 0);
++		return;
++	}
++
++			nfc_set_field(mtd, NFC_ROW_ADDR,
++			ROW_ADDR_CHIP_SEL_RB_MASK,
++			ROW_ADDR_CHIP_SEL_RB_SHIFT, (1<<chip));
++
++			nfc_set_field(mtd, NFC_ROW_ADDR,
++			ROW_ADDR_CHIP_SEL_MASK,
++			ROW_ADDR_CHIP_SEL_SHIFT, (1<<chip));
++
++}
++
++/* Read NAND Ready/Busy signal */
++static int mpc5125_nfc_dev_ready(struct mtd_info *mtd)
++{
++	/*
++	 * NFC handles ready/busy signal internally. Therefore, this function
++	 * always returns status as ready.
++	 */
++	return 1;
++}
++
++/* Write command to NAND flash */
++static void mpc5125_nfc_command(struct mtd_info *mtd, unsigned command,
++						int column, int page)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++
++	prv->column = (column >= 0) ? column : 0;
++	prv->spareonly = 0;
++	get_id = 0;
++	get_status = 0;
++
++
++	switch (command) {
++	case NAND_CMD_PAGEPROG:
++		mpc5125_nfc_send_cmd(mtd,
++				PROGRAM_PAGE_CMD_BYTE1,
++				PROGRAM_PAGE_CMD_BYTE2,
++#if (NFC_DMA_ENABLE)
++				DMA_PROGRAM_PAGE_CMD_CODE);
++		/*
++		nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
++			CMD_BYTE1_SHIFT, READ_STATUS_CMD_BYTE);
++			*/
++		mpc5125_dma_config(mtd,chip,0);
++#else
++				PROGRAM_PAGE_CMD_CODE);
++#endif
++		break;
++	/*
++	 * NFC does not support sub-page reads and writes,
++	 * so emulate them using full page transfers.
++	 */
++	case NAND_CMD_READ0:
++		column = 0;
++		goto read0;
++		break;
++
++	case NAND_CMD_READ1:
++		prv->column += 256;
++		command = NAND_CMD_READ0;
++		column = 0;
++		goto read0;
++		break;
++
++	case NAND_CMD_READOOB:
++		prv->spareonly = 1;
++		command = NAND_CMD_READ0;
++		column = 0;
++read0:
++
++		mpc5125_nfc_send_cmd(mtd,
++				PAGE_READ_CMD_BYTE1,
++				PAGE_READ_CMD_BYTE2,
++				READ_PAGE_CMD_CODE);
++#if NFC_DMA_ENABLE
++		mpc5125_dma_config( mtd,  chip,1);
++#endif
++		break;
++
++	case NAND_CMD_SEQIN:
++		mpc5125_nfc_command(mtd, NAND_CMD_READ0, column, page);
++		column = 0;
++		break;
++
++	case NAND_CMD_ERASE1:
++		mpc5125_nfc_send_cmd(mtd,
++				ERASE_CMD_BYTE1,
++				ERASE_CMD_BYTE2,
++				ERASE_CMD_CODE);
++		break;
++	case NAND_CMD_ERASE2:
++		return;
++	case NAND_CMD_READID:
++		get_id = 1;
++		mpc5125_nfc_send_one_byte(mtd, command, READ_ID_CMD_CODE);
++		break;
++	case NAND_CMD_STATUS:
++		get_status = 1;
++		mpc5125_nfc_send_one_byte(mtd, command, STATUS_READ_CMD_CODE);
++		break;
++	case NAND_CMD_RNDOUT:
++		mpc5125_nfc_send_cmd(mtd,
++				RANDOM_OUT_CMD_BYTE1,
++				RANDOM_OUT_CMD_BYTE2,
++				RANDOM_OUT_CMD_CODE);
++		break;
++	default:
++		return;
++	}
++
++	mpc5125_nfc_addr_cycle(mtd, column, page);
++	mpc5125_nfc_done(mtd);
++
++#if (NFC_DMA_ENABLE)
++	/*mpc5125_nand_dma_wait(mtd,chip);*/
++	nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_MASK);
++#endif
++
++
++}
++
++/* Copy data from/to NFC spare buffers. */
++static void mpc5125_nfc_copy_spare(struct mtd_info *mtd, uint offset,
++						u8 *buffer, uint size, int wr)
++{
++	struct nand_chip *nand = mtd->priv;
++	struct mpc5125_nfc_prv *prv = nand->priv;
++	u16 ooblen = mtd->oobsize;
++	u8 i, count;
++	uint  sbsize, blksize;
++
++	/*
++	 * NAND spare area is available through NFC spare buffers.
++	 * The NFC divides spare area into (page_size / 512) chunks.
++	 * Each chunk is placed into separate spare memory area, using
++	 * first (spare_size / num_of_chunks) bytes of the buffer.
++	 *
++	 * For NAND device in which the spare area is not divided fully
++	 * by the number of chunks, number of used bytes in each spare
++	 * buffer is rounded down to the nearest even number of bytes,
++	 * and all remaining bytes are added to the last used spare area.
++	 *
++	 * For more information read section 26.6.10 of MPC5121e
++	 * Microcontroller Reference Manual, Rev. 3.
++	 */
++
++	/* Calculate number of valid bytes in each spare buffer */
++	count = mtd->writesize >> 11;
++	count=(count>0)?count:1;
++	sbsize = (ooblen / count >> 1) << 1;
++	/*printk("%s line:%d  %s len:%d\n",__FUNCTION__,__LINE__,wr?"write":"read",size);*/
++	for(i=0;(i<count)&&size;i++)
++	{
++		blksize = min(sbsize, size);
++		if(wr)
++		{
++			memcpy_toio(prv->regs + NFC_SPARE_AREA(i) ,
++							buffer, blksize);
++		}
++		else
++		{
++			memcpy_fromio(buffer,
++				prv->regs + NFC_SPARE_AREA(i), blksize);
++		}
++		/*mpc5125_spare_debug(buffer,blksize);*/
++		buffer += blksize;
++		offset += blksize;
++		size -= blksize;
++	}
++}
++
++/* Copy data from/to NFC main and spare buffers */
++static void mpc5125_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
++									int wr)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	uint c = prv->column;
++	uint l;
++	/* Handle spare area access */
++	if (prv->spareonly || c >= mtd->writesize) {
++		/* Calculate offset from beginning of spare area */
++		if (c >= mtd->writesize)
++			c -= mtd->writesize;
++
++		prv->column += len;
++#if NFC_DMA_ENABLE
++		if(wr)
++		{
++			memcpy(prv->ops_buffer,buf,len);
++		}
++		else
++		{
++			memcpy(buf,prv->ops_buffer,len);
++		}
++#else
++		mpc5125_nfc_copy_spare(mtd, c, buf, len, wr);
++#endif
++		return;
++	}
++
++	/*
++	 * Handle main area access - limit copy length to prevent
++	 * crossing main/spare boundary.
++	 */
++	l = min((uint)len, mtd->writesize - c);
++	/*
++	printk("%s line:%d %s l=0x%x,mtd->writesize=0x%x,c=0x%x \n",__FUNCTION__,__LINE__,wr?"write":"read",l,mtd->writesize,c);
++	*/
++	prv->column += l;
++
++	if (wr)
++	{
++		unsigned int size,i;
++#if NFC_DMA_ENABLE
++		memcpy(prv->data_buffers+c,buf,len);
++#else
++		for(i=(c/PAGE_2K);i<4;i++)
++		{
++			size=min(len,PAGE_2K);
++			memcpy_toio(prv->regs + NFC_MAIN_AREA(i) + c, buf, size);
++			buf+=size;
++			len-=size;
++			if(!len)break;
++		}
++#endif
++	}
++	else {
++		if (get_status) {
++			get_status = 0;
++			*buf = mpc5125_nfc_get_status(mtd);
++		} else if (l == 1 && c <= 3 && get_id) {
++			*buf = mpc5125_nfc_get_id(mtd, c);
++		} else
++		{
++			unsigned int size,i;
++#if NFC_DMA_ENABLE
++			if(len==mtd->writesize)
++				{
++			memcpy(buf,prv->data_buffers+c,len);
++				}
++			else
++#endif
++			for(i=(c/PAGE_2K);i<4;i++)
++			{
++				size=min(len,PAGE_2K);
++				memcpy_fromio(buf,prv->regs + NFC_MAIN_AREA(i) + c, size);
++				buf+=size;
++				len-=size;
++				if(!len)break;
++			}
++		}
++	}
++}
++
++/* Read data from NFC buffers */
++static void mpc5125_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
++{
++	mpc5125_nfc_buf_copy(mtd, buf, len, 0);
++}
++
++/* Write data to NFC buffers */
++static void mpc5125_nfc_write_buf(struct mtd_info *mtd,
++						const u_char *buf, int len)
++{
++	mpc5125_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
++}
++
++/* Compare buffer with NAND flash */
++static int mpc5125_nfc_verify_buf(struct mtd_info *mtd,
++						const u_char *buf, int len)
++{
++	u_char tmp[256];
++	uint bsize;
++	while (len) {
++		bsize = min(len, 256);
++		mpc5125_nfc_read_buf(mtd, tmp, bsize);
++		if (memcmp(buf, tmp, bsize))
++			return 1;
++		buf += bsize;
++		len -= bsize;
++	}
++	return 0;
++}
++
++/* Read byte from NFC buffers */
++static u8 mpc5125_nfc_read_byte(struct mtd_info *mtd)
++{
++	u8 tmp;
++	mpc5125_nfc_read_buf(mtd, &tmp, sizeof(tmp));
++	return tmp;
++}
++
++/* Read word from NFC buffers */
++static u16 mpc5125_nfc_read_word(struct mtd_info *mtd)
++{
++	u16 tmp;
++	mpc5125_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
++	return tmp;
++}
++
++/*
++ * Read NFC configuration from Reset Config Word
++ *
++ */
++static int mpc5125_nfc_read_hw_config(struct mtd_info *mtd)
++{
++	uint rcw_pagesize = 0;
++	uint rcw_sparesize = 0;
++
++	rcw_pagesize = 4096;
++	rcw_sparesize = 128;
++	mtd->writesize = rcw_pagesize;
++	mtd->oobsize = rcw_sparesize;
++	return 0;
++}
++
++/* Free driver resources */
++static void mpc5125_nfc_free(struct device *dev, struct mtd_info *mtd)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++
++	if (prv->clk) {
++		clk_disable(prv->clk);
++		clk_put(prv->clk);
++	}
++	if (prv->csreg)
++		iounmap(prv->csreg);
++}
++
++#ifdef CONFIG_MTD_PARTITIONS
++static int parse_flash_partitions(struct mtd_info *mtd,struct device_node *dp)
++{
++	int i;
++	const  char *name;
++	struct device_node *pp;
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	int nr_parts = 0;
++
++	for (pp = dp->child; pp; pp = pp->sibling)
++		nr_parts++;
++
++	if (!nr_parts)
++		return 0;
++
++	prv->parts = devm_kzalloc(prv->dev,
++			nr_parts * sizeof(struct mtd_partition),
++			GFP_KERNEL);
++	if (!prv->parts)
++		return -ENOMEM;
++	for (pp = dp->child, i =0; pp; pp = pp->sibling, i++) {
++		const u32 *reg;
++		int len;
++
++		reg = of_get_property(pp, "reg", &len);
++		if (!reg || (len != 2*sizeof(u32))) {
++			printk(KERN_ERR DRV_NAME ": "
++				"Invalid 'reg' on %s\n", dp->full_name);
++			kfree(prv->parts);
++			prv->parts = NULL;
++			return -EINVAL;
++		}
++		prv->parts[i].offset = reg[0];
++		prv->parts[i].size = reg[1];
++
++		name = of_get_property(pp, "label", &len);
++		if (!name)
++			name = of_get_property(pp, "name", &len);
++		prv->parts[i].name = (char *)name;
++
++		if (of_get_property(pp, "read-only", &len))
++			prv->parts[i].mask_flags = MTD_WRITEABLE;
++	}
++	return nr_parts;
++}
++#endif
++static void mpc5125_nand_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++	nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_ECC_MODE_MASK,
++			CONFIG_ECC_MODE_SHIFT, ECC_30_BYTE);
++	return;
++}
++/*
++ * Function to correct the detected errors. This NFC corrects all the errors
++ * detected. So this function is not required.
++ */
++static int mpc5125_nand_correct_data(struct mtd_info *mtd, u_char * dat,
++				 u_char * read_ecc, u_char * calc_ecc)
++{
++	panic("Shouldn't be called here: %d\n", __LINE__);
++	return 0;		/* FIXME */
++}
++
++/*
++ * Function to calculate the ECC for the data to be stored in the Nand device.
++ * This NFC has a hardware RS(511,503) ECC engine together with the RS ECC
++ * CONTROL blocks are responsible for detection  and correction of up to
++ * 4 symbols of 9 bits each in 528 byte page.
++ * So this function is not required.
++ */
++
++static int mpc5125_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat,
++				  u_char * ecc_code)
++{
++	panic(KERN_ERR "Shouldn't be called here %d \n", __LINE__);
++	return 0;		/* FIXME */
++}
++static int mpc5125_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
++			     int page, int sndcmd)
++{
++
++	if(sndcmd)
++	{
++		mpc5125_nfc_command(mtd,NAND_CMD_READ0,0,page);
++		sndcmd=0;
++	}
++#if NFC_DMA_ENABLE
++{
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	memcpy(chip->oob_poi,prv->ops_buffer, mtd->oobsize);
++}
++#else
++	mpc5125_nfc_copy_spare(mtd,0,chip->oob_poi, mtd->oobsize,0);
++#endif
++	return sndcmd;
++}
++
++static int mpc5125_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
++			      int page)
++{
++
++	unsigned int stat;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	mpc5125_nfc_command(mtd,NAND_CMD_READ0,0,page);
++#if NFC_DMA_ENABLE
++	memcpy(prv->ops_buffer,chip->oob_poi, mtd->oobsize);
++#else
++	mpc5125_nfc_copy_spare(mtd,0,chip->oob_poi, mtd->oobsize,1);
++#endif
++	mpc5125_nfc_command(mtd,NAND_CMD_PAGEPROG,0,page);
++	if(prv->wait_timeout)
++	{
++		printk(KERN_ERR"%s line:%d wait timeout.\n",__FUNCTION__,__LINE__);
++		return -EIO;
++	}
++	if(prv->irq_stat&WERR_IRQ_MASK)
++	{
++		printk(KERN_ERR"%s line:%d faield.\n",__FUNCTION__,__LINE__);
++		return -EIO;
++	}
++	return 0;
++}
++
++static int mpc5125_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
++			      uint8_t * buf)
++{
++	unsigned int stat;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	u8 *erase_page_check,ecc_bytes=0,i;
++	u8 ecc_bytes_map[]={0,8,12,15,23,30,45,60};
++	stat=nfc_read(mtd, NFC_FLASH_CONFIG);
++	stat>>=17;
++	stat&=0x7;
++	ecc_bytes=ecc_bytes_map[stat];
++	erase_page_check=(u8 *)(PAGE_virtual_2K-ecc_bytes+prv->regs);
++	stat=nfc_read(mtd, MPC5125_NFC_ECC_STATUS_ADD+4);
++	DEBUG(MTD_DEBUEVEL3,"%s line:%d stat:%08x\n",__FUNCTION__,__LINE__,stat);
++	if(stat&0x80)
++	{
++		/*check the page is erased*/
++		if(stat&0x3f)
++		{
++			mtd->ecc_stats.failed++;
++			printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
++		}
++
++	}
++	else if(stat&0x3f)
++	{
++		/*printk(KERN_WARNING "Correctable ECC %d\n",stat&0x3f);*/
++		mtd->ecc_stats.corrected+=stat&0x3f;
++	}
++#if NFC_DMA_ENABLE
++	memcpy(buf,prv->data_buffers,mtd->writesize);
++	memcpy(chip->oob_poi,prv->ops_buffer, mtd->oobsize);
++#else
++	mpc5125_nfc_buf_copy(mtd, buf, mtd->writesize, 0);
++	mpc5125_nfc_copy_spare(mtd,0,chip->oob_poi, mtd->oobsize,0);
++#endif
++	return 0;
++}
++
++static void mpc5125_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
++				const uint8_t * buf)
++{
++#if NFC_DMA_ENABLE
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	memcpy(prv->data_buffers,buf,mtd->writesize);
++	memcpy(prv->ops_buffer,chip->oob_poi, mtd->oobsize);
++#else
++	mpc5125_nfc_buf_copy(mtd, buf, mtd->writesize, 1);
++	mpc5125_nfc_copy_spare(mtd,0,chip->oob_poi, mtd->oobsize,1);
++#endif
++
++}
++static int chip_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
++			   const uint8_t *buf, int page, int cached, int raw)
++{
++	int status;
++#if (NFC_DMA_ENABLE<1)
++	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
++#endif
++	if (unlikely(raw))
++		chip->ecc.write_page_raw(mtd, chip, buf);
++	else
++		chip->ecc.write_page(mtd, chip, buf);
++
++	/*
++	 * Cached progamming disabled for now, Not sure if its worth the
++	 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
++	 */
++	cached = 0;
++
++	if (!cached || !(chip->options & NAND_CACHEPRG)) {
++#if NFC_DMA_ENABLE
++		chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, 0x00, page);
++#else
++		chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
++#endif
++
++		status = chip->waitfunc(mtd, chip);
++		/*
++		 * See if operation failed and additional status checks are
++		 * available
++		 */
++		if ((status & NAND_STATUS_FAIL) && (chip->errstat))
++			status = chip->errstat(mtd, chip, FL_WRITING, status,
++					       page);
++
++		if (status & NAND_STATUS_FAIL)
++			return -EIO;
++	} else {
++#if NFC_DMA_ENABLE
++		chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, 0x00, page);
++#else
++		chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
++#endif
++		status = chip->waitfunc(mtd, chip);
++	}
++	if(nfc_get_field(mtd, NFC_IRQ_STATUS,WERR_IRQ_MASK|WERR_STATUS_MASK))
++	{
++		printk(KERN_ERR"%s line:%d write page %d failed\n",__FUNCTION__,__LINE__,page);
++		nfc_set_field(mtd, NFC_IRQ_STATUS,
++			WERR_CLEAR_MASK,
++			WERR_CLEAR_SHIFT, 1);
++		return -EIO;
++	}
++	return 0;
++}
++#if NFC_DMA_ENABLE
++static void mpc5125_dma_config(struct mtd_info *mtd, struct nand_chip *chip,unsigned isRead)
++{
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	nfc_write(mtd, NFC_DMA1_ADDR,prv->data_buffers_phyaddr);
++	nfc_write(mtd, NFC_DMA2_ADDR,prv->ops_buffer_phyaddr);
++	if(isRead)
++		nfc_set_field(mtd, NFC_FLASH_CONFIG,
++                       CONFIG_DMA_REQ_MASK,
++                       CONFIG_DMA_REQ_SHIFT, 1);
++	else
++		nfc_set_field(mtd, NFC_FLASH_CONFIG,
++                       CONFIG_DMA_REQ_MASK,
++                       CONFIG_DMA_REQ_SHIFT, 0);
++         nfc_set_field(mtd, NFC_FLASH_COMMAND_REPEAT,
++                       COMMAND_REPEAT_MASK,
++                       COMMAND_REPEAT_SHIFT, 0);
++	nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
++		BUFNO_SHIFT, 0);
++}
++static void mpc5125_nand_dma_wait(struct mtd_info *mtd, struct nand_chip *chip)
++{
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	if(((DMA_BUSY_MASK|ECC_BUSY_MASK|RESIDUE_BUSY_MASK)&nfc_read(mtd,NFC_IRQ_STATUS)))
++	{
++		int rv;
++		 rv=wait_event_timeout(prv->irq_waitq,
++			(nfc_read(mtd,NFC_IRQ_STATUS)&(CMD_DONE_IRQ_MASK|IDLE_IRQ_MASK))==(CMD_DONE_IRQ_MASK|IDLE_IRQ_MASK), NFC_TIMEOUT*4);
++		 if (!rv)
++		{
++
++			prv->irq_stat=nfc_read(mtd,NFC_IRQ_STATUS);
++			printk(KERN_ERR DRV_NAME"%s timeour status:%08x\n",__FUNCTION__,prv->irq_stat);
++			prv->wait_timeout=1;
++
++		}
++	}
++}
++/**
++ * nand_read_page_raw - [Intern] read raw page data without ecc
++ * @mtd:	mtd info structure
++ * @chip:	nand chip info structure
++ * @buf:	buffer to store read data
++ */
++static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
++			      uint8_t *buf)
++{
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	memcpy(buf,prv->data_buffers,mtd->writesize);
++	memcpy(chip->oob_poi,prv->ops_buffer, mtd->oobsize);
++	return 0;
++}
++/**
++ * nand_write_page_raw - [Intern] raw page write function
++ * @mtd:	mtd info structure
++ * @chip:	nand chip info structure
++ * @buf:	data buffer
++ */
++static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
++				const uint8_t *buf)
++{
++	struct mpc5125_nfc_prv *prv = chip->priv;
++	memcpy(prv->data_buffers,buf,mtd->writesize);
++	memcpy(prv->ops_buffer,chip->oob_poi, mtd->oobsize);
++	mpc5125_dma_config(mtd,chip,0);
++}
++#endif
++
++static int __init mpc5125_nfc_probe(struct of_device *op,
++					const struct of_device_id *match)
++{
++	struct device_node *rootnode, *dn = op->node;
++	struct device *dev = &op->dev;
++	struct mpc5125_nfc_prv *prv;
++	struct resource res;
++	struct mtd_info *mtd;
++	struct nand_chip *chip;
++	unsigned long regs_paddr, regs_size;
++	const uint *chips_no;
++	int retval = 0;
++	int len;
++	prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
++	if (!prv) {
++		printk(KERN_ERR DRV_NAME ": Memory exhausted!\n");
++		return -ENOMEM;
++	}
++	mtd = &prv->mtd;
++	chip = &prv->chip;
++
++	mtd->priv = chip;
++	chip->priv = prv;
++	prv->dev = dev;
++
++	/* Read NFC configuration from Reset Config Word */
++	retval = mpc5125_nfc_read_hw_config(mtd);
++	if (retval) {
++		printk(KERN_ERR DRV_NAME ": Unable to read NFC config!\n");
++		return retval;
++	}
++	/*speed up nand flash r/w add by cloudy*/
++	{
++		volatile u32 *nfc_div=ioremap(0x80000f80,sizeof(u32));
++		if(!nfc_div)
++		{
++			printk(KERN_ERR DRV_NAME ": Unable to speed up nfc !\n");
++		}
++		else
++		{
++#ifdef CONFIG_MTD_NAND_MPC5125_HARDWARE_ECC_CORRECTION
++			*nfc_div=(0x1430<<16);
++#else
++			*nfc_div=(0x2860<<16);
++#endif
++			iounmap(nfc_div);
++		}
++	}
++	prv->irq = irq_of_parse_and_map(dn, 0);
++	if (prv->irq == NO_IRQ) {
++		printk(KERN_ERR DRV_NAME ": Error mapping IRQ!\n");
++		return -EINVAL;
++	}
++	retval = of_address_to_resource(dn, 0, &res);
++	if (retval) {
++		printk(KERN_ERR DRV_NAME ": Error parsing memory region!\n");
++		return retval;
++	}
++	chips_no = of_get_property(dn, "chips", &len);
++	if (!chips_no || len != sizeof(*chips_no)) {
++		printk(KERN_ERR DRV_NAME ": Invalid/missing 'chips' "
++								"property!\n");
++		return -EINVAL;
++	}
++	regs_paddr = res.start;
++	regs_size = res.end - res.start + 1;
++	if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
++		printk(KERN_ERR DRV_NAME ": Error requesting memory region!\n");
++		return -EBUSY;
++	}
++	prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
++	if (!prv->regs) {
++		printk(KERN_ERR DRV_NAME ": Error mapping memory region!\n");
++		return -ENOMEM;
++	}
++	prv->data_buffers=dma_alloc_coherent(NULL, DATA_BUFFER_MAX_SIZE,
++                       &prv->data_buffers_phyaddr, GFP_KERNEL);
++	if(!prv->data_buffers)return -ENOMEM;
++	prv->ops_buffer=dma_alloc_coherent(NULL, SPARE_BUFFER_MAX_SIZE,
++                       &prv->ops_buffer_phyaddr, GFP_KERNEL);
++	if(!prv->ops_buffer)
++	{
++		dma_free_coherent(NULL,DATA_BUFFER_MAX_SIZE,prv->data_buffers,prv->data_buffers_phyaddr);
++		return -ENOMEM;
++	}
++	/* Enable NFC clock */
++	prv->clk = clk_get(dev, "nfc_clk");
++	if (!prv->clk) {
++		printk(KERN_ERR DRV_NAME ": Unable to acquire NFC clock!\n");
++		retval = -ENODEV;
++		goto error;
++	}
++	clk_enable(prv->clk);
++	init_waitqueue_head(&prv->irq_waitq);
++	retval = devm_request_irq(dev, prv->irq, &mpc5125_nfc_irq,
++			0, DRV_NAME, mtd);
++	if (retval) {
++		printk(KERN_ERR DRV_NAME ": Error requesting IRQ!\n");
++		goto error;
++	}
++
++	mtd->name = "MPC5125 NAND";
++	chip->write_page=chip_nand_write_page;
++	chip->dev_ready = mpc5125_nfc_dev_ready;
++	chip->cmdfunc = mpc5125_nfc_command;
++	chip->read_byte = mpc5125_nfc_read_byte;
++	chip->read_word = mpc5125_nfc_read_word;
++	chip->read_buf = mpc5125_nfc_read_buf;
++	chip->write_buf = mpc5125_nfc_write_buf;
++
++	chip->verify_buf = mpc5125_nfc_verify_buf;
++	chip->options = NAND_NO_AUTOINCR|NAND_USE_FLASH_BBT|NAND_SKIP_BBTSCAN;
++	chip->select_chip = ads5125_select_chip;
++	if(hardware_ecc)
++	{
++		chip->ecc.read_page = mpc5125_nand_read_page;
++		chip->ecc.write_page = mpc5125_nand_write_page;
++		chip->ecc.read_oob = mpc5125_nand_read_oob;
++		chip->ecc.write_oob = mpc5125_nand_write_oob;
++		chip->ecc.calculate = mpc5125_nand_calculate_ecc;
++		chip->ecc.hwctl = mpc5125_nand_enable_hwecc;
++		chip->ecc.correct = mpc5125_nand_correct_data;
++		chip->ecc.mode = NAND_ECC_HW;
++		chip->ecc.size = 512;	/* RS-ECC is applied for both MAIN+SPARE not MAIN alone */
++		chip->ecc.bytes = 9;	/* used for both main and spare area */
++		chip->ecc.layout=&nand_hw_eccoob_4k;
++		nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_ECC_SRAM_ADDR_MASK,
++			CONFIG_ECC_SRAM_ADDR_SHIFT, (MPC5125_NFC_ECC_STATUS_ADD>>3)&0x00001ff);
++
++		nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_ECC_MODE_MASK,
++			CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
++
++		nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_CMD_TIMEOUT_MASK,
++			CONFIG_CMD_TIMEOUT_SHIFT, 0xf);
++
++		nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_ECC_SRAM_REQ_MASK,
++			CONFIG_ECC_SRAM_REQ_SHIFT, 1);
++
++	}
++	else
++	{
++#if NFC_DMA_ENABLE
++		chip->ecc.read_page_raw= nand_read_page_raw;
++		chip->ecc.write_page_raw= nand_write_page_raw;
++#endif
++		chip->ecc.mode = NAND_ECC_SOFT;
++		chip->ecc.layout=&nand_hw_eccoob_4k;
++		nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_ECC_MODE_MASK,
++			CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
++		nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_ECC_SRAM_REQ_MASK,
++			CONFIG_ECC_SRAM_REQ_SHIFT, 0);
++	}
++	memset( &prv->int_sem, 0, sizeof(struct semaphore));
++	sema_init( &prv->int_sem, 0 );
++
++	/* SET SECTOR SIZE */
++	nfc_write(mtd, NFC_SECTOR_SIZE,PAGE_virtual_2K);
++	nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_PAGE_CNT_MASK,
++			CONFIG_PAGE_CNT_SHIFT, 2);
++	nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_ADDR_AUTO_INCR_MASK,
++			CONFIG_ADDR_AUTO_INCR_SHIFT, 0);
++	nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_BUFNO_AUTO_INCR_MASK,
++			CONFIG_BUFNO_AUTO_INCR_SHIFT, 1);
++	nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_16BIT_MASK,
++			CONFIG_16BIT_SHIFT, 0);
++#if NFC_DMA_ENABLE
++	nfc_set_field(mtd,NFC_DMA_CONFIG,DMA_CONFIG_DMA1_CNT_MASK,
++                       DMA_CONFIG_DMA1_CNT_SHIFT,PAGE_2K);
++        nfc_set_field(mtd,NFC_DMA_CONFIG,DMA_CONFIG_DMA2_CNT_MASK,
++                       DMA_CONFIG_DMA2_CNT_SHIFT,0x40);
++        nfc_set_field(mtd,NFC_DMA_CONFIG,DMA_CONFIG_DMA1_ACT_MASK,
++                       DMA_CONFIG_DMA1_ACT_SHIFT,1);
++         nfc_set_field(mtd,NFC_DMA_CONFIG,DMA_CONFIG_DMA2_OFFSET_MASK,
++                       DMA_CONFIG_DMA2_OFFSET_SHIFT,(PAGE_2K>>1));
++         nfc_set_field(mtd,NFC_DMA_CONFIG,DMA_CONFIG_DMA2_ACT_MASK,
++                       DMA_CONFIG_DMA2_ACT_SHIFT,1);
++#endif
++	/* SET FAST_FLASH = 1 */
++	nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_FAST_FLASH_MASK,
++			CONFIG_FAST_FLASH_SHIFT, 1);
++	nfc_set_field(mtd, NFC_FLASH_CONFIG,
++			CONFIG_BOOT_MODE_MASK,
++			CONFIG_BOOT_MODE_SHIFT, 0);
++	/* Detect NAND chips */
++	if (nand_scan(mtd, *chips_no)) {
++		printk(KERN_ERR DRV_NAME ": NAND Flash not found !\n");
++		devm_free_irq(dev, prv->irq, mtd);
++		retval = -ENXIO;
++		goto error;
++	}
++	dev_set_drvdata(dev, mtd);
++
++
++	/* Register the partitions */
++#ifdef CONFIG_MTD_PARTITIONS
++	prv->nr_parts =
++	    parse_mtd_partitions(mtd, mpc5125_nfc_pprobes, &prv->parts, 0);
++	if (prv->nr_parts > 0)
++		add_mtd_partitions(mtd, prv->parts, prv->nr_parts);
++	else if ((prv->nr_parts = parse_flash_partitions(mtd, dn)) > 0) {
++		dev_info(dev, "Using OF partition info\n");
++		add_mtd_partitions(mtd, prv->parts, prv->nr_parts);
++	} else
++#endif
++	{
++		pr_info("Registering %s as whole device\n", mtd->name);
++		add_mtd_device(mtd);
++	}
++	if (retval) {
++		printk(KERN_ERR DRV_NAME ": Error adding MTD device!\n");
++		devm_free_irq(dev, prv->irq, mtd);
++		goto error;
++	}
++	return 0;
++error:
++	dma_free_coherent(NULL,DATA_BUFFER_MAX_SIZE,prv->data_buffers,prv->data_buffers_phyaddr);
++	dma_free_coherent(NULL,SPARE_BUFFER_MAX_SIZE,prv->ops_buffer,prv->ops_buffer_phyaddr);
++	mpc5125_nfc_free(dev, mtd);
++	return retval;
++}
++
++static int __exit mpc5125_nfc_remove(struct of_device *op)
++{
++	struct device *dev = &op->dev;
++	struct mtd_info *mtd = dev_get_drvdata(dev);
++	struct nand_chip *chip = mtd->priv;
++	struct mpc5125_nfc_prv *prv = chip->priv;
++
++	nand_release(mtd);
++	devm_free_irq(dev, prv->irq, mtd);
++	dma_free_coherent(NULL,DATA_BUFFER_MAX_SIZE,prv->data_buffers,prv->data_buffers_phyaddr);
++	dma_free_coherent(NULL,SPARE_BUFFER_MAX_SIZE,prv->ops_buffer,prv->ops_buffer_phyaddr);
++	mpc5125_nfc_free(dev, mtd);
++
++	return 0;
++}
++
++static struct of_device_id mpc5125_nfc_match[] = {
++	{ .compatible = "fsl,mpc5125-nfc", },
++	{},
++};
++
++static struct of_platform_driver mpc5125_nfc_driver = {
++	.owner		= THIS_MODULE,
++	.name		= DRV_NAME,
++	.match_table	= mpc5125_nfc_match,
++	.probe		= mpc5125_nfc_probe,
++	.remove		= __exit_p(mpc5125_nfc_remove),
++	.suspend	= NULL,
++	.resume		= NULL,
++	.driver		= {
++		.name	= DRV_NAME,
++		.owner	= THIS_MODULE,
++	},
++};
++
++static int __init mpc5125_nfc_init(void)
++{
++	pr_info("MPC5125 MTD nand Driver %s\n", DRV_VERSION);
++	if (of_register_platform_driver(&mpc5125_nfc_driver) != 0) {
++		printk(KERN_ERR DRV_NAME ": Driver register failed!\n");
++		return -ENODEV;
++	}
++	return 0;
++}
++
++static void __exit mpc5125_nfc_cleanup(void)
++{
++	of_unregister_platform_driver(&mpc5125_nfc_driver);
++}
++
++module_init(mpc5125_nfc_init);
++module_exit(mpc5125_nfc_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MPC5125 NAND MTD driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION(DRV_VERSION);
+diff -Naur linux-2.6.29/drivers/mtd/nand/nand_ids.c linux-2.6.29-v2010041601/drivers/mtd/nand/nand_ids.c
+--- linux-2.6.29/drivers/mtd/nand/nand_ids.c	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/mtd/nand/nand_ids.c	2010-04-13 20:23:26.000000000 +0200
+@@ -65,6 +65,7 @@
+ 	{"NAND 128MiB 3,3V 16-bit",	0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
+ 
+ 	{"NAND 256MiB 3,3V 8-bit",	0x71, 512, 256, 0x4000, 0},
++	{"NAND 4GiB 3,3V 8-bit",	0x68, 0x1000, 0x1000, 0x100000, 0x00},
+ 
+ 	/*
+ 	 * These are the new chips with large page size. The pagesize and the
+diff -Naur linux-2.6.29/drivers/net/can/Kconfig linux-2.6.29-v2010041601/drivers/net/can/Kconfig
+--- linux-2.6.29/drivers/net/can/Kconfig	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/net/can/Kconfig	2010-04-13 20:23:26.000000000 +0200
+@@ -22,4 +22,24 @@
+ 	  a problem with CAN support and want to see more of what is going
+ 	  on.
+ 
++config CAN_MSCAN
++	depends on CAN && (PPC || M68K || M68KNOMMU)
++	tristate "Support for a Freescale MSCAN based chips"
++	---help---
++	  The Motorola Scalable Controller Area Network (MSCAN) definition
++	  is based on the MSCAN12 definition which is the specific
++	  implementation of the Motorola Scalable CAN concept targeted for
++	  the Motorola MC68HC12 Microcontroller Family.
++
++config CAN_MPC52XX
++	tristate "Freescale MPC5200/MPC5121 onboard CAN controller"
++	depends on CAN_MSCAN && (PPC_MPC52xx || PPC_52xx || PPC_MPC5121 || PPC_MPC5125)
++	default LITE5200
++	---help---
++	  If you say yes here you get support for Freescale MPC5200/MPC5121
++	  onboard dualCAN controller.
++
++	  This driver can also be built as a module.  If so, the module
++	  will be called mpc52xx_can.
++
+ endmenu
+diff -Naur linux-2.6.29/drivers/net/can/Makefile linux-2.6.29-v2010041601/drivers/net/can/Makefile
+--- linux-2.6.29/drivers/net/can/Makefile	2009-03-24 00:12:14.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/net/can/Makefile	2010-04-13 20:23:26.000000000 +0200
+@@ -3,3 +3,4 @@
+ #
+ 
+ obj-$(CONFIG_CAN_VCAN)		+= vcan.o
++obj-$(CONFIG_CAN_MSCAN)		+= mscan/
+diff -Naur linux-2.6.29/drivers/net/can/mscan/Makefile linux-2.6.29-v2010041601/drivers/net/can/mscan/Makefile
+--- linux-2.6.29/drivers/net/can/mscan/Makefile	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/net/can/mscan/Makefile	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_CAN_MPC52XX)	+= mscan-mpc52xx.o
++mscan-mpc52xx-objs	:= mscan.o mpc52xx_can.o
+diff -Naur linux-2.6.29/drivers/net/can/mscan/mpc52xx_can.c linux-2.6.29-v2010041601/drivers/net/can/mscan/mpc52xx_can.c
+--- linux-2.6.29/drivers/net/can/mscan/mpc52xx_can.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/net/can/mscan/mpc52xx_can.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,337 @@
++/*
++ * DESCRIPTION:
++ *  CAN bus driver for the Freescale MPC52xx embedded CPU.
++ *
++ * AUTHOR:
++ *  Andrey Volkov <avolkov@varma-el.com>
++ *
++ * COPYRIGHT:
++ *  2004-2005, Varma Electronics Oy
++ *
++ * LICENCE:
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ *
++ * HISTORY:
++ * 	 2008-02-26 Add support for MPC512x
++ * 	 		Hongjun, Chen <hong-jun.chen@freescale.com>
++ *	 2005-02-03 created
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/netdevice.h>
++#include <linux/can.h>
++#include <linux/can/dev.h>
++#include <asm/io.h>
++#include <asm/of_platform.h>
++#include <asm/mpc512x.h>
++#include <linux/clk.h>
++#include "mscan.h"
++
++#include <linux/can/version.h>	/* for RCSID. Removed by mkpatch script */
++
++RCSID("$Id$");
++
++#define PDEV_MAX 4
++
++struct platform_device *pdev[PDEV_MAX];
++
++static int __devinit mpc52xx_can_probe(struct platform_device *pdev)
++{
++	struct resource *mem;
++	struct net_device *dev;
++	struct mscan_platform_data *pdata = pdev->dev.platform_data;
++	struct can_priv *can;
++	u32 mem_size;
++	int ret = -ENODEV;
++
++	if (!pdata)
++		return ret;
++	dev = alloc_mscandev();
++	if (!dev)
++		return -ENOMEM;
++	can = netdev_priv(dev);
++
++	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	dev->irq = platform_get_irq(pdev, 0);
++	if (!mem || !dev->irq)
++		goto req_error;
++
++	mem_size = mem->end - mem->start + 1;
++	if (!request_mem_region(mem->start, mem_size, pdev->dev.driver->name)) {
++		dev_err(&pdev->dev, "resource unavailable\n");
++		goto req_error;
++	}
++
++	SET_NETDEV_DEV(dev, &pdev->dev);
++
++	dev->base_addr = (unsigned long)ioremap_nocache(mem->start, mem_size);
++
++	if (!dev->base_addr) {
++		dev_err(&pdev->dev, "failed to map can port\n");
++		ret = -ENOMEM;
++		goto fail_map;
++	}
++
++	if (pdata->cpu_type == MPC512x_MSCAN) {
++		struct clk *mscan_clk, *port_clk;
++		char clk_name[15];
++
++		mscan_clk = clk_get(NULL, "mscan_clk");
++		if (!mscan_clk) {
++			dev_err(&pdev->dev, "can't get mscan clock!");
++			ret = -EINVAL;
++			goto fail_map;
++		}
++
++		sprintf(clk_name, "mscan%d_clk", pdata->port);
++		port_clk = clk_get(NULL, clk_name);
++
++		/* update clock rate for mpc5121e rev2 chip */
++		if (port_clk)
++			pdata->clock_frq = clk_get_rate(port_clk);
++
++		/* enable clock for mscan module */
++		clk_enable(mscan_clk);
++	}
++
++	can->can_sys_clock = pdata->clock_frq;
++
++	platform_set_drvdata(pdev, dev);
++
++	ret = register_mscandev(dev, pdata->clock_src);
++	if (ret >= 0) {
++		dev_info(&pdev->dev, "probe port 0x%lX done, clk rate:%d\n",
++			 dev->base_addr, pdata->clock_frq);
++		return ret;
++	}
++
++	iounmap((unsigned long *)dev->base_addr);
++      fail_map:
++	release_mem_region(mem->start, mem_size);
++      req_error:
++	free_candev(dev);
++	dev_err(&pdev->dev, "probe failed\n");
++	return ret;
++}
++
++static int __devexit mpc52xx_can_remove(struct platform_device *pdev)
++{
++	struct net_device *dev = platform_get_drvdata(pdev);
++	struct resource *mem;
++
++	platform_set_drvdata(pdev, NULL);
++	unregister_mscandev(dev);
++
++	iounmap((volatile void __iomem *)dev->base_addr);
++	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	release_mem_region(mem->start, mem->end - mem->start + 1);
++	free_candev(dev);
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static struct mscan_regs saved_regs;
++static int mpc52xx_can_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct net_device *dev = platform_get_drvdata(pdev);
++	struct mscan_regs *regs = (struct mscan_regs *)dev->base_addr;
++
++	_memcpy_fromio(&saved_regs, regs, sizeof(*regs));
++
++	regs->canctl1 |= MSCAN_CANE;
++	regs->canctl1 &= ~MSCAN_LISTEN;
++	regs->canctl0 |= MSCAN_SLPRQ;
++	regs->canctl0 |= MSCAN_INITRQ;
++	mdelay(20);
++	regs->canctl0 &= ~MSCAN_INITRQ;
++	regs->canctl0 |= MSCAN_WUPE;
++	mdelay(20);
++	regs->canrier |= 0xff;
++
++	return 0;
++}
++
++static int mpc52xx_can_resume(struct platform_device *pdev)
++{
++	struct net_device *dev = platform_get_drvdata(pdev);
++	struct mscan_regs *regs = (struct mscan_regs *)dev->base_addr;
++
++	regs->canctl0 |= MSCAN_INITRQ;
++	while ((regs->canctl1 & MSCAN_INITAK) == 0)
++		udelay(10);
++
++	regs->canctl1 = saved_regs.canctl1;
++	regs->canbtr0 = saved_regs.canbtr0;
++	regs->canbtr1 = saved_regs.canbtr1;
++	regs->canidac = saved_regs.canidac;
++
++	/* restore masks, buffers etc. */
++	_memcpy_toio(&regs->canidar1_0, (void *)&saved_regs.canidar1_0,
++		     sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
++
++	regs->canctl0 &= ~MSCAN_INITRQ;
++	regs->cantbsel = saved_regs.cantbsel;
++	regs->canrier = saved_regs.canrier;
++	regs->cantier = saved_regs.cantier;
++	regs->canctl0 = saved_regs.canctl0;
++
++	regs->canrflg &= 0xc3;
++
++	return 0;
++}
++#endif
++
++static struct platform_driver mpc52xx_can_driver = {
++	.driver = {
++		   .name = "fsl-mscan",
++		   },
++	.probe = mpc52xx_can_probe,
++	.remove = __devexit_p(mpc52xx_can_remove),
++#ifdef CONFIG_PM
++	.suspend = mpc52xx_can_suspend,
++	.resume = mpc52xx_can_resume,
++#endif
++};
++
++#ifdef CONFIG_PPC_MERGE
++unsigned int fsl_find_ipb_freq(struct device_node *node)
++{
++	struct device_node *np;
++	const unsigned int *p_ipb_freq = NULL;
++
++	of_node_get(node);
++	while (node) {
++		p_ipb_freq = of_get_property(node, "bus-frequency", NULL);
++		if (p_ipb_freq)
++			break;
++
++		np = of_get_parent(node);
++		of_node_put(node);
++		node = np;
++	}
++	if (node)
++		of_node_put(node);
++
++	return p_ipb_freq ? *p_ipb_freq : 0;
++}
++
++static int __init mpc52xx_of_to_pdev(void)
++{
++	struct device_node *np = NULL;
++	unsigned int i;
++	int ret, type = -1, index = 0;
++	int *port;
++	char *mscan_comp_name[] = {"fsl,mpc5200-mscan",
++				   "fsl,mpc5121rev2-mscan",
++				   "fsl,mpc5121-mscan"};
++	int  cpu_type[] = {MPC52xx_MSCAN, MPC512x_MSCAN, MPC512x_MSCAN};
++
++	for (i = 0; i < 3; i++) {
++		np = of_find_compatible_node(np, NULL, mscan_comp_name[i]);
++		if (np) {
++			type = cpu_type[i];
++			index = i;
++			of_node_put(np);
++			np = NULL;
++			break;
++		}
++	}
++
++	if (type != cpu_type[0] && type != cpu_type[1]) {
++		printk(KERN_ERR "%s: can't find any CAN devices\n", __func__);
++		return -1;
++	}
++
++	for (i = 0;
++	     (np = of_find_compatible_node(np, NULL,
++					   mscan_comp_name[index]));
++	     i++) {
++		struct resource r[2] = { };
++		struct mscan_platform_data pdata;
++
++		if (i >= PDEV_MAX) {
++			printk(KERN_WARNING "%s: increase PDEV_MAX for more "
++			       "than %i devices\n", __func__, PDEV_MAX);
++			break;
++		}
++
++		ret = of_address_to_resource(np, 0, &r[0]);
++		if (ret)
++			goto err;
++
++		of_irq_to_resource(np, 0, &r[1]);
++
++		pdev[i] =
++		    platform_device_register_simple("fsl-mscan", i, r, 2);
++		if (IS_ERR(pdev[i])) {
++			ret = PTR_ERR(pdev[i]);
++			goto err;
++		}
++
++		pdata.clock_src = MSCAN_CLKSRC_BUS;
++		pdata.cpu_type = type;
++		pdata.clock_frq = fsl_find_ipb_freq(np);
++
++		if (pdata.cpu_type == MPC512x_MSCAN) {
++			port = (int *)of_get_property(np, "cell-index", NULL);
++			if (!port) {
++				printk(KERN_ERR "Err: can't find can port!\n");
++				goto err;
++			}
++			pdata.port = *port;
++		}
++
++		ret = platform_device_add_data(pdev[i], &pdata, sizeof(pdata));
++		if (ret)
++			goto err;
++	}
++	/*can1_tx psc9 pin 0*/
++	mpc5125_io_controller_set(0x4d,0x03);
++	/*can2_tx psc9 pin 1*/
++	mpc5125_io_controller_set(0x4e, 0x03);
++	return 0;
++      err:
++	return ret;
++}
++#else
++#define mscan_of_to_pdev()
++#endif
++
++int __init mpc52xx_can_init(void)
++{
++	mpc52xx_of_to_pdev();
++	printk(KERN_INFO "%s initializing\n", mpc52xx_can_driver.driver.name);
++	return platform_driver_register(&mpc52xx_can_driver);
++}
++
++void __exit mpc52xx_can_exit(void)
++{
++	int i;
++	platform_driver_unregister(&mpc52xx_can_driver);
++	for (i = 0; i < PDEV_MAX; i++)
++		platform_device_unregister(pdev[i]);
++	printk(KERN_INFO "%s unloaded\n", mpc52xx_can_driver.driver.name);
++}
++
++module_init(mpc52xx_can_init);
++module_exit(mpc52xx_can_exit);
++
++MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
++MODULE_DESCRIPTION("Freescale MPC5200/MPC512x CAN driver");
++MODULE_LICENSE("GPL v2");
+diff -Naur linux-2.6.29/drivers/net/can/mscan/mscan.c linux-2.6.29-v2010041601/drivers/net/can/mscan/mscan.c
+--- linux-2.6.29/drivers/net/can/mscan/mscan.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.29-v2010041601/drivers/net/can/mscan/mscan.c	2010-04-13 20:23:26.000000000 +0200
+@@ -0,0 +1,718 @@
++/*
++ * mscan.c
++ *
++ * DESCRIPTION:
++ *  CAN bus driver for the alone generic (as possible as) MSCAN controller.
++ *
++ * AUTHOR:
++ *  Andrey Volkov <avolkov@varma-el.com>
++ *
++ * COPYRIGHT:
++ *  2005-2006, Varma Electronics Oy
++ *
++ * LICENCE:
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/netdevice.h>
++#include <linux/if_arp.h>
++#include <linux/if_ether.h>
++#include <linux/can.h>
++#include <linux/list.h>
++#include <asm/io.h>
++#include <asm/of_platform.h>
++
++#include <linux/can/dev.h>
++#include <linux/can/error.h>
++#include "mscan.h"
++
++#include <linux/can/version.h>	/* for RCSID. Removed by mkpatch script */
++RCSID("$Id$");
++
++#define MSCAN_NORMAL_MODE	0
++#define MSCAN_SLEEP_MODE	MSCAN_SLPRQ
++#define MSCAN_INIT_MODE		(MSCAN_INITRQ | MSCAN_SLPRQ)
++#define MSCAN_POWEROFF_MODE	(MSCAN_CSWAI | MSCAN_SLPRQ)
++#define MSCAN_SET_MODE_RETRIES	1000
++
++
++#define BTR0_BRP_MASK		0x3f
++#define BTR0_SJW_SHIFT		6
++#define BTR0_SJW_MASK		(0x3 << BTR0_SJW_SHIFT)
++
++#define BTR1_TSEG1_MASK 	0xf
++#define BTR1_TSEG2_SHIFT	4
++#define BTR1_TSEG2_MASK 	(0x7 << BTR1_TSEG2_SHIFT)
++#define BTR1_SAM_SHIFT  	7
++
++#define BTR0_SET_BRP(brp)	(((brp) - 1) & BTR0_BRP_MASK)
++#define BTR0_SET_SJW(sjw)	((((sjw) - 1) << BTR0_SJW_SHIFT) & \
++				 BTR0_SJW_MASK)
++
++#define BTR1_SET_TSEG1(tseg1)	(((tseg1) - 1) &  BTR1_TSEG1_MASK)
++#define BTR1_SET_TSEG2(tseg2)	((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \
++				 BTR1_TSEG2_MASK)
++#define BTR1_SET_SAM(sam)	(((sam) & 1) << BTR1_SAM_SHIFT)
++
++struct mscan_state {
++	u8 mode;
++	u8 canrier;
++	u8 cantier;
++};
++
++#define TX_QUEUE_SIZE	3
++
++typedef struct {
++	struct list_head list;
++	u8 mask;
++} tx_queue_entry_t;
++
++struct mscan_priv {
++	struct can_priv can;
++	struct napi_struct napi;
++	struct net_device *netdev;
++	volatile unsigned long flags;
++	u8 shadow_statflg;
++	u8 shadow_canrier;
++	u8 cur_pri;
++	u8 tx_active;
++
++	struct list_head tx_head;
++	tx_queue_entry_t tx_queue[TX_QUEUE_SIZE];
++};
++
++#define F_RX_PROGRESS	0
++#define F_TX_PROGRESS	1
++#define F_TX_WAIT_ALL	2
++
++static int mscan_set_mode(struct net_device *dev, u8 mode)
++{
++	struct mscan_regs *regs = (struct mscan_regs *)dev->base_addr;
++	struct mscan_priv *priv = netdev_priv(dev);
++	int ret = 0;
++	int i;
++	u8 canctl1;
++
++	if (mode != MSCAN_NORMAL_MODE) {
++		if (priv->tx_active) {
++			/* Abort transfers before going to sleep */
++			out_8(&regs->cantarq, priv->tx_active);
++			/* Suppress TX done interrupts */
++			out_8(&regs->cantier, 0);
++		}
++		canctl1 = in_8(&regs->canctl1);
++		if ((mode & MSCAN_SLPRQ) && (canctl1 & MSCAN_SLPAK) == 0) {
++			out_8(&regs->canctl0,in_8(&regs->canctl0) | MSCAN_SLPRQ);
++			for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
++				out_8(&regs->canctl0,in_8(&regs->canctl0) | MSCAN_SLPRQ);
++				if (in_8(&regs->canctl1) & MSCAN_SLPAK)
++					break;
++				udelay(100);
++			}
++			if (i >= MSCAN_SET_MODE_RETRIES)
++				ret = -ENODEV;
++		}
++		if (!ret && (mode & MSCAN_INITRQ)
++		    && (canctl1 & MSCAN_INITAK) == 0) {
++			out_8(&regs->canctl0,
++			      in_8(&regs->canctl0) | MSCAN_INITRQ);
++			for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
++				out_8(&regs->canctl0,
++					in_8(&regs->canctl0) | MSCAN_INITRQ);
++				if (in_8(&regs->canctl1) & MSCAN_INITAK)
++					break;
++			}
++			if (i >= MSCAN_SET_MODE_RETRIES)
++				ret = -ENODEV;
++		}
++		if (!ret && (mode & MSCAN_CSWAI))
++			out_8(&regs->canctl0,
++			      in_8(&regs->canctl0) | MSCAN_CSWAI);
++
++	} else {
++		canctl1 = in_8(&regs->canctl1);
++		if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) {
++			out_8(&regs->canctl0, in_8(&regs->canctl0) &
++			      ~(MSCAN_SLPRQ | MSCAN_INITRQ));
++			for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
++				out_8(&regs->canctl0, in_8(&regs->canctl0) &
++					 ~(MSCAN_SLPRQ | MSCAN_INITRQ));
++				canctl1 = in_8(&regs->canctl1);
++				if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK)))
++					break;
++			}
++			if (i >= MSCAN_SET_MODE_RETRIES)
++				ret = -ENODEV;
++		}
++	}
++	return ret;
++}
++
++static void mscan_push_state(struct net_device *dev, struct mscan_state *state)
++{
++	struct mscan_regs *regs = (struct mscan_regs *)dev->base_addr;
++
++	state->mode = in_8(&regs->canctl0) & (MSCAN_SLPRQ | MSCAN_INITRQ |
++					      MSCAN_CSWAI);
++	state->canrier = in_8(&regs->canrier);
++	state->cantier = in_8(&regs->cantier);
++}
++
++static int mscan_pop_state(struct net_device *dev, struct mscan_state *state)
++{
++	struct mscan_regs *regs = (struct mscan_regs *)dev->base_addr;
++
++	int ret;
++	ret = mscan_set_mode(dev, state->mode);
++	if (!ret) {
++		out_8(&regs->canrier, state->canrier);
++		out_8(&regs->cantier, state->cantier);
++	}
++	return ret;
++}
++
++static int mscan_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++	struct can_frame *frame = (struct can_frame *)skb->data;
++	struct mscan_regs *regs = (struct mscan_regs *)dev->base_addr;
++	struct mscan_priv *priv = netdev_priv(dev);
++
++	int i, rtr, buf_id;
++	u32 can_id;
++
++	if (frame->can_dlc > 8)
++		return -EINVAL;
++
++	dev_dbg(ND2D(dev), "%s\n", __FUNCTION__);
++	out_8(&regs->cantier, 0);
++
++	i = ~priv->tx_active & MSCAN_TXE;
++	buf_id = ffs(i) - 1;
++	switch (hweight8(i)) {
++	case 0:</