deleted file mode 100644
@@ -1,450 +0,0 @@
-From f05911e053a51d9a5aa0c8632b442354a7486f45 Mon Sep 17 00:00:00 2001
-From: Matthieu Crapet <mcrapet@gmail.com>
-Date: Thu, 10 Jun 2010 10:43:24 +0200
-Subject: [PATCH 01/24] ts72xx_base
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-- patch: allow to force nF bit in control reg
-- register pwm1
-
-Signed-off-by: Petr Štetiar <ynezz@true.cz>
----
- arch/arm/Kconfig | 3 +
- arch/arm/mach-ep93xx/Kconfig | 9 ++
- arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h | 7 +
- arch/arm/mach-ep93xx/include/mach/memory.h | 28 +++++
- arch/arm/mach-ep93xx/include/mach/ts72xx.h | 145 +++++++++++++++++++++--
- arch/arm/mach-ep93xx/ts72xx.c | 41 ++++++-
- arch/arm/mm/proc-arm920.S | 5 +-
- scripts/Makefile.fwinst | 2 +-
- 8 files changed, 223 insertions(+), 17 deletions(-)
-
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index 9c26ba7..8e6c85d 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -327,6 +327,9 @@ config ARCH_EP93XX
- select CPU_ARM920T
- select ARM_AMBA
- select ARM_VIC
-+ select ARCH_SPARSEMEM_ENABLE
-+ select GENERIC_GPIO
-+ select HAVE_CLK
- select COMMON_CLKDEV
- select ARCH_REQUIRE_GPIOLIB
- select ARCH_HAS_HOLES_MEMORYMODEL
-diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
-index 3a08b18..b6be37e 100644
---- a/arch/arm/mach-ep93xx/Kconfig
-+++ b/arch/arm/mach-ep93xx/Kconfig
-@@ -7,6 +7,15 @@ config CRUNCH
- help
- Enable kernel support for MaverickCrunch.
-
-+config CR1_NFBIT
-+ bool "Turn on nF bit in ControlRegister 1"
-+ help
-+ Say 'Y' here to force the nF bit on. Usually this is set
-+ by the bootrom. If it is not set, then the CPU core will
-+ run from HCLK instead of FCLK, and performance will suffer.
-+ If you see BogoMIPS of about 1/4 of your CPU clock, try
-+ turning this on; your performance should double.
-+
- comment "EP93xx Platforms"
-
- choice
-diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
-index c54b3e5..db351cc 100644
---- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
-+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
-@@ -83,6 +83,7 @@
-
- #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
-
-+#define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000)
- #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
-
- #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
-@@ -97,12 +98,17 @@
- #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
-
- #define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
-+#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
-+#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
-
- #define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
- #define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
- #define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
-+#define EP93XX_GPIO_F_INT_DEBOUNCE EP93XX_GPIO_REG(0x64)
- #define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0)
-+#define EP93XX_GPIO_A_INT_DEBOUNCE EP93XX_GPIO_REG(0xa8)
- #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
-+#define EP93XX_GPIO_B_INT_DEBOUNCE EP93XX_GPIO_REG(0xc4)
- #define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8)
-
- #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
-@@ -220,6 +226,7 @@
- #define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
- #define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
- #define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
-+#define EP93XX_SYSCON_CHIPID EP93XX_SYSCON_REG(0x94)
- #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
-
- #define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
-diff --git a/arch/arm/mach-ep93xx/include/mach/memory.h b/arch/arm/mach-ep93xx/include/mach/memory.h
-index 554064e..78eaacf 100644
---- a/arch/arm/mach-ep93xx/include/mach/memory.h
-+++ b/arch/arm/mach-ep93xx/include/mach/memory.h
-@@ -19,4 +19,32 @@
- #error "Kconfig bug: No EP93xx PHYS_OFFSET set"
- #endif
-
-+/*
-+ * Non-linear mapping like so:
-+ * phys => virt
-+ * 0x00000000 => 0xc0000000
-+ * 0x01000000 => 0xc1000000
-+ * 0x04000000 => 0xc4000000
-+ * 0x05000000 => 0xc5000000
-+ * 0xe0000000 => 0xc8000000
-+ * 0xe1000000 => 0xc9000000
-+ * 0xe4000000 => 0xcc000000
-+ * 0xe5000000 => 0xcd000000
-+ *
-+ * As suggested here: http://marc.info/?l=linux-arm&m=122754446724900&w=2
-+ *
-+ * Note that static inline functions won't work here because
-+ * arch/arm/include/asm/memory.h uses "#ifndef __virt_to_phys" to check whether to
-+ * use generic functions or not.
-+ */
-+
-+#define __phys_to_virt(p) \
-+ (((p) & 0x07ffffff) | (((p) & 0xe0000000) ? 0x08000000 : 0) | PAGE_OFFSET)
-+
-+#define __virt_to_phys(v) \
-+ (((v) & 0x07ffffff) | (((v) & 0x08000000) ? 0xe0000000 : 0 ))
-+
-+#define SECTION_SIZE_BITS 24
-+#define MAX_PHYSMEM_BITS 32
-+
- #endif
-diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
-index 0eabec6..1d50dec 100644
---- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
-+++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
-@@ -8,36 +8,41 @@
- * virt phys size
- * febff000 22000000 4K model number register
- * febfe000 22400000 4K options register
-- * febfd000 22800000 4K options register #2
-+ * febfd000 22800000 4K options register #2 (JP6 and TS-9420 flags)
-+ * febfc000 [67]0000000 4K NAND data register
-+ * febfb000 [67]0400000 4K NAND control register
-+ * febfa000 [67]0800000 4K NAND busy register
- * febf9000 10800000 4K TS-5620 RTC index register
- * febf8000 11700000 4K TS-5620 RTC data register
-+ * febf7000 23400000 4K PLD version (3 bits)
-+ * febf6000 22c00000 4K RS-485 control register
-+ * febf5000 23000000 4K RS-485 mode register
- */
-
- #define TS72XX_MODEL_PHYS_BASE 0x22000000
- #define TS72XX_MODEL_VIRT_BASE 0xfebff000
- #define TS72XX_MODEL_SIZE 0x00001000
-
--#define TS72XX_MODEL_TS7200 0x00
--#define TS72XX_MODEL_TS7250 0x01
--#define TS72XX_MODEL_TS7260 0x02
-+#define TS7XXX_MODEL_TS7200 0x00
-+#define TS7XXX_MODEL_TS7250 0x01
-+#define TS7XXX_MODEL_TS7260 0x02
-+#define TS7XXX_MODEL_TS7300 0x03
-+#define TS7XXX_MODEL_TS7400 0x04
-+#define TS7XXX_MODEL_MASK 0x07
-
-
- #define TS72XX_OPTIONS_PHYS_BASE 0x22400000
- #define TS72XX_OPTIONS_VIRT_BASE 0xfebfe000
- #define TS72XX_OPTIONS_SIZE 0x00001000
--
- #define TS72XX_OPTIONS_COM2_RS485 0x02
- #define TS72XX_OPTIONS_MAX197 0x01
-
--
- #define TS72XX_OPTIONS2_PHYS_BASE 0x22800000
- #define TS72XX_OPTIONS2_VIRT_BASE 0xfebfd000
- #define TS72XX_OPTIONS2_SIZE 0x00001000
--
- #define TS72XX_OPTIONS2_TS9420 0x04
- #define TS72XX_OPTIONS2_TS9420_BOOT 0x02
-
--
- #define TS72XX_RTC_INDEX_VIRT_BASE 0xfebf9000
- #define TS72XX_RTC_INDEX_PHYS_BASE 0x10800000
- #define TS72XX_RTC_INDEX_SIZE 0x00001000
-@@ -49,32 +54,146 @@
- #define TS72XX_WDT_CONTROL_PHYS_BASE 0x23800000
- #define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000
-
-+#define TS72XX_PLD_VERSION_VIRT_BASE 0xfebf7000
-+#define TS72XX_PLD_VERSION_PHYS_BASE 0x23400000
-+#define TS72XX_PLD_VERSION_SIZE 0x00001000
-+
-+#define TS72XX_JUMPERS_MAX197_PHYS_BASE 0x10800000 // jumpers/max197 busy bit/COM1 dcd register (8-bit, read only)
-+#define TS72XX_MAX197_SAMPLE_PHYS_BASE 0x10f00000 // max197 sample/control register (16-bit read/8-bit write)
-+
-+/*
-+ * RS485 option
-+ */
-+#define TS72XX_RS485_CONTROL_VIRT_BASE 0xfebf6000
-+#define TS72XX_RS485_CONTROL_PHYS_BASE 0x22c00000
-+#define TS72XX_RS485_CONTROL_SIZE 0x00001000
-+
-+#define TS72XX_RS485_MODE_VIRT_BASE 0xfebf5000
-+#define TS72XX_RS485_MODE_PHYS_BASE 0x23000000
-+#define TS72XX_RS485_MODE_SIZE 0x00001000
-+
-+#define TS72XX_RS485_AUTO485FD 1
-+#define TS72XX_RS485_AUTO485HD 2
-+#define TS72XX_RS485_MODE_RS232 0x00
-+#define TS72XX_RS485_MODE_FD 0x01
-+#define TS72XX_RS485_MODE_9600_HD 0x04
-+#define TS72XX_RS485_MODE_19200_HD 0x05
-+#define TS72XX_RS485_MODE_57600_HD 0x06
-+#define TS72XX_RS485_MODE_115200_HD 0x07
-+
-+/*
-+ * PC/104 8-bit & 16-bit bus
-+ *
-+ * virt phys size
-+ * febf0000 11e00000 4K PC/104 8-bit I/O
-+ * febef000 21e00000 4K PC/104 16-bit I/O
-+ * fea00000 11a00000 1MB PC/104 8-bit memory
-+ * fe900000 21a00000 1MB PC/104 16-bit memory
-+ */
-+#define TS72XX_PC104_8BIT_IO_VIRT_BASE 0xfebf0000
-+#define TS72XX_PC104_8BIT_IO_PHYS_BASE 0x11e00000
-+#define TS72XX_PC104_8BIT_IO_SIZE 0x00001000
-+#define TS72XX_PC104_8BIT_MEM_VIRT_BASE 0xfea00000
-+#define TS72XX_PC104_8BIT_MEM_PHYS_BASE 0x11a00000
-+#define TS72XX_PC104_8BIT_MEM_SIZE 0x00100000
-+
-+#define TS72XX_PC104_16BIT_IO_VIRT_BASE 0xfebef000
-+#define TS72XX_PC104_16BIT_IO_PHYS_BASE 0x21e00000
-+#define TS72XX_PC104_16BIT_IO_SIZE 0x00001000
-+#define TS72XX_PC104_16BIT_MEM_VIRT_BASE 0xfe900000
-+#define TS72XX_PC104_16BIT_MEM_PHYS_BASE 0x21a00000
-+#define TS72XX_PC104_16BIT_MEM_SIZE 0x00100000
-+
-+/*
-+ * TS7200 specific : CompactFlash memory map
-+ *
-+ * phys size description
-+ * 11000000 7 CF registers (8-bit each), starting at 11000001
-+ * 10400006 2 CF aux registers (8-bit)
-+ * 21000000 2 CF data register (16-bit)
-+ */
-+#define TS7200_CF_CMD_PHYS_BASE 0x11000000
-+#define TS7200_CF_AUX_PHYS_BASE 0x10400006
-+#define TS7200_CF_DATA_PHYS_BASE 0x21000000
-+
-+/*
-+ * TS7260 specific : SD card & Power Management
-+ *
-+ * phys size description
-+ * 12000000 4K Power management register (8-bit)
-+ * 13000000 4K SD card registers (4 x 8-bit)
-+ */
-+#define TS7260_POWER_MANAGEMENT_PHYS_BASE 0x12000000
-+#define TS7260_PM_RS232_LEVEL_CONVERTER 0x01
-+#define TS7260_PM_USB 0x02
-+#define TS7260_PM_LCD 0x04
-+#define TS7260_PM_5V_SWITCHER 0x08
-+#define TS7260_PM_PC104_CLOCK 0x10
-+#define TS7260_PM_PC104_FAST_STROBES 0x20
-+#define TS7260_PM_TTL_UART_ENABLE 0x40
-+#define TS7260_PM_SCRATCH_BIT 0x80
-+
-+#define TS7260_SDCARD_PHYS_BASE 0x13000000
-+
- #ifndef __ASSEMBLY__
-
- static inline int board_is_ts7200(void)
- {
-- return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200;
-+ return (__raw_readb(TS72XX_MODEL_VIRT_BASE) &
-+ TS7XXX_MODEL_MASK) == TS7XXX_MODEL_TS7200;
- }
-
- static inline int board_is_ts7250(void)
- {
-- return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250;
-+ return (__raw_readb(TS72XX_MODEL_VIRT_BASE) &
-+ TS7XXX_MODEL_MASK) == TS7XXX_MODEL_TS7250;
- }
-
- static inline int board_is_ts7260(void)
- {
-- return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260;
-+ return (__raw_readb(TS72XX_MODEL_VIRT_BASE) &
-+ TS7XXX_MODEL_MASK) == TS7XXX_MODEL_TS7260;
-+}
-+
-+static inline int board_is_ts7300(void)
-+{
-+ return (__raw_readb(TS72XX_MODEL_VIRT_BASE) &
-+ TS7XXX_MODEL_MASK) == TS7XXX_MODEL_TS7300;
-+}
-+
-+static inline int board_is_ts7400(void)
-+{
-+ return (__raw_readb(TS72XX_MODEL_VIRT_BASE) &
-+ TS7XXX_MODEL_MASK) == TS7XXX_MODEL_TS7400;
- }
-
- static inline int is_max197_installed(void)
- {
- return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) &
-- TS72XX_OPTIONS_MAX197);
-+ TS72XX_OPTIONS_MAX197);
- }
-
- static inline int is_ts9420_installed(void)
- {
- return !!(__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) &
-- TS72XX_OPTIONS2_TS9420);
-+ TS72XX_OPTIONS2_TS9420);
- }
-+
-+static inline int is_rs485_installed(void)
-+{
-+ return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) &
-+ TS72XX_OPTIONS_COM2_RS485);
-+}
-+
-+static inline int get_ts72xx_pld_version(void)
-+{
-+ return (__raw_readb(TS72XX_PLD_VERSION_VIRT_BASE) & 0x7);
-+}
-+
-+/* User jumper */
-+static inline int is_jp6_set(void)
-+{
-+ return (__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) & 0x1);
-+}
-+
- #endif
-diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
-index 93aeab8..345ce18 100644
---- a/arch/arm/mach-ep93xx/ts72xx.c
-+++ b/arch/arm/mach-ep93xx/ts72xx.c
-@@ -54,7 +54,36 @@ static struct map_desc ts72xx_io_desc[] __initdata = {
- .pfn = __phys_to_pfn(TS72XX_RTC_DATA_PHYS_BASE),
- .length = TS72XX_RTC_DATA_SIZE,
- .type = MT_DEVICE,
-- }
-+ },
-+ /* Use this for debug only. Each device will map its own PC/104 address space */
-+ ///* PC/104 (8-bit) I/O bus */
-+ //{
-+ // .virtual = TS72XX_PC104_8BIT_IO_VIRT_BASE,
-+ // .pfn = __phys_to_pfn(TS72XX_PC104_8BIT_IO_PHYS_BASE),
-+ // .length = TS72XX_PC104_8BIT_IO_SIZE,
-+ // .type = MT_DEVICE,
-+ //},
-+ ///* PC/104 (16-bit) I/O bus */
-+ //{
-+ // .virtual = TS72XX_PC104_16BIT_IO_VIRT_BASE,
-+ // .pfn = __phys_to_pfn(TS72XX_PC104_16BIT_IO_PHYS_BASE),
-+ // .length = TS72XX_PC104_16BIT_IO_SIZE,
-+ // .type = MT_DEVICE,
-+ //},
-+ ///* PC/104 (8-bit) MEM bus */
-+ //{
-+ // .virtual = TS72XX_PC104_8BIT_MEM_VIRT_BASE,
-+ // .pfn = __phys_to_pfn(TS72XX_PC104_8BIT_MEM_PHYS_BASE),
-+ // .length = TS72XX_PC104_8BIT_MEM_SIZE,
-+ // .type = MT_DEVICE,
-+ //},
-+ ///* PC/104 (16-bit) MEM bus */
-+ //{
-+ // .virtual = TS72XX_PC104_16BIT_MEM_VIRT_BASE,
-+ // .pfn = __phys_to_pfn(TS72XX_PC104_16BIT_MEM_PHYS_BASE),
-+ // .length = TS72XX_PC104_16BIT_MEM_SIZE,
-+ // .type = MT_DEVICE,
-+ //}
- };
-
- static void __init ts72xx_map_io(void)
-@@ -194,7 +223,9 @@ static void __init ts72xx_register_flash(void)
- }
- }
-
--
-+/*************************************************************************
-+ * RTC
-+ *************************************************************************/
- static unsigned char ts72xx_rtc_readbyte(unsigned long addr)
- {
- __raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE);
-@@ -242,6 +273,9 @@ static struct platform_device ts72xx_wdt_device = {
- };
-
- static struct ep93xx_eth_data __initdata ts72xx_eth_data = {
-+/*************************************************************************
-+ * Ethernet
-+ *************************************************************************/
- .phy_id = 1,
- };
-
-@@ -253,6 +287,9 @@ static void __init ts72xx_init_machine(void)
- platform_device_register(&ts72xx_wdt_device);
-
- ep93xx_register_eth(&ts72xx_eth_data, 1);
-+
-+ /* PWM1 is DIO_6 on TS-72xx header */
-+ ep93xx_register_pwm(0, 1);
- }
-
- MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
-diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
-index 86f80aa..11ea759 100644
---- a/arch/arm/mm/proc-arm920.S
-+++ b/arch/arm/mm/proc-arm920.S
-@@ -190,7 +190,7 @@ ENTRY(arm920_coherent_kern_range)
- */
- ENTRY(arm920_coherent_user_range)
- bic r0, r0, #CACHE_DLINESIZE - 1
--1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
-+1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
- mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
- add r0, r0, #CACHE_DLINESIZE
- cmp r0, r1
-@@ -390,6 +390,9 @@ __arm920_setup:
- mrc p15, 0, r0, c1, c0 @ get control register v4
- bic r0, r0, r5
- orr r0, r0, r6
-+#ifdef CONFIG_CR1_NFBIT
-+ orr r0, r0, #0x40000000 @ set nF
-+#endif
- mov pc, lr
- .size __arm920_setup, . - __arm920_setup
-
-diff --git a/scripts/Makefile.fwinst b/scripts/Makefile.fwinst
-index 6bf8e87..fb20532 100644
---- a/scripts/Makefile.fwinst
-+++ b/scripts/Makefile.fwinst
-@@ -37,7 +37,7 @@ install-all-dirs: $(installed-fw-dirs)
- @true
-
- quiet_cmd_install = INSTALL $(subst $(srctree)/,,$@)
-- cmd_install = $(INSTALL) -m0644 $< $@
-+ cmd_install = $(INSTALL) -m 0644 $< $@
-
- $(installed-fw-dirs):
- $(call cmd,mkdir)
-1.7.0.4
-
deleted file mode 100644
@@ -1,49 +0,0 @@
-From 841896f3124d3493f5bb1b98370a1d5fcdcaedb4 Mon Sep 17 00:00:00 2001
-From: Matthieu Crapet <mcrapet@gmail.com>
-Date: Thu, 10 Jun 2010 10:51:39 +0200
-Subject: [PATCH 02/24] ts72xx_force_machine-id
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Petr Štetiar <ynezz@true.cz>
----
- arch/arm/kernel/head.S | 3 +++
- arch/arm/mach-ep93xx/Kconfig | 7 +++++++
- 2 files changed, 10 insertions(+), 0 deletions(-)
-
-diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
-index eb62bf9..543eccf 100644
---- a/arch/arm/kernel/head.S
-+++ b/arch/arm/kernel/head.S
-@@ -82,6 +82,9 @@ ENTRY(stext)
- bl __lookup_processor_type @ r5=procinfo r9=cpuid
- movs r10, r5 @ invalid processor (r5=0)?
- beq __error_p @ yes, error 'p'
-+#ifdef CONFIG_MACH_TS72XX_FORCE_MACHINEID
-+ ldr r1, =0x2a1
-+#endif
- bl __lookup_machine_type @ r5=machinfo
- movs r8, r5 @ invalid machine (r5=0)?
- beq __error_a @ yes, error 'a'
-diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
-index b6be37e..bd463a0 100644
---- a/arch/arm/mach-ep93xx/Kconfig
-+++ b/arch/arm/mach-ep93xx/Kconfig
-@@ -205,6 +205,13 @@ config EP93XX_EARLY_UART3
-
- endchoice
-
-+config MACH_TS72XX_FORCE_MACHINEID
-+ bool "Force Machine ID"
-+ depends on MACH_TS72XX
-+ help
-+ Say 'Y' here to force Machine ID to 0x2A1 (MACH_TYPE_TS72XX legacy value)
-+ In early days Technologic Systems fixed the 0x163 value in redboot.
-+
- endmenu
-
- endif
-1.7.0.4
-
deleted file mode 100644
@@ -1,36 +0,0 @@
-From 31727a8a72dc85dc4dc0eeeb27f7f9313c74914b Mon Sep 17 00:00:00 2001
-From: Matthieu Crapet <mcrapet@gmail.com>
-Date: Thu, 10 Jun 2010 10:59:31 +0200
-Subject: [PATCH 03/24] ep93xx_cpuinfo
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Petr Štetiar <ynezz@true.cz>
----
- arch/arm/kernel/setup.c | 9 +++++++++
- 1 files changed, 9 insertions(+), 0 deletions(-)
-
-diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
-index d5231ae..a47ad88 100644
---- a/arch/arm/kernel/setup.c
-+++ b/arch/arm/kernel/setup.c
-@@ -953,6 +953,15 @@ static int c_show(struct seq_file *m, void *v)
- seq_puts(m, "\n");
-
- seq_printf(m, "Hardware\t: %s\n", machine_name);
-+
-+ #if defined(CONFIG_ARCH_EP93XX)
-+ #include <mach/io.h>
-+ #include <mach/ep93xx-regs.h>
-+ system_rev = *((unsigned int *)EP93XX_SYSCON_CHIPID) >> 28;
-+ system_serial_low = *((unsigned int *)EP93XX_SECURITY_UNIQID);
-+ system_serial_high = 0;
-+ #endif
-+
- seq_printf(m, "Revision\t: %04x\n", system_rev);
- seq_printf(m, "Serial\t\t: %08x%08x\n",
- system_serial_high, system_serial_low);
-1.7.0.4
-
deleted file mode 100644
@@ -1,555 +0,0 @@
-From 802fa6d7ec0d57684912b39f0fb0341698cda4e3 Mon Sep 17 00:00:00 2001
-From: Matthieu Crapet <mcrapet@gmail.com>
-Date: Thu, 10 Jun 2010 13:34:14 +0200
-Subject: [PATCH 04/24] ep93xx_eth
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Petr Štetiar <ynezz@true.cz>
----
- drivers/net/arm/Kconfig | 1 +
- drivers/net/arm/ep93xx_eth.c | 346 ++++++++++++++++++++++++++++++++++--------
- 2 files changed, 280 insertions(+), 67 deletions(-)
-
-diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
-index 39e1c0d..55c0dd4 100644
---- a/drivers/net/arm/Kconfig
-+++ b/drivers/net/arm/Kconfig
-@@ -52,6 +52,7 @@ config EP93XX_ETH
- tristate "EP93xx Ethernet support"
- depends on ARM && ARCH_EP93XX
- select MII
-+ select PHYLIB
- help
- This is a driver for the ethernet hardware included in EP93xx CPUs.
- Say Y if you are building a kernel for EP93xx based devices.
-diff --git a/drivers/net/arm/ep93xx_eth.c b/drivers/net/arm/ep93xx_eth.c
-index 4a5ec94..7e60c4d 100644
---- a/drivers/net/arm/ep93xx_eth.c
-+++ b/drivers/net/arm/ep93xx_eth.c
-@@ -2,6 +2,7 @@
- * EP93xx ethernet network device driver
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- * Dedicated to Marija Kulikova.
-+ * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
-@@ -16,6 +17,7 @@
- #include <linux/kernel.h>
- #include <linux/netdevice.h>
- #include <linux/mii.h>
-+#include <linux/phy.h>
- #include <linux/etherdevice.h>
- #include <linux/ethtool.h>
- #include <linux/init.h>
-@@ -27,8 +29,8 @@
-
- #include <mach/hardware.h>
-
--#define DRV_MODULE_NAME "ep93xx-eth"
--#define DRV_MODULE_VERSION "0.1"
-+#define DRV_NAME "ep93xx-eth"
-+#define DRV_VERSION "0.13"
-
- #define RX_QUEUE_ENTRIES 64
- #define TX_QUEUE_ENTRIES 8
-@@ -40,6 +42,8 @@
- #define REG_RXCTL_DEFAULT 0x00073800
- #define REG_TXCTL 0x0004
- #define REG_TXCTL_ENABLE 0x00000001
-+#define REG_TESTCTL 0x0008
-+#define REG_TESTCTL_MFDX 0x00000040
- #define REG_MIICMD 0x0010
- #define REG_MIICMD_READ 0x00008000
- #define REG_MIICMD_WRITE 0x00004000
-@@ -48,6 +52,9 @@
- #define REG_MIISTS_BUSY 0x00000001
- #define REG_SELFCTL 0x0020
- #define REG_SELFCTL_RESET 0x00000001
-+#define REG_SELFCTL_MDCDIV_MSK 0x00007e00
-+#define REG_SELFCTL_MDCDIV_OFS 9
-+#define REG_SELFCTL_PSPRS 0x00000100
- #define REG_INTEN 0x0024
- #define REG_INTEN_TX 0x00000008
- #define REG_INTEN_RX 0x00000007
-@@ -177,8 +184,14 @@ struct ep93xx_priv
-
- struct net_device_stats stats;
-
-- struct mii_if_info mii;
- u8 mdc_divisor;
-+ int phy_supports_mfps:1;
-+
-+ struct mii_bus mii_bus;
-+ struct phy_device *phy_dev;
-+ int speed;
-+ int duplex;
-+ int link;
- };
-
- #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
-@@ -188,46 +201,78 @@ struct ep93xx_priv
- #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
- #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
-
--static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
-+/* common MII transactions should take < 100 iterations */
-+#define EP93XX_PHY_TIMEOUT 2000
-+
-+static int ep93xx_mdio_wait(struct mii_bus *bus)
- {
-- struct ep93xx_priv *ep = netdev_priv(dev);
-- int data;
-- int i;
-+ struct ep93xx_priv *ep = bus->priv;
-+ unsigned int timeout = EP93XX_PHY_TIMEOUT;
-
-- wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
-+ while ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY)
-+ && timeout--)
-+ cpu_relax();
-
-- for (i = 0; i < 10; i++) {
-- if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
-- break;
-- msleep(1);
-+ if (timeout <= 0) {
-+ dev_err(&bus->dev, "MII operation timed out\n");
-+ return -ETIMEDOUT;
- }
-
-- if (i == 10) {
-- pr_info("mdio read timed out\n");
-- data = 0xffff;
-- } else {
-- data = rdl(ep, REG_MIIDATA);
-- }
-+ return 0;
-+}
-+
-+static int ep93xx_mdio_read(struct mii_bus *bus, int mii_id, int reg)
-+{
-+ struct ep93xx_priv *ep = bus->priv;
-+ u32 selfctl;
-+ u32 data;
-+
-+ if (ep93xx_mdio_wait(bus) < 0)
-+ return -ETIMEDOUT;
-+
-+ selfctl = rdl(ep, REG_SELFCTL);
-
-- return data;
-+ if (ep->phy_supports_mfps)
-+ wrl(ep, REG_SELFCTL, selfctl | REG_SELFCTL_PSPRS);
-+ else
-+ wrl(ep, REG_SELFCTL, selfctl & ~REG_SELFCTL_PSPRS);
-+
-+ wrl(ep, REG_MIICMD, REG_MIICMD_READ | (mii_id << 5) | reg);
-+
-+ if (ep93xx_mdio_wait(bus) < 0)
-+ return -ETIMEDOUT;
-+
-+ data = rdl(ep, REG_MIIDATA);
-+
-+ wrl(ep, REG_SELFCTL, selfctl);
-+
-+ return data;
- }
-
--static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
-+static int ep93xx_mdio_write(struct mii_bus *bus, int mii_id, int reg, u16 data)
- {
-- struct ep93xx_priv *ep = netdev_priv(dev);
-- int i;
-+ struct ep93xx_priv *ep = bus->priv;
-+ u32 selfctl;
-+
-+ if (ep93xx_mdio_wait(bus) < 0)
-+ return -ETIMEDOUT;
-+
-+ selfctl = rdl(ep, REG_SELFCTL);
-+
-+ if (ep->phy_supports_mfps)
-+ wrl(ep, REG_SELFCTL, selfctl | REG_SELFCTL_PSPRS);
-+ else
-+ wrl(ep, REG_SELFCTL, selfctl & ~REG_SELFCTL_PSPRS);
-
- wrl(ep, REG_MIIDATA, data);
-- wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
-+ wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (mii_id << 5) | reg);
-
-- for (i = 0; i < 10; i++) {
-- if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
-- break;
-- msleep(1);
-- }
-+ if (ep93xx_mdio_wait(bus) < 0)
-+ return -ETIMEDOUT;
-
-- if (i == 10)
-- pr_info("mdio write timed out\n");
-+ wrl(ep, REG_SELFCTL, selfctl);
-+
-+ return 0;
- }
-
- static struct net_device_stats *ep93xx_get_stats(struct net_device *dev)
-@@ -557,6 +602,22 @@ err:
- return 1;
- }
-
-+static int ep93xx_mdio_reset(struct mii_bus *bus)
-+{
-+ struct ep93xx_priv *ep = bus->priv;
-+
-+ u32 selfctl = rdl(ep, REG_SELFCTL);
-+
-+ selfctl &= ~(REG_SELFCTL_MDCDIV_MSK | REG_SELFCTL_PSPRS);
-+
-+ selfctl |= (ep->mdc_divisor - 1) << REG_SELFCTL_MDCDIV_OFS;
-+ selfctl |= REG_SELFCTL_PSPRS;
-+
-+ wrl(ep, REG_SELFCTL, selfctl);
-+
-+ return 0;
-+}
-+
- static int ep93xx_start_hw(struct net_device *dev)
- {
- struct ep93xx_priv *ep = netdev_priv(dev);
-@@ -575,11 +636,8 @@ static int ep93xx_start_hw(struct net_device *dev)
- return 1;
- }
-
-- wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
--
-- /* Does the PHY support preamble suppress? */
-- if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
-- wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
-+ /* The reset cleared REG_SELFCTL, so set the MDC divisor again */
-+ ep93xx_mdio_reset(&ep->mii_bus);
-
- /* Receive descriptor ring. */
- addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
-@@ -688,6 +746,8 @@ static int ep93xx_open(struct net_device *dev)
-
- wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
-
-+ phy_start(ep->phy_dev);
-+
- netif_start_queue(dev);
-
- return 0;
-@@ -700,6 +760,9 @@ static int ep93xx_close(struct net_device *dev)
- napi_disable(&ep->napi);
- netif_stop_queue(dev);
-
-+ if (ep->phy_dev)
-+ phy_stop(ep->phy_dev);
-+
- wrl(ep, REG_GIINTMSK, 0);
- free_irq(ep->irq, dev);
- ep93xx_stop_hw(dev);
-@@ -711,47 +774,44 @@ static int ep93xx_close(struct net_device *dev)
- static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
- {
- struct ep93xx_priv *ep = netdev_priv(dev);
-- struct mii_ioctl_data *data = if_mii(ifr);
-
-- return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
-+ return phy_mii_ioctl(ep->phy_dev, ifr, cmd);
- }
-
- static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
- {
-- strcpy(info->driver, DRV_MODULE_NAME);
-- strcpy(info->version, DRV_MODULE_VERSION);
-+ strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
-+ strlcpy(info->version, DRV_VERSION, sizeof(info->version));
-+ strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
- }
-
- static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
- {
- struct ep93xx_priv *ep = netdev_priv(dev);
-- return mii_ethtool_gset(&ep->mii, cmd);
-+ struct phy_device *phydev = ep->phy_dev;
-+
-+ if (!phydev)
-+ return -ENODEV;
-+
-+ return phy_ethtool_gset(phydev, cmd);
- }
-
- static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
- {
- struct ep93xx_priv *ep = netdev_priv(dev);
-- return mii_ethtool_sset(&ep->mii, cmd);
--}
-+ struct phy_device *phydev = ep->phy_dev;
-
--static int ep93xx_nway_reset(struct net_device *dev)
--{
-- struct ep93xx_priv *ep = netdev_priv(dev);
-- return mii_nway_restart(&ep->mii);
--}
-+ if (!phydev)
-+ return -ENODEV;
-
--static u32 ep93xx_get_link(struct net_device *dev)
--{
-- struct ep93xx_priv *ep = netdev_priv(dev);
-- return mii_link_ok(&ep->mii);
-+ return phy_ethtool_sset(phydev, cmd);
- }
-
- static const struct ethtool_ops ep93xx_ethtool_ops = {
- .get_drvinfo = ep93xx_get_drvinfo,
- .get_settings = ep93xx_get_settings,
- .set_settings = ep93xx_set_settings,
-- .nway_reset = ep93xx_nway_reset,
-- .get_link = ep93xx_get_link,
-+ .get_link = ethtool_op_get_link,
- };
-
- static const struct net_device_ops ep93xx_netdev_ops = {
-@@ -813,6 +873,113 @@ static int ep93xx_eth_remove(struct platform_device *pdev)
- return 0;
- }
-
-+static void ep93xx_adjust_link(struct net_device *dev)
-+{
-+ struct ep93xx_priv *ep = netdev_priv(dev);
-+ struct phy_device *phydev = ep->phy_dev;
-+
-+ int status_change = 0;
-+
-+ if (phydev->link) {
-+ if ((ep->speed != phydev->speed) ||
-+ (ep->duplex != phydev->duplex)) {
-+ /* speed and/or duplex state changed */
-+ u32 testctl = rdl(ep, REG_TESTCTL);
-+
-+ if (DUPLEX_FULL == phydev->duplex)
-+ testctl |= REG_TESTCTL_MFDX;
-+ else
-+ testctl &= ~(REG_TESTCTL_MFDX);
-+
-+ wrl(ep, REG_TESTCTL, testctl);
-+
-+ ep->speed = phydev->speed;
-+ ep->duplex = phydev->duplex;
-+ status_change = 1;
-+ }
-+ }
-+
-+ /* test for online/offline link transition */
-+ if (phydev->link != ep->link) {
-+ if (phydev->link) /* link went online */
-+ netif_tx_schedule_all(dev);
-+ else { /* link went offline */
-+ ep->speed = 0;
-+ ep->duplex = -1;
-+ }
-+ ep->link = phydev->link;
-+
-+ status_change = 1;
-+ }
-+
-+ if (status_change)
-+ phy_print_status(phydev);
-+}
-+
-+static int ep93xx_mii_probe(struct net_device *dev, int phy_addr)
-+{
-+ struct ep93xx_priv *ep = netdev_priv(dev);
-+ struct phy_device *phydev = NULL;
-+ int val;
-+
-+ if (phy_addr >= 0 && phy_addr < PHY_MAX_ADDR)
-+ phydev = ep->mii_bus.phy_map[phy_addr];
-+
-+ if (!phydev) {
-+ pr_info("PHY not found at specified address,"
-+ " trying autodetection\n");
-+
-+ /* find the first phy */
-+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
-+ if (ep->mii_bus.phy_map[phy_addr]) {
-+ phydev = ep->mii_bus.phy_map[phy_addr];
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (!phydev) {
-+ pr_err("no PHY found\n");
-+ return -ENODEV;
-+ }
-+
-+ phydev = phy_connect(dev, dev_name(&phydev->dev),
-+ ep93xx_adjust_link, 0, PHY_INTERFACE_MODE_MII);
-+
-+ if (IS_ERR(phydev)) {
-+ pr_err("Could not attach to PHY\n");
-+ return PTR_ERR(phydev);
-+ }
-+
-+ ep->phy_supports_mfps = 0;
-+
-+ val = phy_read(phydev, MII_BMSR);
-+ if (val < 0) {
-+ pr_err("failed to read MII register\n");
-+ return val;
-+ }
-+
-+ if (val & 0x0040) {
-+ pr_info("PHY supports MII frame preamble suppression\n");
-+ ep->phy_supports_mfps = 1;
-+ }
-+
-+ phydev->supported &= PHY_BASIC_FEATURES;
-+
-+ phydev->advertising = phydev->supported;
-+
-+ ep->link = 0;
-+ ep->speed = 0;
-+ ep->duplex = -1;
-+ ep->phy_dev = phydev;
-+
-+ pr_info("attached PHY driver [%s] "
-+ "(mii_bus:phy_addr=%s, irq=%d)\n",
-+ phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
-+
-+ return 0;
-+}
-+
- static int ep93xx_eth_probe(struct platform_device *pdev)
- {
- struct ep93xx_eth_data *data;
-@@ -820,7 +987,7 @@ static int ep93xx_eth_probe(struct platform_device *pdev)
- struct ep93xx_priv *ep;
- struct resource *mem;
- int irq;
-- int err;
-+ int err, i;
-
- if (pdev == NULL)
- return -ENODEV;
-@@ -847,24 +1014,43 @@ static int ep93xx_eth_probe(struct platform_device *pdev)
- if (ep->res == NULL) {
- dev_err(&pdev->dev, "Could not reserve memory region\n");
- err = -ENOMEM;
-- goto err_out;
-+ goto err_out_request_mem_region;
- }
-
- ep->base_addr = ioremap(mem->start, resource_size(mem));
- if (ep->base_addr == NULL) {
- dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
- err = -EIO;
-- goto err_out;
-+ goto err_out_ioremap;
- }
- ep->irq = irq;
-
-- ep->mii.phy_id = data->phy_id;
-- ep->mii.phy_id_mask = 0x1f;
-- ep->mii.reg_num_mask = 0x1f;
-- ep->mii.dev = dev;
-- ep->mii.mdio_read = ep93xx_mdio_read;
-- ep->mii.mdio_write = ep93xx_mdio_write;
-+ /* mdio/mii bus */
-+ ep->mii_bus.state = MDIOBUS_ALLOCATED; /* see mdiobus_alloc */
-+ ep->mii_bus.name = "ep93xx_mii_bus";
-+ snprintf(ep->mii_bus.id, MII_BUS_ID_SIZE, "0");
-+
-+ ep->mii_bus.read = ep93xx_mdio_read;
-+ ep->mii_bus.write = ep93xx_mdio_write;
-+ ep->mii_bus.reset = ep93xx_mdio_reset;
-+
-+ ep->mii_bus.phy_mask = 0;
-+
-+ ep->mii_bus.priv = ep;
-+ ep->mii_bus.dev = dev->dev;
-+
-+ ep->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
-+ if (NULL == ep->mii_bus.irq) {
-+ dev_err(&pdev->dev, "Could not allocate memory\n");
-+ err = -ENOMEM;
-+ goto err_out_mii_bus_irq_kmalloc;
-+ }
-+
-+ for (i = 0; i < PHY_MAX_ADDR; i++)
-+ ep->mii_bus.irq[i] = PHY_POLL;
-+
- ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
-+ ep->phy_supports_mfps = 0; /* probe without preamble suppression */
-
- if (is_zero_ether_addr(dev->dev_addr))
- random_ether_addr(dev->dev_addr);
-@@ -872,14 +1058,39 @@ static int ep93xx_eth_probe(struct platform_device *pdev)
- err = register_netdev(dev);
- if (err) {
- dev_err(&pdev->dev, "Failed to register netdev\n");
-- goto err_out;
-+ goto err_out_register_netdev;
-+ }
-+
-+ err = mdiobus_register(&ep->mii_bus);
-+ if (err) {
-+ dev_err(&dev->dev, "Could not register MII bus\n");
-+ goto err_out_mdiobus_register;
-+ }
-+
-+ err = ep93xx_mii_probe(dev, data->phy_id);
-+ if (err) {
-+ dev_err(&dev->dev, "failed to probe MII bus\n");
-+ goto err_out_mii_probe;
- }
-
-- printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
-- dev->name, ep->irq, dev->dev_addr);
-+ dev_info(&dev->dev, "ep93xx on-chip ethernet, IRQ %d, %pM\n",
-+ ep->irq, dev->dev_addr);
-
- return 0;
-
-+err_out_mii_probe:
-+ mdiobus_unregister(&ep->mii_bus);
-+err_out_mdiobus_register:
-+ unregister_netdev(dev);
-+err_out_register_netdev:
-+ kfree(ep->mii_bus.irq);
-+err_out_mii_bus_irq_kmalloc:
-+ iounmap(ep->base_addr);
-+err_out_ioremap:
-+ release_resource(ep->res);
-+ kfree(ep->res);
-+err_out_request_mem_region:
-+ free_netdev(dev);
- err_out:
- ep93xx_eth_remove(pdev);
- return err;
-@@ -897,7 +1108,6 @@ static struct platform_driver ep93xx_eth_driver = {
-
- static int __init ep93xx_eth_init_module(void)
- {
-- printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n");
- return platform_driver_register(&ep93xx_eth_driver);
- }
-
-@@ -908,5 +1118,7 @@ static void __exit ep93xx_eth_cleanup_module(void)
-
- module_init(ep93xx_eth_init_module);
- module_exit(ep93xx_eth_cleanup_module);
-+
- MODULE_LICENSE("GPL");
--MODULE_ALIAS("platform:ep93xx-eth");
-+MODULE_DESCRIPTION("EP93XX Ethernet driver");
-+MODULE_ALIAS("platform:" DRV_NAME);
-1.7.0.4
-
deleted file mode 100644
@@ -1,886 +0,0 @@
-From 619f5711bc905176dc23de3e646686bee36f1601 Mon Sep 17 00:00:00 2001
-From: Matthieu Crapet <mcrapet@gmail.com>
-Date: Thu, 10 Jun 2010 16:40:16 +0200
-Subject: [PATCH 05/24] ep93xx: m2m DMA support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Petr Štetiar <ynezz@true.cz>
----
- arch/arm/mach-ep93xx/Makefile | 2 +-
- arch/arm/mach-ep93xx/dma-m2m.c | 753 +++++++++++++++++++++++++++++++
- arch/arm/mach-ep93xx/include/mach/dma.h | 65 +++
- 3 files changed, 819 insertions(+), 1 deletions(-)
- create mode 100644 arch/arm/mach-ep93xx/dma-m2m.c
-
-diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
-index 33ee2c8..ea652c2 100644
---- a/arch/arm/mach-ep93xx/Makefile
-+++ b/arch/arm/mach-ep93xx/Makefile
-@@ -1,7 +1,7 @@
- #
- # Makefile for the linux kernel.
- #
--obj-y := core.o clock.o dma-m2p.o gpio.o
-+obj-y := core.o clock.o dma-m2p.o dma-m2m.o gpio.o
- obj-m :=
- obj-n :=
- obj- :=
-diff --git a/arch/arm/mach-ep93xx/dma-m2m.c b/arch/arm/mach-ep93xx/dma-m2m.c
-new file mode 100644
-index 0000000..8b0d720
---- /dev/null
-+++ b/arch/arm/mach-ep93xx/dma-m2m.c
-@@ -0,0 +1,753 @@
-+/*
-+ * arch/arm/mach-ep93xx/dma-m2m.c
-+ * M2M DMA handling for Cirrus EP93xx chips.
-+ * Copyright (C) 2007 Metasoft <prylowski@xxxxxxxxxxx>
-+ *
-+ * Based on dma-m2p.c by:
-+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@xxxxxxxxxxxxxx>
-+ * Copyright (C) 2006 Applied Data Systems
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or (at
-+ * your option) any later version.
-+ */
-+
-+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
-+
-+#include <linux/kernel.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/string.h>
-+#include <linux/io.h>
-+
-+#include <mach/dma.h>
-+#include <mach/hardware.h>
-+
-+/* TEMP */
-+#define DPRINTK(fmt, args...)
-+
-+#define M2M_CONTROL 0x00
-+#define M2M_INTERRUPT 0x04
-+#define M2M_STATUS 0x0c
-+#define M2M_BCR0 0x10
-+#define M2M_BCR1 0x14
-+#define M2M_SAR_BASE0 0x18
-+#define M2M_SAR_BASE1 0x1c
-+#define M2M_SAR_CURR0 0x24
-+#define M2M_SAR_CURR1 0x28
-+#define M2M_DAR_BASE0 0x2c
-+#define M2M_DAR_BASE1 0x30
-+#define M2M_DAR_CURR0 0x34
-+#define M2M_DAR_CURR1 0x3c
-+
-+
-+/* control register bits */
-+#define CTRL_STALL_INT_EN 0x00000001 /* stall interrupt enable */
-+#define CTRL_SCT 0x00000002 /* source copy transfer
-+ (1 elem. from source fills
-+ destination block */
-+#define CTRL_DONE_INT_EN 0x00000004 /* done interrupt enable */
-+#define CTRL_ENABLE 0x00000008 /* channel enable / disable,
-+ should be set after
-+ write to SAR/DAR/BCR
-+ registers */
-+#define CTRL_NFB_INT_EN 0x00200000 /* nfb (next frame buffer)
-+ interrupt enable */
-+
-+
-+#define CTRL_START 0x00000010 /* software triggered
-+ dma start, not used
-+ for M2P/P2M/IDE/SSP */
-+#define CTRL_BWC_MASK 0x000001e0 /* bandwidth control (number
-+ of bytes in a block
-+ transfer, only M2M */
-+#define CTRL_BWC_SHIFT 5
-+
-+#define BWC_FULL 0x0 /* full bandwidth utilized */
-+#define BWC_16 0x1 /* 16 bytes per block */
-+#define BWC_32 0x5
-+#define BWC_64 0x6
-+#define BWC_128 0x7
-+#define BWC_256 0x8
-+#define BWC_512 0x9
-+#define BWC_1024 0xa
-+#define BWC_2048 0xb
-+#define BWC_4096 0xc
-+#define BWC_8192 0xd
-+#define BWC_16384 0xe
-+#define BWC_32768 0xf
-+
-+#define CTRL_PW_MASK 0x00000600 /* peripheral width,
-+ only M2P/P2M */
-+#define CTRL_PW_SHIFT 9
-+
-+#define PW_BYTE 0x0 /* one byte width */
-+#define PW_HALFWORD 0x1 /* 16 bits */
-+#define PW_WORD 0x2 /* 32 bits */
-+#define PW_NOT_USED 0x3
-+
-+#define CTRL_DAH 0x00000800 /* destination address
-+ hold, for M2P */
-+#define CTRL_SAH 0x00001000 /* source address
-+ hold, for P2M */
-+#define CTRL_TM_MASK 0x00006000 /* transfer mode */
-+#define CTRL_TM_SHIFT 13
-+
-+#define TM_M2M 0x0 /* software initiated M2M transfer */
-+#define TM_M2P 0x1 /* memory to ext. peripheral
-+ or IDE/SSP */
-+#define TM_P2M 0x2 /* ext. peripheral or IDE/SSP
-+ to memory */
-+#define TM_NOT_USED 0x3
-+
-+#define CTRL_ETDP_MASK 0x00018000 /* end of transfer/terminal
-+ count pin direction
-+ & polarity */
-+#define CTRL_ETDP_SHIFT 15
-+
-+#define ETDP_ACT_LOW_EOT 0x0 /* pin programmed as active
-+ * low end-of-transfer input */
-+#define ETDP_ACT_HIGH_EOT 0x1 /* active high eot input */
-+#define ETDP_ACT_LOW_TC 0x2 /* active low terminal count output */
-+#define ETDP_ACT_HIGH_TC 0x3 /* active high tc output */
-+
-+#define CTRL_DACKP 0x00020000 /* dma acknowledge pin
-+ polarity */
-+#define CTRL_DREQP_MASK 0x00180000 /* dma request pin polarity */
-+#define CTRL_DREQP_SHIFT 19
-+
-+#define DREQP_ACT_LOW_LEVEL 0x0 /* DREQ is active low, level
-+ sensitive */
-+#define DREQP_ACT_HIGH_LEVEL 0x1 /* active high, level sensitive */
-+#define DREQP_ACT_LOW_EDGE 0x2 /* active low, edge sensitive */
-+#define DREQP_ACT_HIGH_EDGE 0x3 /* active high, edge sensitive */
-+
-+
-+#define CTRL_RSS_MASK 0x00c00000 /* request source selection */
-+#define CTRL_RSS_SHIFT 22
-+
-+#define RSS_EXT 0x0 /* external dma request */
-+#define RSS_SSP_RX 0x1 /* internal SSPRx */
-+#define RSS_SSP_TX 0x2 /* internal SSPTx */
-+#define RSS_IDE 0x3 /* internal IDE */
-+
-+#define CTRL_NO_HDSK 0x01000000 /* no handshake, required for
-+ SSP/IDE, optional for
-+ ext. M2P/P2M */
-+
-+/* interrupt register bits */
-+#define INTR_STALL 0x1
-+#define INTR_DONE 0x2
-+#define INTR_NFB 0x4
-+#define INTR_ALL 0x7
-+
-+/* status register bits */
-+#define STAT_STALL 0x0001 /* waiting for software start
-+ or device request */
-+#define STAT_CTL_STATE_MASK 0x000e /* control fsm state */
-+#define STAT_CTL_STATE_SHIFT 1
-+
-+#define CTL_STATE_IDLE 0x0
-+#define CTL_STATE_STALL 0x1
-+#define CTL_STATE_MEM_RD 0x2
-+#define CTL_STATE_MEM_WR 0x3
-+#define CTL_STATE_BWC_WAIT 0x4
-+
-+#define STAT_BUF_STATE_MASK 0x0030 /* buffer fsm state */
-+#define STAT_BUF_STATE_SHIFT 4
-+
-+#define BUF_STATE_NO_BUF 0x0
-+#define BUF_STATE_BUF_ON 0x1
-+#define BUF_STATE_BUF_NEXT 0x2
-+
-+#define STAT_DONE 0x0040 /* transfer completed successfully
-+ (by device or BCR is 0) */
-+
-+#define STAT_TCS_MASK 0x0018 /* terminal count status */
-+#define STAT_TCS_SHIFT 7
-+
-+#define TCS_NONE 0x0 /* terminal count not reached
-+ for buffer0 and buffer1 */
-+#define TCS_BUF0 0x1 /* terminal count reached
-+ for buffer0 */
-+#define TCS_BUF1 0x2
-+#define TCS_BOTH 0x3 /* terminal count reached
-+ for both buffers */
-+
-+#define STAT_EOTS_MASK 0x0060 /* end of transfer status */
-+#define STAT_EOTS_SHIFT 9
-+
-+#define EOTS_NONE 0x0 /* end of transfer has not been
-+ requested by ext. periph. for
-++ any buffer */
-+#define EOTS_BUF0 0x1 /* eot requested for buffer0 */
-+#define EOTS_BUF1 0x2
-+#define EOTS_BOTH 0x3 /* eot requested for both buffers */
-+
-+#define STAT_NFB 0x0800 /* next frame buffer interrupt */
-+#define STAT_NB 0x1000 /* next buffer status, inform which
-+ buffer is free for update */
-+#define STAT_DREQS 0x2000 /* status of dma request signal from
-+ ext. periph or IDE/SSP request */
-+
-+/* IDE/SSP support */
-+#define IDE_UDMA_DATAOUT 0x20
-+#define IDE_UDMA_DATAIN 0x24
-+
-+#ifndef SSPDR
-+#define SSPDR 0x08
-+#endif
-+
-+struct m2m_channel {
-+ char *name;
-+ void __iomem *base;
-+ int irq;
-+
-+ struct clk *clk;
-+ spinlock_t lock;
-+
-+ void *client;
-+ unsigned next_slot:1;
-+ struct ep93xx_dma_buffer *buffer_xfer;
-+ struct ep93xx_dma_buffer *buffer_next;
-+ struct list_head buffers_pending;
-+};
-+
-+static struct m2m_channel m2m_rxtx[] = {
-+ {"m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0},
-+ {"m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1},
-+ {NULL},
-+};
-+
-+
-+static void feed_buf(struct m2m_channel *ch, struct ep93xx_dma_buffer *buf)
-+{
-+ struct ep93xx_dma_m2m_client *cl = ch->client;
-+ u32 src_addr, dst_addr;
-+
-+ if ((cl->flags & EP93XX_DMA_M2M_DIR_MASK) == EP93XX_DMA_M2M_TX) {
-+ src_addr = buf->bus_addr;
-+ switch (cl->flags & EP93XX_DMA_M2M_DEV_MASK) {
-+ case EP93XX_DMA_M2M_DEV_IDE:
-+ dst_addr = EP93XX_IDE_PHYS_BASE + IDE_UDMA_DATAOUT;
-+ break;
-+ case EP93XX_DMA_M2M_DEV_SSP:
-+ dst_addr = EP93XX_SPI_PHYS_BASE + SSPDR;
-+ break;
-+ default:
-+ dst_addr = buf->bus_addr2;
-+ break;
-+ }
-+ } else {
-+ switch (cl->flags & EP93XX_DMA_M2M_DEV_MASK) {
-+ case EP93XX_DMA_M2M_DEV_IDE:
-+ src_addr = EP93XX_IDE_PHYS_BASE + IDE_UDMA_DATAIN;
-+ break;
-+ case EP93XX_DMA_M2M_DEV_SSP:
-+ src_addr = EP93XX_SPI_PHYS_BASE + SSPDR;
-+ break;
-+ default:
-+ src_addr = buf->bus_addr2;
-+ break;
-+ }
-+ dst_addr = buf->bus_addr;
-+ }
-+
-+ if (ch->next_slot == 0) {
-+ DPRINTK("Writing src_addr: %08x\n", src_addr);
-+ DPRINTK("Writing dest_addr: %08x\n", dst_addr);
-+ DPRINTK("Writing size: %08x\n", buf->size);
-+ writel(src_addr, ch->base + M2M_SAR_BASE0);
-+ writel(dst_addr, ch->base + M2M_DAR_BASE0);
-+ writel(buf->size, ch->base + M2M_BCR0);
-+ } else {
-+ writel(src_addr, ch->base + M2M_SAR_BASE1);
-+ writel(dst_addr, ch->base + M2M_DAR_BASE1);
-+ writel(buf->size, ch->base + M2M_BCR1);
-+ }
-+ ch->next_slot ^= 1;
-+ DPRINTK("data size = %d, slot %d\n", buf->size, ch->next_slot ^ 1);
-+}
-+
-+static void choose_buffer_xfer(struct m2m_channel *ch)
-+{
-+ struct ep93xx_dma_buffer *buf;
-+
-+ ch->buffer_xfer = NULL;
-+ if (!list_empty(&ch->buffers_pending)) {
-+ buf = list_entry(ch->buffers_pending.next,
-+ struct ep93xx_dma_buffer, list);
-+ list_del(&buf->list);
-+ feed_buf(ch, buf);
-+ ch->buffer_xfer = buf;
-+ }
-+}
-+
-+static void choose_buffer_next(struct m2m_channel *ch)
-+{
-+ struct ep93xx_dma_buffer *buf;
-+
-+ ch->buffer_next = NULL;
-+ if (!list_empty(&ch->buffers_pending)) {
-+ buf = list_entry(ch->buffers_pending.next,
-+ struct ep93xx_dma_buffer, list);
-+ list_del(&buf->list);
-+ feed_buf(ch, buf);
-+ ch->buffer_next = buf;
-+ }
-+}
-+
-+static irqreturn_t m2m_irq(int irq, void *dev_id)
-+{
-+ struct m2m_channel *ch = dev_id;
-+ struct ep93xx_dma_m2m_client *cl;
-+ u32 irq_status, dma_state, buf_state, ctl_state;
-+
-+ spin_lock(&ch->lock);
-+ irq_status = readl(ch->base + M2M_INTERRUPT);
-+ /*if ((irq_status & INTR_ALL) == 0) {
-+ spin_unlock(&ch->lock);
-+ return IRQ_NONE;
-+ }*/
-+ dma_state = readl(ch->base + M2M_STATUS);
-+ cl = ch->client;
-+
-+ //printk("intr status: %08x, dma state: %08x\n", irq_status, dma_state);
-+
-+ DPRINTK("intr status %d, dma state %x\n",
-+ irq_status, dma_state);
-+
-+ buf_state = (dma_state & STAT_BUF_STATE_MASK) >> STAT_BUF_STATE_SHIFT;
-+ ctl_state = (dma_state & STAT_CTL_STATE_MASK) >> STAT_CTL_STATE_SHIFT;
-+ /*printk("STAT_CTL_STATE: %d, STAT_BUF_STATE: %d\n",
-+ * ctl_state, buf_state);*/
-+ if (ctl_state == CTL_STATE_STALL &&
-+ buf_state == BUF_STATE_NO_BUF &&
-+ dma_state & STAT_DONE) {
-+ /* transfer completed successfully (done) */
-+
-+
-+ /* send client the done command */
-+ if (cl->buffer_finished) {
-+ cl->buffer_finished(cl->cookie, ch->buffer_xfer, ch->buffer_xfer->size, 0);
-+ }
-+
-+ writel(0, ch->base + M2M_INTERRUPT);
-+ choose_buffer_xfer(ch);
-+ choose_buffer_next(ch);
-+ if (ch->buffer_xfer != NULL) {
-+ /* retrigger if more buffers exist */
-+ if ((cl->flags & EP93XX_DMA_M2M_DEV_MASK) ==
-+ EP93XX_DMA_M2M_DEV_MEM) {
-+ DPRINTK("Writing start1 to M2M control\n");
-+ writel(readl(ch->base + M2M_CONTROL) |
-+ CTRL_START, ch->base + M2M_CONTROL);
-+ readl(ch->base + M2M_CONTROL);
-+ }
-+ } else {
-+ DPRINTK("DISABLING DMA: dreqs state: %d\n", dma_state & STAT_DREQS);
-+
-+ writel(readl(ch->base + M2M_CONTROL)
-+ & ~CTRL_ENABLE, ch->base + M2M_CONTROL);
-+ readl(ch->base + M2M_CONTROL);
-+ }
-+ } else if (ctl_state ==